Power sensitivity of low-voltage CMOS current-mode circuits

This paper proposes an analytical method for analysis of the power sensitivity of low-voltage CMOS current-mode circuits. The power sensitivity is analyzed using the transfer function from the supply voltage to the biasing currents at both low and high frequencies. We show that conventional voltage-mode circuits are sensitive to switching noise and are therefore not particularly suitable for gigabit per second serial links where timing jitter is critical to BER of the links. Current-mode circuits, on the other hand, exhibit much less power sensitivity. We further show that cascode techniques are effective in reducing the power sensitivity of low-voltage CMOS current-mode circuits. Several current-controlled oscillators are implemented using TSMC 0.18 /spl mu/m CMOS technology and analyzed using Spectre with BSIM3.3 device models. Simulation results are presented.