Reconfigurable hardware accelerator for a universal Reed Solomon codec

This paper presents a hardware accelerator for a universal Reed Solomon codec which can be configured to behave as an encoder or decoder for any RS(n, k, t) code with programmable field dimension m. For this purpose a hardware-software codesign approach is followed. A general C implementation of the scheduling for any RS(n, k, t) code which initially configures the accelerator, gives comparable performance to hand-optimized assembly level implementation for a specific RS code on state-of-the-art DSPs supporting Galois field arithmetic. These features facilitate the use of the same accelerator in multiple communication standards and also in different environments, without requiring any manual intervention when the characteristics of the RS code change.