A CMOS inverter model for propagation delay evaluation

A model for the propagation delay and rise (fall) times of an inverter is discussed. The model is based on the approximate analysis of the differential equations that govern the behavior of the inverter. The slopes of the input waveform along with the currents of the pMOS (nMOS) transistor in the falling (rising) outputs are included in the model. Simulations are made using the model for different values of transconductances of transistors, loads, and rise (fall) times. These simulations are compared to the results of SPICE simulations.<>