Three-Level MIS Antifuse Formed by Polarity-Dependent Dielectric Breakdown on 3.5-nm SiO2 for One-Time Programmable Application

A metal–insulator–semiconductor (MIS) antifuse with three stable and highly distinguishable current states obtained by performing dielectric breakdown (BD) under electrical stress with opposite polarities is proposed in this work. For p-type silicon substrate with positive voltage stressed at top metal gate, once the first BD event happens and a conducting percolation path has formed, inversion charge would leak out and the oxide electric field would drop significantly. Consequently, under positive voltage stress (PVS), further BD event would hardly occur and the procedure could therefore be considered as self-protective BD. This results in an intermediate current level, compared with the pristine low current level and the high current level formed by catastrophically oxide BD using negative voltage stress (NVS). The three-level MIS antifuse shows nonvolatile properties with current window larger than
$10^{{8}}\times $
and current margin larger than
$10^{{2}}\times $
when a number of devices are tested, and is also immune to sustained read disturb at ±1 V and write disturb at ±8 V. The proposed device and the idea of forming dielectric BD under opposite polarities for different current states might be beneficial for the future design of one-time programmable (OTP) multilevel memory.