ITER-SIS: Robust Unlimited Sampling Via Iterative Signal Sieving

Unlimited Sampling Framework (USF) is a digital acquisition protocol that recovers high dynamic range (HDR) input signals from their low dynamic range, modulo samples. Current USF theory and algorithms are predominantly focused on bandlimited signal classes that rely on a relatively high sampling rate. Recently, the "Fourier-Prony" algorithm was proposed and validated via hardware experiments with modulo ADCs. It was shown that this algorithm offers competitive performance in the presence of system noise and quantization, especially when periodic boundary conditions are satisfied.In practice, signals are often measured over a finite observation window and this implies leakage in the Fourier domain. Depending on the severity of spectral leakage, Fourier domain algorithms may fail to reconstruct. To overcome this bottleneck, in this paper, we propose an Iterative Signal Sieving Algorithm (ITER-SIS) that solely operates in the time domain. By utilizing a continuous-domain characterization of modulo samples, ITER-SIS achieves a robust, low-sampling-rate, FFT-free recovery of signals with a finite time observation window, even when there is considerable spectral leakage. Hardware experiments with the modulo ADC demonstrate the robustness of our method in a realistic, noisy and low-sampling rate settings, thus validating its high practical utility in a variety of applications.