4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering

Ultra-low-jitter and high-spectral-purity frequency synthesizers are key building blocks for high-performance wireless transceivers and
$\text{FMCW}$
radars. A bang-bang
$\text{PLL} (\text{BBPLL}$
) is an attractive solution thanks to its small footprint and low power consumption; however, its operation in the
$\text{fractional-N}$
mode is hindered by the large quantization error
$(\text{Q-error})$
I caused by the non-integer frequency multiplication saturating the narrow input range of the bang-bang phase detector
$(\text{BBPD})$
. A digital-to-time converter
$(\text{DTC})$
is typically used to cancel the
$\text{Q-error}$
in time domain [1] (Fig. 4.3.1 top-left). Unfortunately, the
$\text{DTC}$
non-linearity can generate significant fractional spurs, thus corrupting the
$\text{PLL}$
spectral purity and integrated jitter. Solutions to this problem rely on either improving the
$\text{DTC}$
linearity or adopting a suitable randomization of the
$\text{Q-error}$
sequence to generate lower spurs in the presence of the
$\text{DTC}$
non-linearity. The constant slope
$\text{DTC} (\text{CS-DTC})$
achieves superior linearity among
$\text{DTC}$
architectures [2], even if further improvements are limited by the voltage sensitivity of current generators
$(\text{CGs})$
and parasitic capacitances as well as by the non-linearity of the digital-to-analog converter
$(\text{DAC})$
adopted in the circuit. On the other hand, those randomization techniques to reduce spurs typically require a larger
$\text{Q-error}$
range [3], [4] that increases
$\text{PLL jitter}$
for two reasons: the higher quantization-noise power and the larger random jitter induced by the wider range needed for the
$\text{DTC}$
. This work introduces a
$9.25-\text{to}-10.5\text{GHz} \text{fractional-N BBPLL}$
achieving
$-71.9\text{dBc}$
fractional spur and a total rms jitter (including spurs) of
$76.7\text{fs}$
at near-integer channels leveraging:
$(\mathrm{i})$
a
$\text{DTC}$
architecture (denoted as
$inverse constant-slope DTC)$
I overcoming the
$\text{CS-DTC}$
limitations and
$(\text{ii})$
a
$\text{Q-error}$
randomization technique (denoted as
$FCW$
subtractive dithering), which keeps the
$\mathrm{Q}- \text{error}$
range constant thus not degrading
$\text{PLL jitter}$
.