10.4 A Rail-to-Rail 12MS 91.3dB SNDR 94.1dB DR Two-Step SAR ADC with Integrated Input Buffer Using Predictive Level-Shifting

Recent years have witnessed the development of high-resolution ADCs >14b utilizing the power-efficient SAR topology at medium speed (1-20MSps) [1–4]. However, high-resolution discrete-time Nyquist ADCs are difficult to drive, especially at high sampling frequencies, due to their large input sampling capacitance required to suppress thermal noise. Standalone general-use buffers are costly since a wide supply-range is needed to maintain linearity across signal swing resulting in low power-efficiency. Integrated driving techniques such as [5] have also been explored although the use of the embedded buffer inside the SAR loop requires each SAR decision trial to resettle through the bandwidth of the buffer, while also requiring a separate larger power supply (2.5V) to accommodate the 1.8V
^pp
signal swing. This work presents the predictive level-shifting integrated driving technique, implemented in a two-step SAR ADC with 3.3V/1.8V supplies, capable of processing rail-to-rail 6.6V
^ppd
input, resulting in a peak SNDR of 91.3dB with a 4MHz input signal at 12MS/s.