A 4nm 32Gb/s 8Tb/s/mm Die-to-Die Chiplet Using NRZ Single-Ended Transceiver With Equalization Schemes And Training Techniques

Recently, the demand for multi-chip solutions, such as chip-on-wafer-on-substrate (CoWoS) and embedded multi-die interconnect bridge (EMIB), is increasing as they reduce chip size and cost for high-performance computing (HPC), artificial intelligence (AI), and big data applications [1]. Following this trend, the industry is establishing standard specifications for die-to-die interfaces, such as Universal Chiplet Interconnet Express (UCle) and Open High-Bandwidth Interface (OpenHBI), and developing various chiplets with high data transmission bandwidth per unit width, low latency, and low power consumption [2–5]. This work implements a die-to-die (D2D) chiplet compatible with the UCle specification using 2.5D packaging technology for die-to-die communication. A transmitter (TX) adopts a reflection-cancellation driver (RCD) that cancels the reflections caused by the impedance mismatch in case of not using an on-die termination of a receiver (RX). Also, a TX clock phase training scheme is implemented to achieve low latency with a synchronous reset generator. As for the RX, a direct decision-feedback equalizer (DFE) combined with a double tail latch compensates for the inter-symbol interference (ISI) while reducing its feedback time even at the high-speed operation. All necessary circuits for the offset calibration, the duty-cycle distortion, and the skew calibration are fully implemented in digital to eliminate static power consumption. This transceiver in 4nm FinFET CMOS technology operates at 32Gb/s/wire with 0.44pJ/b energy efficiency and shows 8Tb/s/mm beach-front bandwidth.