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FORTIFY: Analytical Pre-Silicon Side-Channel Characterization of Digital Designs | IEEE Conference Publication | IEEE Xplore

FORTIFY: Analytical Pre-Silicon Side-Channel Characterization of Digital Designs


Abstract:

Power side-channel attacks are potent security threats that exploit the power consumption patterns of an electronic device to glean sensitive information ranging from sec...Show More

Abstract:

Power side-channel attacks are potent security threats that exploit the power consumption patterns of an electronic device to glean sensitive information ranging from secret keys and passwords to web-browsing activity. While pre-Silicon tools promise early detection of side-channel leakage at the design stage, they require several hours of simulation time. In this paper, we present an analytical framework called FORTIFY that estimates the power side-channel vulnerability of digital circuit designs at signal-level granularity, given the RTL or gate-level netlist of the design, at least 100 times faster than contemporary works. We demonstrate the correctness of FORTIFY by comparing it with a recent simulation-based side-channel leakage analysis framework. We also test its scalability by evaluating FORTIFY on an open-source System-on-Chip.
Date of Conference: 17-20 January 2022
Date Added to IEEE Xplore: 21 February 2022
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Conference Location: Taipei, Taiwan

I. Introduction

Electronic devices are highly vulnerable to a potent form of physical attacks known as power side-channel attacks [1]. These attacks can reveal secrets by analysing the power con-sumption patterns of a device. While the most common ap-plication of side-channel attacks is to steal secret keys from ciphers, the attacks are finding application beyond cryptogra-phy to discover passwords [2], reverse engineer software [3], [4] and Deep Learning algorithms [5], [6], log keystrokes, and fin-gerprint website activity [7]. Thus, there is a critical need to protect systems against power side-channel attacks.

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