Path Based Timing Validation for Timed Asynchronous Design

Timing is an important parameter necessary to ensure the correctness of a design. Timed asynchronous designs can have complex timing paths that include combinational cycles. Commercial electronic design automation (EDA) tools do not support asynchronous designs because timing graphs are required to be acyclic. This paper reports on a methodology that enables commercial tools to support full cyclic path timing validation of timed asynchronous designs.

I. Introduction

Scaling has revolutionized circuit design, allowing designs to be produced with over four billion transistors on a single chip. This capability is enabled with commercial electronic design automation (EDA) tools which are continuously enhanced to handle more complex circuits and technology nodes. With the increasing complexity of circuit design, obeying timing is a challenge. Commercial EDA tools offer well developed static timing analysis (STA) algorithms to validate timing constraints on clocked systems represented as a directed acyclic graph (DAG) [1].