Abstract:
Timing is an important parameter necessary to ensure the correctness of a design. Timed asynchronous designs can have complex timing paths that include combinational cycl...Show MoreMetadata
Abstract:
Timing is an important parameter necessary to ensure the correctness of a design. Timed asynchronous designs can have complex timing paths that include combinational cycles. Commercial electronic design automation (EDA) tools do not support asynchronous designs because timing graphs are required to be acyclic. This paper reports on a methodology that enables commercial tools to support full cyclic path timing validation of timed asynchronous designs.
Published in: 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID)
Date of Conference: 04-08 January 2016
Date Added to IEEE Xplore: 17 March 2016
Electronic ISBN:978-1-4673-8700-2
Electronic ISSN: 2380-6923