Abstract:
Stress optimization for memory devices is a complex process due to the continuous space of possible optimization values for relevant parameters. This paper uses a method ...Show MoreMetadata
Abstract:
Stress optimization for memory devices is a complex process due to the continuous space of possible optimization values for relevant parameters. This paper uses a method based on electrical Spice simulation to perform this optimization process for DRAM devices. The paper presents a case-study performed in Qimonda to optimize the timing and temperature stresses for the strap problem in defective memory cells. The paper also considers the impact of bit line coupling effects on the faulty behavior and identifies the worst case coupling background needed to detect the faulty cells.
Published in: 2009 4th International Design and Test Workshop (IDT)
Date of Conference: 15-17 November 2009
Date Added to IEEE Xplore: 02 February 2010
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