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0.13um 32Mb/64Mb embedded DRAM core with high efficient redundancy and enhanced testability | IEEE Conference Publication | IEEE Xplore

0.13um 32Mb/64Mb embedded DRAM core with high efficient redundancy and enhanced testability


Abstract:

This paper describes the 32Mb and the 64Mb embedded DRAM core with high efficient redundancy, which is fabricated using 0.13µm triple-well 4-level Cu embedded DRAM techno...Show More

Abstract:

This paper describes the 32Mb and the 64Mb embedded DRAM core with high efficient redundancy, which is fabricated using 0.13µm triple-well 4-level Cu embedded DRAM technology. The core size of 18.9mm2and the cell efficiency of 51.3% for the 32Mb capacity, the core size of 33.4mm2and the cell efficiency of 58.1% for the 64Mb capacity are realized. This core can be achieved 230MHz burst access at 1.0V power supply condition adopting data bus architecture merged shift column redundancy. We implemented 4 test functions to improve the testability of embedded DRAM core. It realizes DRAM core test in a logic test environment.
Date of Conference: 18-20 September 2001
Date Added to IEEE Xplore: 01 August 2005
Conference Location: Villach, Austria

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