Showing 1-25 of 11,123 resultsfor "Index Terms":Nanoscale devices
"Index Terms":Nanoscale devices
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This recommended practice provides a definition, terminology, conceptual model, and standard metrics for ad hoc network communication at the nanoscale. The physical properties of nanoscale communication extend human-engineered networking in ways beyond that defined in existing communication standards including in vivo, sub-cellular medical communication, smart materials and sensing at the molecula...Show More
This recommended practice provides a definition, terminology, conceptual model, and standard metrics for ad hoc network communication at the nanoscale. The physical properties of nanoscale communication extend human-engineered networking in ways beyond that defined in existing communication standards including in vivo, sub-cellular medical communication, smart materials and sensing at the molecula...Show More
This recommended practice provides a definition, terminology, conceptual model, and standard metrics for ad hoc network communication at the nanoscale. The physical properties of nanoscale communication extend human-engineered networking in ways beyond that defined in existing communication standards including in vivo, sub-cellular medical communication, smart materials and sensing at the molecula...Show More
The Impact of Nanoscale CMOS Devices Scaling and Variations on mm-Wave CMOS Performance
2024 19th European Microwave Integrated Circuits Conference (EuMIC)
Year: 2024 | Conference Paper |
The impact of nanoscale CMOS devices scaling and variations as well as layout dependent effects (LDE) on high frequency performance appears as the most critical challenge to nanoscale devices optimization and modeling for mm-Wave and Sub-THz CMOS circuits simulation and design. This paper presents an extraordinary finding in sub-60 nm devices which can exactly meet the foundry golden die target in...Show More
Investigation on the Impact of Program/Erase Cycling Frequency on Data Retention of Nanoscale Charge Trap Nonvolatile Memory
IEEE Electron Device Letters
Cited by: Papers (2)
This letter presents a detailed study to investigate the impact of program/erase (P/E) cycling frequency on threshold voltage (Vt) instability of nanoscale nitride-based charge trap nonvolatile memory (NB-CTNVM) devices. Post-P/E cycled Vt instability was found to exacerbate with higher P/E cycling frequency, which resulted in lower activation energy (Ea). The Ea obtained is 30% higher than those ...Show More
Network device technologies for ubiquitous IT in the 21st century
Digest of Papers. Microprocesses and Nanotechnology 2001. 2001 International Microprocesses and Nanotechnology Conference (IEEE Cat. No.01EX468)
Year: 2001 | Conference Paper |
Cited by: Papers (1)
Summary form only given. We discuss progress and prospects of network device technologies for ubiquitous communication systems in the 21st century. Broadband and mobile/wireless networks will remove various bottlenecks which block the way to the ubiquitous information society. After a brief overview of the direction toward ubiquitous information technologies, we discuss the technology roadmap with...Show More
Organic Electronic Device Modeling at the Nanoscale
2006 IEEE/ACM International Conference on Computer Aided Design
Year: 2006 | Conference Paper |
Electronic devices with nanoscale features (~ 100 nm or smaller) are becoming increasingly important in electronics technology. While nanoscale electronic devices comprise a variety of different material sets and structures, many of the nanoscale devices developed in the last decade employ organic materials. In this talk, we discuss the modeling of organic electronic thin film devices. In our appr...Show More
This review investigates the possibility of using Machine Learning as a replacement for numerical TCAD device simulation. As the chip design is getting complex to incorporate more and more functionality in the devices, many chipmakers started exploring advanced techniques of machine learning to get rid of some big challenges faced by IC industry. In Machine learning, advanced algorithms are utiliz...Show More
Excellent Selector Characteristics of Nanoscale \hbox{VO}_{2} for High-Density Bipolar ReRAM Applications
Myungwoo Son;Joonmyoung Lee;Jubong Park;Jungho Shin;Godeuni Choi;Seungjae Jung;Wootae Lee;Seonghyun Kim;Sangsu Park;Hyunsang Hwang
We herein present a nanoscale vanadium oxide (\hbox{VO}_{2}) device with excellent selector characteristics such as a high on/off ratio (> 50), fast switching speed ( \hbox{10}^{6}\ \hbox{A/cm}^{2}). Owing to extrinsic defects, a large-area device with a 20-nm-thick \hbox{VO}_{2} layer underwent an electrical short. In contrast, after scaling the dev...Show More
Partial-Coupled Mode Space for quantum transport simulation in nanoscale double-gate MOSFETs
2010 International Conference on Microelectronics
Year: 2010 | Conference Paper |
Cited by: Papers (2)
A novel computationally efficient approach for simulation of quantum transport in nanoscale devices is proposed. The idea is based on partial coupling between the modes of the nanoscale device. The proposed approach, termed Partial-Coupled Mode Space (PCMS), is applied to the double-gate MOSFETs and device targets from the ITRS roadmap were simulated. A Comparison with the fully Coupled-Mode Space...Show More
Subthreshold Swing Performance Assessment of Nanoscale Junctionless GAA FETs using Machine Learning Approach
2024 21st International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE)
Year: 2024 | Conference Paper |
In this work, the current-voltage (I-V) characteristics of nanoscale Junctionless Gate-All-Around (JLGAA) Field-Effect Transistor (FET) structures, with and without high-k dielectric materials, were investigated using the ATLAS 2D simulator. Various machine learning (ML) algorithms were employed to analyze and classify the design factors influencing one of the principal electrical parameters of th...Show More
Terahertz-capability nanoscale InGaAs HEMT design guidelines by means of full-band Monte Carlo device simulations
Diego Guerra;Fabio A. Marino;R. Akis;David K. Ferry;Stephen M. Goodnick;Marco Saraniti
2011 IEEE 11th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems
Year: 2011 | Conference Paper |
We provide design guidelines for InGaAs HEMT nanoscale scaling from the analysis of results obtained through our full band Cellular Monte Carlo simulator. In particular, improved RF performance can be obtained preserving a minimum aspect ratio of 5, limiting in such way short channel effects and reducing the electron transit time through the reduction of the effective gate length. Further improvem...Show More
A definition, terminology, conceptual model, and standard metrics for ad hoc network communication at the nanoscale are provided. Human-engineered networking is extended by the physical properties of nanoscale communication in ways beyond that defined in existing communication standards. These include in vivo, sub-cellular medical communication, smart materials and sensing at the molecular level, ...Show More
A set of YANG modules describing nanoscale communication systems and their associated physical quantities in conformance with IEEE Std 1906.1-2015--a common framework for all nanoscale communication technologies--are comprised by this data model. Physics unique to the nanoscale are represented by the model. The physics are referred to as non-standard, required by IEEE Std 1906.1-2015. Remote confi...Show More
A set of YANG modules describing nanoscale communication systems and their associated physical quantities in conformance with IEEE Std 1906.1-2015--a common framework for all nanoscale communication technologies--are comprised by this data model. Physics unique to the nanoscale are represented by the model. The physics are referred to as non-standard, required by IEEE Std 1906.1-2015. Remote confi...Show More
A set of YANG modules describing nanoscale communication systems and their associated physical quantities in conformance with IEEE Std 1906.1-2015--a common framework for all nanoscale communication technologies--are comprised by this data model. Physics unique to the nanoscale are represented by the model. The physics are referred to as non-standard, required by IEEE Std 1906.1-2015. Remote confi...Show More
Device engineering and CMOS integration of nanoscale memristors
2014 IEEE International Symposium on Circuits and Systems (ISCAS)
Year: 2014 | Conference Paper |
Cited by: Papers (4)
Our group focuses on developing better nanoscale memristor with improved performance, understanding the underlying device physics, and exploring new applications for this novel device. This paper introduces our recent work on memristor device engineering and CMOS integration. We have fabricated the smallest memristors (8 nm × 8 nm) in a crossbar array, with each of the device consumes orders of ma...Show More
Working Principles of a DRAM Cell Based on Gated-Thyristor Bistability
Halid Mulaosmanovic;Giovanni M. Paolucci;Christian Monzio Compagnoni;Niccòl Castellani;Gianpietro Carnevale;Paolo Fantini;Domenico Ventrice;Andrea L. Lacaita;Alessandro S. Spinelli;Augusto Benvenuti
IEEE Electron Device Letters
Cited by: Papers (28)
This letter discusses the working principles of a memory cell exploiting the bistability of a single nanoscale gated-thyristor to achieve high-performance DRAM operation (T-RAM cell). The device relies on the possibility to reach either of the two stable states of the thyristor by means of a fast low-to-high gate switch and depending on the amount of holes in the gated p -base. In particular,...Show More
Nanoscale Surface Roughness Effects on THz Vacuum Electron Device Performance
Diana Gamzina;Hanyan Li;Logan Himes;Robert Barchfeld;Branko Popovic;Pan Pan;Rosa Letizia;Mauro Mineo;Jinjun Feng;Claudio Paoloni;Neville C. Luhmann
Vacuum electron devices are the most promising solution for the generation of watt-level power at millimeter wave and terahertz frequencies. However, the three-dimensional nature of metal structures required to provide an effective interaction between an electron beam and THz signal poses significant fabrication challenges. At increasing frequency, losses present a serious detrimental effect on pe...Show More
Molecular communications, where molecules are used to encode, transmit, and receive information, are a promising means of enabling the coordination of nanoscale devices. The paradigm has been extensively studied from various aspects, including channel modeling and noise analysis. Comparatively little attention has been given to the physical design of molecular receiver and transmitter, envisioning...Show More
Whole-chip ESD protection strategy for CMOS integrated circuits in nanotechnology
Proceedings of the 2001 1st IEEE Conference on Nanotechnology. IEEE-NANO 2001 (Cat. No.01EX516)
Year: 2001 | Conference Paper |
On-chip electrostatic discharge (ESD) protection circuits are built in IC chips to protect the devices and circuits against ESD damage. But, ESD protection circuits constructed with scaled-down CMOS devices are very susceptible to ESD stress. Therefore, novel ESD protection solutions must be developed to overcome this reliability challenge for integrated circuits fabricated in nano-scale CMOS tech...Show More
Technology Platform for IC Design in Nano-scale CMOS
2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings
Year: 2006 | Conference Paper |
Cited by: Papers (1)
This paper discusses the technology platform development for IC design in nano-CMOS technologies. New effects and issues in nano-CMOS are reviewed before the discussion on the contents of the technology platform. Some key components are briefly discussed with the exploration of some further challenges to develop a RF SOC design technology platform. An advanced technology platform with strong links...Show More
Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology
Chun-Yu Lin;Pin-Hsin Chang;Rong-Kun Chang;Ming-Dou Ker;Wen-Tai Wang
2015 IEEE 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits
Year: 2015 | Conference Paper |
A vertical silicon-controlled rectifier (SCR) structure utilizing ESD implantation layer was proposed and implemented in nanoscale CMOS technology. Compared with the traditional SCR structure, the proposed structure has lower trigger voltage and high enough ESD protection capability. Therefore, the proposed structure was suitable for ESD protection in nanoscale CMOS process.Show More
Security primitive design with nanoscale devices: A case study with resistive RAM
2016 International Great Lakes Symposium on VLSI (GLSVLSI)
Year: 2016 | Conference Paper |
Cited by: Papers (5)
Inherent stochastic physical mechanisms in emerging nonvolatile memories (NVMs), such as resistive random-access-memory (RRAM), have recently been explored for hardware security applications. Unlike the conventional silicon Physical Unclonable Functions (PUFs) that are solely based on manufacturing process variation, RRAM has some intrinsic randomness in its physical mechanisms that can be utilize...Show More
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