<![CDATA[ IEEE Transactions on Very Large Scale Integration (VLSI) Systems - new TOC ]]>
http://ieeexplore.ieee.org
TOC Alert for Publication# 92 2018April 26<![CDATA[Table of contents]]>265C1C4406<![CDATA[IEEE Transactions on Very Large Scale Integration (VLSI) Systems]]>265C2C2114<![CDATA[The Cat and Mouse in Split Manufacturing]]>2658058172766<![CDATA[Robust Design-for-Security Architecture for Enabling Trust in IC Manufacturing and Test]]>2658188302459<![CDATA[Performance Evaluation and Optimization of HBM-Enabled GPU for Data-Intensive Applications]]>$1.63times $ speedup on an HBM-enabled GPU compared with the best high-performance GPU in market, and the two optimization techniques for the BFS algorithm make it at most $24.5times $ ($9.8times $ and $2.5times $ for each technique, respectively) faster than conventional implementations.]]>2658318401856<![CDATA[Adaptive Precision Cellular Nonlinear Network]]>2658418542626<![CDATA[Aging Management Using a Reconfigurable Switch Network for Arrays of Nonideal Power Cells]]>2658558663559<![CDATA[Hardware Implementation of Iterative Method With Adaptive Thresholding for Random Sampling Recovery of Sparse Signals]]>$32 times 32$ , the IMAT implementation using WHT provides the reconstruction time of $185~mu text{s}$ and the dynamic power of 123 mW.]]>2658678772773<![CDATA[Toward an Energy-Efficient High-Voltage Compliant Visual Intracortical Multichannel Stimulator]]>$mu text{A}$ per channel. The microelectrode array driver is able to deliver 20 V per anodic or cathodic phase across the microelectrode–tissue interface for ±13 V power supplies. The MED supplies different current levels with the maximum value of 400 $mu text{A}$ per input and 100 $mu text{A}$ per output channel simultaneously to 8–16 stimulation sites through microelectrodes, connected either in bipolar or monopolar configuration. Both chips receive power via inductive link and data through capacitive coupling. The SG and MED chips have been fabricated in 0.13-$mu text{m}$ CMOS and 0.8-$mu text{m}$ 5-/20-V CMOS/double-diffused metal-oxide-semiconductor technologies. The measured dc power budgets consumed by low- and mid-voltage chips are 2.56 and 2.1 mW consecutively. The system, modular in architecture, is interfaced with a newly developed platinum-coated pyramidal microelectrode array. In vitro test r-
sults with 0.9% phosphate buffer saline show the microelectrode impedance of 70 $text{k}Omega $ at 1 kHz.]]>2658788918208<![CDATA[A Single-Stage Direct-Conversion AC–DC Converter for Inductively Powered Application]]>$mu text{m}$ standard CMOS process. Measurement results show that a peak power transfer efficiency of 93.48% is achieved at a regulated output voltage of 2 V in an output power range of 2–80 mW.]]>2658929023095<![CDATA[A New Fast-Response Current-Mode Buck Converter With Improved <inline-formula> <tex-math notation="LaTeX">$I^{2}$ </tex-math></inline-formula>-Controlled Techniques]]>$I^{2}$ -controlled techniques is presented in this paper. First, the proposed converter uses the improved $I^{2}$ -controlled techniques to design a new current-mode buck converter. The current-sensing circuit can fully sense the inductor current. The sensing current is divided into two paths; one is flown through the dynamic-acceleration circuit, and the other is transferred to hysteretic comparator to compare with dynamic-acceleration output. The $I^{2}$ -controlled techniques increase the bandwidth of the converter’s closed-loop gain that will speed up the converter’s transient response. Second, the converter uses the phase–frequency-controlled techniques to lock the switching frequency of the adaptive on-time generator of the proposed converter and reduce the difficulty of the output filter. Third, the circuit does not need slope compensation, so that it is very simple to implement. Fourth, the proposed buck converter was implemented with TSMC 0.35-$mu text{m}$ CMOS 2P4M processes, which is a low-cost process. The experimental results show that the maximum load current can be up to 600 mA, the input voltage range is 2.6–4 V, the output voltage is regulated at 1.8 V, the maximum power efficiency is up to 90%, and the transient response times are 2.5 and $2.8~mu text{s}$ at rising and falling edges, respectively.]]>2659039113121<![CDATA[Fast and Accurate Emissivity and Absolute Temperature Maps Measurement for Integrated Circuits]]>2659129232187<![CDATA[A Hardware-Efficient Synchronization in L-DACS1 for Aeronautical Communications]]>$L$ -band digital aeronautical communication system type-1 (L-DACS1) is an emerging standard that aims at enhancing air traffic management by transitioning the traditional analog aeronautical communication systems to the superior and highly efficient digital domain. L-DACS1 employs modern and efficient orthogonal frequency-division multiplexing (OFDM) modulation technique to achieve more efficient and higher data rate in comparison to the existing aeronautical communication systems. However, the performance of OFDM systems is very sensitive to synchronization errors such as symbol timing offset (STO) and carrier frequency offset (CFO). STO and CFO estimations are extremely important for maintaining orthogonality among the subcarriers for the retrieval of information. This paper proposes a novel efficient hardware synchronizer for L-DACS1 systems that offers robust performance at low power and low hardware resource usage. Monte Carlo simulations show that the proposed synchronization algorithm provides accurate STO estimation as well as fractional CFO estimation. Implementation of the proposed synchronizer on a widely used field-programmable gate array (FPGA) (Xilinx xc7z020clg484-1) results in a very low hardware usage which consumed 6.5%, 3.7%, and 6.4% of the total number of lookup tables, flip-flops, and digital signal processing blocks, respectively. The dynamic power of the proposed synchronizer is below 1 mW.]]>2659249322030<![CDATA[A 0.9–2.25-GHz Sub-0.2-mW/GHz Compact Low-Voltage Low-Power Hybrid Digital PLL With Loop Bandwidth-Tracking Technique]]>2659339446844<![CDATA[A Concurrent Dual-Band and Dual-Mode Frequency Synthesizer for Radar Systems]]>$times1.675$ mm and consumes a dc power of 67 mW from a supply voltage of 1.2 V.]]>2659459574291<![CDATA[An Electrical Model for Nanometer CMOS Device Stress Effect in Design and Simulation of Analog Reference Circuits]]>2659589682452<![CDATA[Fast Electromigration Stress Evolution Analysis for Interconnect Trees Using Krylov Subspace Method]]>FastEM, is based on the finite-difference method which is used to first discretize the PDEs into linear time-invariant ordinary differential equations (ODEs). After discretization, a modified Krylov subspace-based reduction technique is applied in the frequency domain to reduce the size of the original system matrices so that they can be efficiently simulated in the time domain. The FastEM can perform the simulation process for both void nucleation and void growth phases under piecewise constant linear current density inputs and time-varying stressing temperatures. Furthermore, we show that the steady-state response of stress diffusion equations can be obtained from the resulting ODE system in the frequency domain, which agrees with the recently proposed voltage-based EM analysis method for EM immortality checks. Numerical results show that the proposed method can lead to about 1–2 orders of magnitude speed-up over existing finite-difference time-domain-based methods on large interconnect trees for both void nucleation and growth phases with negligible errors. We further show that for most of the interconnect trees tested; we only need a small number of dominant -
oles for sufficient accuracy.]]>2659699802419<![CDATA[A Source and Channel Coding Approach for Improving Flash Memory Endurance]]>2659819901560<![CDATA[Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications]]>$0~rightarrow ~1$ and $1~rightarrow ~0$ single node upsets, with the increased read/write access time.]]>265991994747<![CDATA[High Dynamic Performance Current-Steering DAC Design With Nested-Segment Structure]]>$2.7times$ fewer multiplexers compared with the reported DEM DACs, while achieving comparable dynamic performance. Fabricated in 130-nm CMOS process, the proposed 12-bit 100-MS/s DAC occupies 0.21 mm^{2}. Measurement results show that $1.9times$ integral nonlinearity reduction ratio and 15.5-dB SFDR improvement from 46.6 to 62.1 dB at near Nyquist frequency are achieved.]]>2659959991825<![CDATA[Current Optimized Coset Coding for Efficient RRAM Programming]]>265100010041206<![CDATA[IEEE Transactions on Very Large Scale Integration (VLSI) Systems]]>265C3C367