<![CDATA[ IEEE Transactions on Circuits and Systems I: Regular Papers - new TOC ]]>
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TOC Alert for Publication# 8919 2019September05<![CDATA[Table of contents]]>669C1C4150<![CDATA[IEEE Transactions on Circuits and Systems—I:Regular Papers publication information]]>669C2C2144<![CDATA[Guest Editorial Special Issue on the 2019 International Symposium on Integrated Circuits and Systems]]>6693253325328<![CDATA[Short-Range Quality-Factor Modulation (SQuirM) for Low Power High Speed Inductive Data Transfer]]>${mu }m$ CMOS. The circuits were capable of reliably transceiving data at speeds of up to 50.4 Mbps, with a BER of $< 4.5 times 10^{-10}$ , and a transmitter energy consumption of 8.11 pJ/b.]]>669325432653533<![CDATA[Analysis and Design of Ultra-Large Dynamic Range CMOS Transimpedance Amplifier With Automatically-Controlled Multi-Current-Bleeding Paths]]>$1.26times 1.33$ mm^{2} also integrates level shifter, post-amplifier, buffer, DC offset cancellation (DCOC), bandgap reference (BGR), and low-dropout regulator (LDO). With a single 3.3-V external supply voltage, the fully integrated TIA in $0.11~mu text{m}$ CMOS achieves a measured input dynamic range up to 7.4 mA@2.5 Gb/s, an input referred noise as low as 137.3 nA and a differential trans-impedance gain of 10 $text{k}Omega $ . Taking the bandwidth, dynamic range, and trans-impedance gain into account, the fabricated CMOS TIA demonstrates the largest input dynamic range with maintaining competitive comprehensive performance.]]>669326632783305<![CDATA[A Wideband dB-Linear VGA With Temperature Compensation and Active Load]]>2. The measurement results show the proposed VGA has a dB-linear gain-control range from −37dB to 14 dB with an error within 0.65 dB. The −3dB bandwidth of the VGA is 740 MHz and is nearly constant when the gain varies. The core VGA circuit consumes about 2.49 mW. The proposed design features wide bandwidth, small chip area, and low power consumption.]]>669327932873624<![CDATA[An Optically-Powered 432 MHz Wireless Tag for Batteryless Internet-of-Things Applications]]>$mu text{m}$ CMOS process. The measurement results demonstrate that the proposed charge pump provides a 1.1 to 1.3 V hysteresis regulated voltage under indoor light illumination larger than 300 lux. The charge pump achieves 84.1% peak efficiency and the communication distance of 3 meters is demonstrated while only consuming $248~mu text{W}$ .]]>669328832953734<![CDATA[An Integrated Discrete-Time Delay-Compensating Technique for Large-Array Beamformers]]>669329633063375<![CDATA[A 0.12-mm<sup>2</sup> 1.2-to-2.4-mW 1.3-to-2.65-GHz Fractional-N Bang-Bang Digital PLL With 8-<inline-formula> <tex-math notation="LaTeX">$mu$ </tex-math></inline-formula>s Settling Time for Multi-ISM-Band ULP Radios]]>2. The settling time measures $8~mu text{s}$ at an 82-MHz initial frequency error.]]>669330733162875<![CDATA[A 2.2-GHz 3.2-mW DTC-Free Sampling <inline-formula> <tex-math notation="LaTeX">$DeltaSigma$ </tex-math></inline-formula> Fractional-<inline-formula> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> PLL With −110-dBc/Hz In-Band Phase Noise and −246-dB FoM and −83-dBc Reference Spur]]>$Delta Sigma $ fractional-$N$ phase-locked loop (PLL) without a digital-to-time converter (DTC), whose design is challenging and requires complex calibration. A linear slope generator (LSG) is employed to generate a linear waveform, which has a large linear phase-to-voltage conversion range. Instead of modulating the reference signal by the DTC, phase dithering is performed at the feedback path through the combination of the LSG and a multi-modulus divider (MMDIV) with multi-phase generation. The reference signal then directly samples the linear LSG output waveform to output a sampled voltage corresponding linearly to the resulting phase error. All these enable the sampling phase detector to handle large phase dither step provided by a phase interpolator (PI), thus eliminating the need for the DTC and the associated calibration. This 2.2-GHz PLL achieves −246-dB FoM with an in-band phase noise of −110 dBc/Hz and −82-dBc reference spur while consuming only 3.2 mW in a 130-nm CMOS process.]]>669331733293700<![CDATA[A 0.0018-mm<sup>2</sup> 153% Locking-Range CML-Based Divider-by-2 With Tunable Self-Resonant Frequency Using an Auxiliary Negative-<inline-formula> <tex-math notation="LaTeX">$g_{{m}}$ </tex-math></inline-formula> Cell]]>$g_{m}$ (NG) cell is inserted between the resonated shunt-peaking inductor and the load resistor to shift the divider’s sensitivity curve (SC), enabling concurrently a higher operating frequency and a wider LR. We also use the injection-locking concept, together with a graphical phasor diagram with the frequency-phase information, to systematically explain the LR-extension mechanism. Prototyped in a 65-nm CMOS, the divider occupies a tiny active area of 0.0018 mm^{2}. The measured LR is 153% (4–30 GHz) while consuming 4.06–4.28 mW at 30 GHz under a single 1.2-V supply. The performance corresponds to two figure of merits: FOM$_{mathbf {Pdc}}$ of 25.5 dB and FOM$_{P}$ of 71.5, both compare favorably with the state of the art.]]>669333033394482<![CDATA[A Spectrum-Sensing DPD Feedback Receiver With <inline-formula> <tex-math notation="LaTeX">$30times$ </tex-math></inline-formula> Reduction in ADC Acquisition Bandwidth and Sample Rate]]>669334033513488<![CDATA[A 27.7 fJ/conv-step 500 MS/s 12-Bit Pipelined ADC Employing a Sub-ADC Forecasting Technique and Low-Power Class AB Slew Boosted Amplifiers]]>2 and consumes 18.16 mW from a 1.1 V supply, resulting in a figure of merit (FOM) of 22.4 and a 27.7 fJ/conversion-step at low-frequency and Nyquist frequency, respectively.]]>669335233643127<![CDATA[A 4-b 7-<inline-formula> <tex-math notation="LaTeX">$mu$ </tex-math></inline-formula>W Phase Domain ADC With Time Domain Reference Generation for Low-Power FSK/PSK Demodulation]]>$7~mu text{W}$ from a 1-V supply. It leads to a 1.36-pJ/conversion-step Walden Figure of Merit at Nyquist input (FoM@Nyquist).]]>669336533721974<![CDATA[A 13-Bit 260MS/s Power-Efficient Pipeline ADC Using a Current-Reuse Technique and Interstage Gain and Nonlinearity Errors Calibration]]>669337333834411<![CDATA[A 10-MHz BW 77.9 dB SNDR DT MASH <inline-formula> <tex-math notation="LaTeX">$Delta!Sigma$ </tex-math></inline-formula> ADC With NC-VCO-Based Quantizer and OPAMP Sharing]]>$0.18~mu text{m}$ CMOS process for wide band applications. A noise-coupled voltage-controlled oscillator (VCO)-based quantizer is used to achieve second or higher order of noise shaping. This structure is power and area efficient as well as simple to implement, since it consists mostly of digital blocks. A 2–2 MASH modulator has been implemented by employing the NC-VCO-based quantizer as the second stage. This helps to overcome the VCO nonlinearity issue, since it only processes the quantization error of the first stage, and improve the dynamic range (DR). The first stage is implemented as a second-order modulator in modified feedback (CIFB) architecture. It consists of two integrators and a 4-bit quantizer. For enhanced power efficiency, opamp sharing is used between the second integrator of the first stage and the adder of second stage. The adder is used to extract the quantization error and also to implement the second stage. The prototype ADC achieves a peak SNDR and SNR of 77.9 and 79.1 dB, respectively, over a 10-MHz bandwidth with a 160-MHz sampling rate. The total power consumption including output buffers, is 19.6 mW from 1.8 V/1.5 V supplies, resulting in Walden and Schreier figures-of-merit of 152 fJ/Conv and 168 dB, respectively.]]>669338433922138<![CDATA[Design Considerations for Low-Distortion Filter and Oscillator ICs for Testing High-Resolution ADCs]]>$mu text{m}$ CMOS process. Band-pass filter prototypes with center frequencies of 1 and 10 kHz have 60 dB attenuation at the second harmonic, THD < −115 dBc while driving 10 V_{ppd} output, and 44 $mu text{V}$ rms output noise. The oscillator prototype can generate 1 or 10 kHz and has THD < −115 dBc while driving 8 V_{ppd} output. Distortion generation mechanisms in the filter and oscillator are analyzed. The nonlinearity of the output stage of the opamp used in the active filter coupled with the capacitance at the input of that stage is shown to be the main cause of nonlinearity. This is suppressed using a buffer between the first and the second stage of the opamp. The modulation of the oscillator’s loss due to ripple in the output of the amplitude stabilization loop that is required for stable sinusoidal oscillations turns out to be a significant contributor to distortion. A four-phase full-wave rectifier combined with second-order ripple filtering minimizes this effect. The filters occupy 11mm^{2} and consume 65 mW from 5.6 V. The oscillator occupies 8.5 mm^{2} and consumes 50 mW from 5 V. Measured frequency and amplitude stability over 166 min are 0.95 mHz (17.3 mHz) and 91 $mu text{V}$ (45 $mu text{V}$ ) at 1 kHz (10 kHz).]]>669339334016012<![CDATA[An Integrated Micromachined Thermopile Sensor With a Chopper Interface Circuit for Contact-Less Temperature Measurements]]>$text{k}Omega $ output resistance, and 0.64-mm^{2} active absorbing area. The interface circuit, fabricated in a standard 130-nm CMOS process, employs chopper technique in order to provide amplification of the sensor output signal, which behaves substantially as a DC while minimizing offset and noise contributions at low frequency. Given the sensor characteristics, a single-ended architecture was preferred over the most straightforward fully-differential approach. The interface circuit reduces the offset by a factor 255, achieving an input referred offset standard deviation equal to 1.365 $mu text{V}$ , measured across 29 samples. The thermopile sensor and the interface circuit, integrated in two separate test-chips, were characterized and extensively measured both as stand-alone devices and together as a system to perform contact-less temperature measurements. Adding a metal cap to the thermopile sensor in order to reduce the environmental noise, a measurement accuracy of approximately ±0.2 °C was obtained, thus verifying the system suitability for human body temperature detection.]]>669340234135503<![CDATA[A Supply-Noise-Insensitive Digitally-Controlled Oscillator]]>$90times 210,,mu text{m},,^{mathrm{ 2}}$ area and consumes 2.25 mW operating over a range of 0.9–1.4 GHz output frequency. At 850 Mv-supply voltage, the frequency pushing of DCO is zero at the optimal point and remains less than 10% over a large excursion of 50 mV_{pp}. When embedded into an all-digital phase locked loop, closed-loop measurements demonstrate that supply noise with 50 mV_{pp}magnitude does not impact the loop dynamics.]]>669341434226407<![CDATA[A Low-Noise, Positive-Input, Negative-Output Voltage Generator for Low-to-Moderate Driving Capacity Applications]]>$800~mu text{A}$ for the regulated output voltage at −3.0, −1.5, and 1.5 V, respectively. The measured steady-state ripple is under 3 mV_{PP}, while the noise voltage at the charge-pump operating frequency harmonics is below 130 $mu text {V}_{mathrm{ rms}}$ and the noise floor is under $5~mu text {V}_{mathrm{ rms}}$ . The design is also the application verified with a gallium nitride power amplifier, thus further confirming its low-noise performance. Implemented in CMOS 180-nm process, the prototype chip occupies an area of 0.55 mm^{2}.]]>669342334367815<![CDATA[An Efficient, Wide-Output, High-Voltage Charge Pump With a Stage Selection Circuit Realized in a Low-Voltage CMOS Process]]>$0.18~mu text{m}$ 1.8 V/3.3 V CMOS process. The proposed stage selection circuit changes the node voltages in the charge pump circuit in a domino effect to ensure that the maximum voltages across the terminals of each transistor are kept within the normal supply voltage ($text{V}_{mathrm {DD}}$ ). The stage selection circuit is able to bypass or activate each stage of the charge pump. Experimental results indicate that the proposed charge pump provides a wide-output voltage range: 3.3–12.6 V from a 3.3 V input source. A peak efficiency of 70% was reached in the charge pump at a current loading of 3.5 mA. By selecting the optimal number of active stages, the overall power efficiencies can be greater than 60% under the output voltages of 4.8 V, 8.1 V, and 10.8 V, respectively. By optimizing the number of active stages, an increase of up to 35% power efficiency can be gained. The proposed stage selection circuit is applicable to other on-chip wide-output charge-pumps.]]>669343734445236<![CDATA[Low-Voltage Current and Voltage Reference Design Based on the MOSFET ZTC Effect]]>$mu text{m}$ CMOS technology operable from 1.3 V is presented. To further explore the possibilities of this approach, a voltage reference with a nominal supply voltage of just 0.5 V is designed and fabricated in a 130-nm technology. Measurement results are given for both circuits.]]>669344534563307<![CDATA[A 0.7-V 28-nW CMOS Subthreshold Voltage and Current Reference in One Simple Circuit]]>$mu text{m}$ CMOS process, the proposed VCR circuit takes an active area of only 0.055 mm^{2}. The measured voltage and current references ($text{V}_{mathrm {ref}}$ and $text{I}_{mathrm {ref}}$ ) at room temperature are 368 mV and 9.77 nA, respectively. The measured average temperature coefficient (TC) of $text{V}_{mathrm {ref}}$ and $text{I}_{mathrm {ref}}$ are 43.1 ppm/°C and 149.8 ppm/°C over a temperature range of −40~125°C with one-time trimming and the variation coefficients are 0.35% and 1.6%, respectively. The measured voltage and current line sensitivities are 0.027%/V and 0.6%/V, respectively. The minimum supply voltage is 0.7 V with a total power consumption of 28 nW. The measured power supply ripple rejection (PSRR) of $text{V}_{mathrm {ref}}$ is −65 dB @DC and −39.4 dB at frequencies higher than 1 Hz.]]>669345734663014<![CDATA[Accurate and Fast On-Wafer Test Circuitry for Device Array Characterization in Wafer Acceptance Test]]>$60~mu text{m}$ by $800~mu text{m}$ which is small enough to be placed into the scribe line on wafers as conventional WAT circuitry is. Measurement results demonstrate the proposed design’s efficiency and capability of revealing local process variations.]]>669346734792366<![CDATA[WRA: A 2.2-to-6.3 TOPS Highly Unified Dynamically Reconfigurable Accelerator Using a Novel Winograd Decomposition Algorithm for Convolutional Neural Networks]]>$1.7times $ –$24times $ speedup compared with the previous FPGA-based designs.]]>669348034934585<![CDATA[A 124 fJ/Bit Cascode Current Mirror Array Based PUF With 1.50% Native Unstable Bit Ratio]]>$3.23~mu text{m}^{2}$ (i.e. 764 ${F}^{2}$ ) for each PUF cell, the proposed PUF implementation is validated using 65-nm standard CMOS process. The excellent randomness of the proposed PUF design is verified based on the test results with widely-accepted auto-correlation function and NIST suites. Meanwhile, the PUF’s uniqueness is measured with 10 chip prototypes and reported to be 49.94%. In addition, the fabricated PUF chips were also characterized with various environmental influences. With multiple readout (500 times) under the reference operating temperature of 27 °C and supply voltage of 1.2 V, the native unstable bit ratio is measured to be as low as 1.50%, which can be further improved to 0.79% by adopting the mainstream temporal majority voting (TMV)-based error correction scheme. Besides, we also evaluate the fabricated PUF chips’ reliability under varied operating temperature from −40 °C to 120 °C and supply voltage from 0.95 to 1.3 V-
The averaged bit error rate (BER) per 10 °C and BER per 0.1 V are measured to be 0.86% and 1.02%, respectively. Compared with the state-of-the-art implementations, the reliability figure of merit (RFoM) is improved by $1.16sim 4.29times $ , with the influences of the temporal noise, the temperature/supply voltage variations and their ranges comprehensively considered.]]>669349435034490<![CDATA[An Ultra-Low-Power Dual-Mode Automatic Sleep Staging Processor Using Neural-Network-Based Decision Tree]]>$mu text{W}$ NN-based automatic sleep staging processor is realized. The dual-mode NN models are trained by an open-source large-scale dataset. The default mode achieves 81.0% classification accuracy based on two signals of one electroencephalography (EEG) signal and one electromyography (EMG) signal, and the compact mode achieves 78.5% accuracy based on only one EEG signal. In addition, the proposed design was verified using the National Taiwan University Hospital (NTUH) dataset, for which 81.1% and 77.1% accuracy is achieved in the default and the compact modes, respectively. A prototype chip using a 180-nm CMOS process occupies a total area of 11.74 mm^{2} and operates at 10 KHz while consuming 4.96 $mu text{W}$ at 1.2 V.]]>669350435165628<![CDATA[Ultra-Low Complex Blind I/Q-Imbalance Compensation]]>669351735302531<![CDATA[Maximizing the Data Rate of an Inductively Coupled Chip-to-Chip Link by Resetting the Channel State Variables]]>$times1.5$ mm planar inductors separated by 0.5 mm in a 0.18 $mathrm {mu m}$ CMOS process. 500 Mb/s data rate is achieved over a link which has a band-pass bandwidth of 185 MHz.]]>669353135434354<![CDATA[A Systematic Design Methodology for Optimization of Sigma-Delta Modulators Based on an Evolutionary Algorithm]]>$Sigma Delta $ Ms), different variables need to be optimized together in order to maximize the performance. This design task has the added difficulty of dealing with the non-linear behavior of the quantizer. Although a linearized model of the quantizer can be used, this may result in significant discrepancies between the predicted and actual behavior of the $Sigma Delta text{M}$ . To better predict the behavior of a given design, we propose a design methodology for $Sigma Delta $ Ms based on a genetic algorithm (GA) that uses both linear equations and simulations. In order to reduce the computation time, the design solution is initially evaluated using equations and only if the performance is deemed good enough, it is subjected to a more refined simulation. This more precise simulation takes into account thermal noise, finite output swing, and gain (among other non-idealities) of the building blocks of the modulator. Moreover, Monte Carlo (MC) analyses are performed during the optimization in order to assess the sensitivity to component variations of the solutions. In order to demonstrate the validity and robustness of the proposed optimization methodology, several $Sigma Delta $ Ms designs are presented, together with the corresponding measured results.]]>669354435564273<![CDATA[Analytical Equivalent Circuit Extraction Procedure for Broadband Scalable Modeling of Three-Port Center-Tapped Symmetric On-Chip Inductors]]>${pi }$ equivalent circuit model for three-port on-chip inductors from a given S-parameter dataset. The compact model provides an accurate fit over a wide frequency range from dc to beyond the self-resonance frequency (SRF) to a tabular input ${S}$ -parameter model describing a symmetric center-tapped on-chip inductor. The input dataset may be obtained from a measurement or from an electromagnetic field solver simulation. Using a passive broadband equivalent circuit instead of the original ${S}$ -parameters’ description is advantageous for circuit design, as it facilitates the convergence of transient simulations. The proposed approach carefully considers center-tap parasitics. Hence, the obtained equivalent circuit model fits the input inductor characteristics accurately not only for differential excitation but also in the common-mode and single-ended operation. Due to the fact that the proposed extraction approach is based on physical assumptions and analytical circuit decomposition, the obtained component values are physically meaningful and relate to geometry. Thus, this approach is suitable for the generation of scalable compact models, which can be used to speed-up inductor optimization during the RF circuit design. The proposed methodology has been verified on a three-port inductor realized in a 28-nm CMOS technology and measured up to 60 GHz. The extracted equivalent circuit model exhibits an accurate fit to the measured data over the entire frequency range in all operation modes. Finally, field-solver models are used to verify the scalability.]]>669355735703314<![CDATA[An LDPC-Coded SCMA Receiver With Multi-User Iterative Detection and Decoding]]>$4times 6$ and $8times 12$ SCMA systems. The proposed MU LDPC decoder has a 57.1% lower hardware complexity than the direct-mapped design that is achieved through hardware sharing and memory access scheduling. Designed in a 40-nm CMOS technology, the SCMA receiver integrates 10.9M logic gates in an area of $3.382times 3.382$ mm^{2}. The proposed design achieves a gross throughput of 1.198 Gb/s and 599 Mb/s for $8times 12$ and $4times 6$ SCMA systems, respectively, under a practical situation. It dissipates 813 mW at a clock frequency of 300 MHz from a 0.9-V supply.]]>669357135843216<![CDATA[A <inline-formula> <tex-math notation="LaTeX">$4times64$ </tex-math></inline-formula> MIMO Detector for Generalized Spatial Modulation Systems]]>$4 times 64$ GSM-MIMO systems with two active antennas using TSMC 40-nm CMOS technology. The synthesis and post-layout simulation results show that the proposed GSM-MIMO detection chip achieves a better normalized throughput, hardware efficiency, and energy efficiency than a previous SM-MIMO detector chip.]]>669358535973307<![CDATA[An 86% Efficiency, Wide-V<inline-formula> <tex-math notation="LaTeX">$_{in}$ </tex-math></inline-formula> SIMO DC–DC Converter Embedded in a Car-Radio IC]]>$text{V}_{bat}$ ), the SIMO converter generates three regulated output voltages: $text{V}_{bat}+6.5$ V boost, 4.5 V buck, and 1.8 V floating around half $text{V}_{bat}$ . A novel, reconfigurable power-stage is conceived and switched appropriately to generate the unique floating output among others. Regulated floating dual-slope (RFDS) drivers are proposed to limit the di/dt through the switches and to reduce the switching-noise. A continuous-time (CT) error-processor is implemented to generate the control-phases. The circuit withstands the 4–40 V range of car-battery variations and regulates in the 4.5–27 V range while remaining in the idle-state outside. The SIMO converter is embedded in a car-radio IC and fabricated in a 110-nm BCD process. The switching frequency is 2.4 MHz. The SIMO converter offers a peak power-efficiency of 86% at 2.7 W of output power and occupies an active area of 2.5 mm^{2}. The operating temperature range is −40°C to +150°C. In a 4-channel car-radio, the proposed SIMO converter reduces the quiescent power-dissipation by up to 36% while having negligible effect on the audio performance.]]>669359836094771<![CDATA[A Fast-Transient-Response Fully-Integrated Digital LDO With Adaptive Current Step Size Control]]>2 including an on-chip output capacitor of 1nF. The measured undershoot and overshoot voltages are only 53 and 37 mV, respectively, when the load current changes between 0 and 100 mA. The quiescent current is 34.6 $mu text{A}$ , while the maximum current efficiency is 99.96%.]]>669361036192970<![CDATA[A Single-Stage Dual-Output Tri-Mode AC-DC Regulator for Inductively Powered Application]]>$0.18~mu text{m}$ CMOS process. It delivers a maximum output power of 114mW. The measured peak power conversion efficiency is 91.7% at dual regulated output voltages of 1.8V and 2V.]]>669362036303884<![CDATA[A Ripple Reduction Method for Switched-Capacitor DC–DC Voltage Converter Using Fully Digital Resistance Modulation]]>2. The measurement results show that the SCVC prototype with the proposed FDRM technique achieves an averaged ripple reduction of 31.6% and a peak conversion efficiency of 88.96% under a loading range of 95–190 $mu text{A}$ .]]>669363136415841<![CDATA[IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors]]>66936423642112<![CDATA[IEEE Circuits and Systems Society Information]]>669C3C3138