<![CDATA[ IEEE Transactions on Circuits and Systems I: Regular Papers - new TOC ]]>
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TOC Alert for Publication# 8919 2018October 22<![CDATA[Table of contents]]>6511C1C4197<![CDATA[IEEE Transactions on Circuits and Systems—I:Regular Papers publication information]]>6511C2C2112<![CDATA[Guest Editorial Special Issue on the 2018 International Symposium on Integrated Circuits and Systems]]>65113605360569<![CDATA[A 0.19 mm<sup>2</sup> 10 b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS]]>boosting-capacitor-sharing technique to enhance the compactness of the time-interleaved bootstrapped sampling front-end, which is particularly critical when omitted the time calibration in this design. Measurement results on a 65 nm CMOS prototype operated at 2.3 GS/s and 1.2 V supply show 31 mW total power consumption with a SNDR of 47.4 dB @Nyquist leading to a FOM of 69 fJ/conv.step.]]>6511360636163338<![CDATA[A 18.5 nW 12-bit 1-kS/s Reset-Energy Saving SAR ADC for Bio-Signal Acquisition in 0.18-<inline-formula> <tex-math notation="LaTeX">$mu$ </tex-math></inline-formula>m CMOS]]>2. At a 1.5-V supply voltage and a 1-kS/s sampling-rate with the electrocardiogram signal input, the ADC power consumption could be reduced to 18.5 nW, corresponding to 71% power saving, and owing to the proposed techniques from a conventional SAR ADC consuming 63.5 nW.]]>6511361736273390<![CDATA[A 2-MS/s, 11.22 ENOB, Extended Input Range SAR ADC With Improved DNL and Offset Calculation]]>pp-d (±1.33 V_{REF}). The circuit also includes a comparator offset compensation technique that results in a residual offset of less than 0.5 LSB. The chip has been designed and implemented in a 0.13-μm CMOS process and demonstrates the state-of-the-art performance, featuring an SNDR of 69.3 dB and the SFDR of 79 dB without requiring any calibration. Total power consumption of the ADC is 0.9 mW, with a measured differential non-linearity of 1.2/-1.0 LSB and INL of 2.3/-2.2 LSB.]]>6511362836382729<![CDATA[A 0.6-V 10-bit 200-kS/s SAR ADC With Higher Side-Reset-and-Set Switching Scheme and Hybrid CAP-MOS DAC]]>$mu text{m}$ CMOS technology, showing an SNDR/SFDR of 56.43 dB/71 dB at 90-kHz input, under a 0.6-V power supply, while consuming $1.01~mu text{W}$ at 200 kS/s for a figure of merit of 9.32 fJ/conv.-step. The ADC occupies only a small active area of 0.0675 mm^{2}.]]>6511363936503073<![CDATA[Reset-Free Memoryless Delta–Sigma Analog-to-Digital Conversion]]>$M$ -band decimation filter running at the oversampled rate. It is also shown that a delta–sigma ADC preceded by a sample-and-hold at the Nyquist rate is a linear, time-invariant system at the Nyquist rate. This relaxes the constraint on the STF and allows using a multi-rate decimation filter and an equalizer at the Nyquist rate to significantly lower the power in the digital filters. Crosstalk suppression, which is limited by analog imperfections when a fixed-coefficient equalizer is used, is shown to be substantially improved using an adaptive equalizer at the Nyquist rate. A 180-nm prototype operating at 32 MHz and an OSR of 32 demonstrates two-channel operation with crosstalk below 89 dB. It consumes 18.2 mA from a 1.8-V supply, occupies 3.86 mm^{2} and has DR/SNR/SNDR of 84.2/82.5/80.1 dB.]]>6511365136613329<![CDATA[Continuous-Time Delta-Sigma Modulators Based on Passive RC Integrators]]>$Delta Sigma $ Ms) are discussed. These techniques are based on increasing the contribution of the 1-bit comparator to the loop gain by using passive RC integrators together with low gain amplifiers in the $Delta Sigma text{M}$ loop filter. A third-order CT $Delta Sigma text{M}$ is designed using these techniques to demonstrate their validity, and it achieves 27.5 fJ/conv.-step of energy efficiency. Due to the many design issues, such as the tradeoff between RC variations and loop stability, the design of this modulator has been optimized using a genetic algorithm. The 65-nm CMOS $Delta Sigma text{M}$ occupies only $0.013~mathrm {mm^{2}}$ , dissipates 256 $mu text{W}$ from a 0.7-V supply and it achieves a peak SNDR of 69.1 dB in a 2-MHz bandwidth. The dynamic range reaches 76.2 dB, which corresponds to a $mathrm {FoM_{Schreier}}$ of 175.1 dB.]]>6511366236745050<![CDATA[A 0.9-V 100-<inline-formula> <tex-math notation="LaTeX">$mu$ </tex-math></inline-formula>W Feedforward Adder-Less Inverter-Based MASH <inline-formula> <tex-math notation="LaTeX">$DeltaSigma$ </tex-math></inline-formula> Modulator With 91-dB Dynamic Range and 20-kHz Bandwidth]]>$Delta Sigma $ modulator integrated into a 0.18-$mu text{m}$ CMOS technology for digitizing signals in low-power devices is presented in this paper. To do so, a cascade (multistage noise shaping) architecture based on an adder-less feedforward structure is proposed. The proposed modulator has a unity signal transfer function in both stages of the modulator in order to reduce the integrator’s output swings. To mitigate the failure of slow process corner in the weak inversion as well as to further diminish the power consumption of the presented modulator, a fully differential self- and bulk-biased inverter-based operational transconductance amplifier is proposed. Experimental results are shown to demonstrate the efficiency of the proposed $Delta Sigma $ converter, showing state-of-the-art performance, by featuring 88.7-dB signal-to-noise ratio, 86.4-dB signal-to-noise plus distortion ratio, and 91-dB dynamic range within a signal bandwidth of 20 kHz, with a power dissipation of $103.4~mu text{W}$ when the circuit is clocked at 5.12 MHz.]]>6511367536875194<![CDATA[A 12-bit Multi-Channel R-R DAC Using a Shared Resistor String Scheme for Area-Efficient Display Source Driver]]>$mu$ m standard CMOS technology. Compared with the conventional RRDAC, the proposed design showed a 15% reduction in size, a DNL of 0.49 LSB and an output voltage deviation of 9. 3mV for eight different chips. Also, the area per channel was 0.0465 mm^{2}.]]>6511368836973476<![CDATA[A 4-Channel 12-Bit High-Voltage Radiation-Hardened Digital-to-Analog Converter for Low Orbit Satellite Applications]]>$mu text{m}$ Bi-CMOS technology to achieve the functionality across a wide-temperature range from −55 °C to 125 °C. In this paper, an R-2R resistor network is adopted in the DAC to provide necessary resistors matching which improves the DAC precision and linearity with both the global common centroid and local common centroid layout. Therefore, no additional, complicated digital calibration or laser-trimming are needed in this design. The experimental and measurement results show that the maximum frequency of the single-chip four-channel 12-bit R-2R ladder high-voltage radiation-tolerant DAC is 100 kHz, and the designed DAC achieves the maximum value of differential non-linearity of 0.18 LSB, and the maximum value of integral non-linearity of −0.53 LSB at 125 °C, which is close to the optimal DAC performance. The performance of the proposed DAC keeps constant over the whole temperature range from −55 °C to 125 °C. Furthermore, an enhanced radiation-hardened design has been demonstrated by utilizing a radiation chamber experimental setup. The fabricated radiation-tolerant DAC chipset occupies a die area of 7 mm $times7$ mm in total including pads (core active area of 4 mm $times5$ mm excluding pads) and consumes less than 525 mW, output voltage ranges from −10 to +10 V.]]>6511369837062859<![CDATA[Missing-Code-Occurrence Probability Calibration Technique for DAC Nonlinearity With Supply and Reference Circuit Analysis in a SAR ADC]]>6511370737193581<![CDATA[A 25-Gb/s 270-mW Time-to-Digital Converter-Based <inline-formula> <tex-math notation="LaTeX">$8{times}$ </tex-math></inline-formula> Oversampling Input-Delayed Data-Receiver in 45-nm SOI CMOS]]>2 of active silicon area. The proposed receiver offers one of the highest time-resolution and oversampling factor, and among the best energy conversion figures compared with the oversampling time-mode receiver architectures reported so far.]]>6511372037334902<![CDATA[An On-Chip Self-Characterization of a Digital-to-Time Converter by Embedding it in a First-Order <inline-formula> <tex-math notation="LaTeX">$DeltaSigma$ </tex-math></inline-formula> Loop]]>$Delta Sigma $ time-to-digital converter with self-calibration is proposed and implemented in TSMC 28-nm CMOS. The system is self-contained, and only one digital clock is needed for the measurements. A system self-calibration algorithm is proposed to calibrate nonlinearities of the analog circuitry. The operation is robust over PVT variations since the delay information is normalized to the input clock period. To verify the proposed idea, two different digital-to-time converters performing the on-chip delay are measured and analyzed at 50-MHz clocking frequency with 0.65-ps standard time deviation per measurement.]]>6511373437442608<![CDATA[A Mixed-Signal Circuit Technique for Cancellation of Interferers Modulated by LO Phase-Noise in 4G/5G CA Transceivers]]>6511374537553461<![CDATA[An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with −55 dBc Fractional and −91 dBc Reference Spurs]]>2.]]>6511375637684910<![CDATA[Operational Transconductance Amplifier With Class-B Slew-Rate Boosting for Fast High-Performance Switched-Capacitor Circuits]]>6511376937792565<![CDATA[Class-J SiGe <inline-formula> <tex-math notation="LaTeX">$X$ </tex-math></inline-formula>-Band Power Amplifier Using a Ladder Filter-Based AM–PM Distortion Reduction Technique]]>$p_{1,text {dB}}$ is 19 dBm. The AM-PM distortion at $p_{1,text {dB}}$ is 5 degrees.]]>6511378037893646<![CDATA[A 0.12–0.4 V, Versatile 3-Transistor CMOS Voltage Reference for Ultra-Low Power Systems]]>$V_{T}$ ) difference of the two NMOS transistors that compose it. Reverse short-channel and narrow-width effects are explored to obtain such $V_{T}$ difference while using the same type of transistor. Ultra-low power operation and low line sensitivity is achieved by biasing the SCM with a zero-$V_{T}$ (native) transistor, also leading to an area efficient design. To show its versatility, three versions of the proposed circuit were fabricated in a standard 0.13-$mu text{m}$ CMOS process. Measurement performed over five samples showed an average temperature coefficient of 150–1500 ppm/°C. Minimum supply voltages of 0.12–0.4 V was observed while providing reference voltages around tens of mV. The proposed circuits consume 0.33–50 pW at room temperature and minimum supply voltage. The occupied area for any version is less than 0.0012 mm^{2}.]]>6511379037992380<![CDATA[A Fully Integrated Analog Front End for Biopotential Signal Sensing]]>$mu text{m}$ CMOS process. The supply voltage is 1.2 V and the quiescent current is $7.7~mu text{A}$ . Measurement results show that the analog front end achieves an in-band gain of 58 dB, a noise spectrum density of 46nV/$sqrt {text{Hz}} $ and can tolerate ±60 mV electrode offset. The THD is below 1% with a 2mV_{pp} input. The analog signal is converted to digital code at 5kS/s by a 12-bit SAR ADC with 63.2 dB SNDR. The prototype IC is experimented with capturing ECG on human beings.]]>6511380038093248<![CDATA[A High Frame Rate Wearable EIT System Using Active Electrode ASICs for Lung Respiration and Heart Rate Monitoring]]>p-p output, a voltage buffer for EIT and heart rate signal recording as well as contact impedance monitoring, and a sensor buffer that provides multi-parameter sensing. The ASIC was designed in a CMOS 0.35-$mu text{m}$ high-voltage process technology. It operates from ±9 V power supplies and occupies a total die area of 3.9 mm^{2}. The EIT system has a bandwidth of 500 kHz and employs two parallel data acquisition channels to achieve a frame rate of 107 frames/s, the fastest wearable EIT system reported to date. Measured results show that the system has a measurement accuracy of 98.88% and a minimum EIT detectability of 0.86 $Omega $ /frame. Its successful operation in capturing EIT lung respiration and heart rate biosignals from a volunteer is demonstrated.]]>6511381038204680<![CDATA[A CMOS Temperature Sensor With Versatile Readout Scheme and High Accuracy for Multi-Sensor Systems]]>$mu text{m}$ CMOS process, the proposed temperature sensor occupies a silicon area of 0.29 mm^{2} and draws a current of $95~mu text{A}$ from a 2 to 3.6 V supply voltage at the room temperature. Measured results show that the proposed design has the inaccuracy of ± 0.47 °C ($3sigma $ ) from −40 °C to 125 °C after a single-point temperature calibration. It achieves a resolution of 16 mK at a conversion time of 5.12 ms and a supply sensitivity of less than 0.05 °C/V. Thanks to the versatile readout scheme, the proposed temperature sensor is compatible with multi-sensor systems where the readout-circuitry can be shared between different input signals.]]>6511382138292209<![CDATA[An Analog CMOS Silicon Photomultiplier Using Perimeter-Gated Single-Photon Avalanche Diodes]]>$18 times 18$ pixel analog PGSPAD-based CMOS silicon photomultiplier (SiPM). The noise model is derived using theories of carrier thermal generation, carrier diffusion, and inter-band tunneling. Parameters are derived using fabricated PGSPAD devices and model validity is verified with experimental measurements. The designed PGSPAD SiPM is implemented in standard $0.5~mu text{m}$ 2-poly, 3-metal CMOS process, and is characterized for dark current, sensitivity, and signal-to-noise ratio (SNR) throughout the visible spectral range for varying bias voltages. Models show that the reduction of dark events in the PGPSAD is primarily caused by a reduction in band-to-band tunneling. Thus, as a function of the applied gate voltage the PGPSAD shows an improvement of SNR over a range of 1 to 1150. The sensitivity of the presented SiPM is $1.06 times 10^{3}$ A/W/cm^{2}. The designed PGSPAD SiPM shows great promise over standard SiPM for applications, such as neutron detection which requires high sensitivities and high SNRs.]]>6511383038412837<![CDATA[A Low-Power Vision System With Adaptive Background Subtraction and Image Segmentation for Unusual Event Detection]]>$104times 104$ pixels vision chip consumes $80~mu text{W}$ at 30 frames/s, while segmentation dramatically cuts down the amount of data to be transferred, resulting in an extremely low-power system suitable for embedded applications.]]>6511384238532396<![CDATA[Asynchronous Spiking Pixel With Programmable Sensitivity to Illumination]]>6511385438633150<![CDATA[A Low Power Diode-Clamped Inverter-Based Strong Physical Unclonable Function for Robust and Lightweight Authentication]]>$V_{text {dd}}$ point. The spread of the Gaussian is broadened by mixing it with another Gaussian distributed trip point obtained from a diode-clamped parallel inverter stage. As the main entropy of the raw response bits is derived from a mono-stable circuit, it has greater immunity to perturbances introduced by operating environments. In addition, as the mono-stable state for the output voltage is a non-linear combination of individual inverter rings, the resilience against machine learning attacks can be improved. The prototype chip was fabricated using a commercial 40-nm CMOS technology. The measurement results show that the power consumption of the 64-bit mono-stable PUF is merely $3.85~mu text{W}$ . The native bit error rate is <8% at 0.9 ~ 1.3 V and −40~ 90°C, which can be further reduced to <1% using the proposed thresholding technique. The proposed PUF reduces the accuracy of support vector machine and reliability-based covariance matrix adaptation evolution strategy attacks by $36{times}$ and $75{times}$ , respectively, over that of arbiter PUF.]]>6511386438732634<![CDATA[TEL Logic Style as a Countermeasure Against Side-Channel Attacks: Secure Cells Library in 65nm CMOS and Experimental Results]]>6511387438842480<![CDATA[A Standard-Cell-Based All-Digital PWM Modulator With High Resolution and Spread- Spectrum Capability]]>6511388538963053<![CDATA[Real-Time Embedded Machine Learning for Tensorial Tactile Data Processing]]>6511389739062226<![CDATA[HTD: A Light-Weight Holosymmetrical Transition Detector for Wide-Voltage-Range Variation Resilient ICs]]>$V_{mathrm {TH}}$ (0.474 V)/super-$V_{mathrm {TH}}$ (1.1 V) operation, as compared with the baseline design. Therefore, our proposed HTD-based resilient technique can improve the energy efficiency of circuits by almost eliminating all the timing margins.]]>6511390739173432<![CDATA[A Hardware-Scalable DSP Architecture for Beam Selection in mm-Wave MU-MIMO Systems]]>2, while dissipating 44 mW at 266 MHz in an MU-MIMO system with 16 beams and 8 users.]]>6511391839282697<![CDATA[Adaptive Learning-Based Compressive Sampling for Low-power Wireless Implants]]>$8{times}$ to $64{times }$ , with a high reconstruction performance, as qualitatively demonstrated on a human data set. Two different versions of the encoder have been designed and tested, one with and the second without the adaptive compression, requiring an area of $230{times }235,,mu text{m}$ and $200times 190,,mu text{m}$ , respectively, while consuming only 0.47 $mu text{W}$ at 0.8 V. The system is powered by a 4-coil inductive link with measured power transmission efficiency of 36%, while the distance between the external and internal coils is 10 mm. Wireless data communication is established by an OOK modulated narrowband and an IR-UWB transmitter, while consuming 124.2 pJ/bit and 45.2 pJ/pulse, respectively.]]>6511392939414589<![CDATA[Design and Implementation of Flexible and Reconfigurable SDF-Based FFT Chip Architecture With Changeable-Radix Processing Elements]]>2 basis of single-path delay feedback FFT and up to 18 various changeable radixes of FFT processing. A design technique of switchable FIFO usage approach is developed to efficiently manage FIFO arrangement for 48 FFT modes. In addition, a design technique of coarse and fine rotating is designed to effectively reduce twiddle-factor circuit area. By using TSMC 40-nm CMOS technology, an FFT ASIC implementation only has a core area occupation of 0.414 mm^{2} and consumes 49.8 mW in average at maximal working frequency of 526.32 MHz. This innovative design work is competitive as compared to current state-of-the-art works, especially in terms of circuit area cost and power/energy performance evaluation.]]>6511394239554651<![CDATA[All-Digital Transmitter Architecture Based on Two-Path Parallel 1-bit High Pass Filtering DACs]]>$Delta Sigma $ -modulator is used. Since the modulator also converts the input resolution to 1-bit, an inherently-linear digital-to-analog conversion is realized by embedding filtering in the DAC. Furthermore, the finite impulse response DAC transfer function is designed to cancel the $Delta Sigma $ -modulator quantization noise. Simulation results at system level demonstrate the robustness of the architecture against random coefficient mismatches, and its suitability for broadband transmissions. The error vector magnitude of the quadrature output is simulated for up to 15% random coefficient mismatch and it maintains a value below −22 dB even when the input signal bandwidths vary from 20 MHz (64-subcarrier OFDM) to 160 MHz (512-subcarrier OFDM). Experimental results are presented to discuss the validity of the proposed all-digital transmitter architecture and to highlight the challenges of implementing it in advanced CMOS nodes.]]>6511395639696744<![CDATA[High-Performance Switched-Capacitor Boost–Buck Integrated Power Converters]]>6511397039832962<![CDATA[A 220-MHz Bondwire-Based Fully-Integrated KY Converter With Fast Transient Response Under DCM Operation]]>2 and achieves an output conversion range of 1.5-2 V from a 1.2-V input. The measured peak efficiency is 75.2% at 97.5 mW. With a 500-ps rising/falling time of the load current step (56 mA), the undershoot/overshoot is 245/205 mV at 146-/140-ns recovery time, and the dc-dc converter achieves a settling time per load transient step of 2.6 ns/mA, which is competitive with the state-of-the-art boost converters.]]>6511398439952862<![CDATA[A Current-Accuracy-Enhanced Wide-Input-Range DC–DC LED Driver With Feedforward Synchronous Current Control]]>6511399640062651<![CDATA[A Dual-Output Switched Capacitor DC–DC Buck Converter Using Adaptive Time Multiplexing Technique in 65-nm CMOS]]>$350~mu text{A}$ and 1–$10~mu text{A}$ at load voltages of 1 and 0.55 V, respectively. The DOSC circuit is fabricated in 65-nm CMOS, and it occupies an active area of 0.27 mm^{2}. Measured results show that a peak efficiency of 78% is achieved at a load power of $300~mu text{W}$ .]]>6511400740162733<![CDATA[Nano-Ampere Low-Dropout Regulator Designs for IoT Devices]]>2, respectively. Measurement results show that LDO1 and LDO2 consume 30 and 100 nA quiescent current, respectively, with 1 V input, 0.8 V output, and 100 nA load current. Stability analysis shows that both LDOs achieve good stability with load current ranging from 100 nA to 10 mA. With the load current steps from 100 nA to 10 mA in 1-$mu text{s}$ transition time, the measured voltage undershoots are 336.8 mV for LDO1 and 196 mV for LDO2. Therefore, we reach a figure-of-merit of 0.00159 ps.]]>6511401740265307<![CDATA[A Fully on-Chip Digitally Assisted LDO Regulator With Improved Regulation and Transient Responses]]>$mu text{m}$ CMOS technology. The maximum load current is 150 mA, the output voltage is 1 V, and the dropout voltage is 0.2 V. The load regulation is 0.17 mV/mA, which is more than 480% improved over the traditional design without digital assistance.]]>6511402740342713<![CDATA[IEEE Transactions on Circuits and Systems - I:Regular Papers information for authors]]>65114035403572<![CDATA[Introducing IEEE Collabratec]]>6511403640362097<![CDATA[IEEE Circuits and Systems Society Information]]>6511C3C3107