<![CDATA[ IEEE Transactions on Circuits and Systems I: Regular Papers - new TOC ]]>
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TOC Alert for Publication# 8919 2019February 21<![CDATA[Table of contents]]>663C1C4180<![CDATA[IEEE Transactions on Circuits and Systems—I:Regular Papers publication information]]>663C2C2109<![CDATA[Improving Receiver Close-In Blocker Tolerance by Baseband <inline-formula> <tex-math notation="LaTeX">$G_m-C$ </tex-math></inline-formula> Notch Filtering]]>6638858963427<![CDATA[An On-Chip Built-in Linearity Estimation Methodology and Hardware Implementation]]>2 architecture achieves notching at specific programmable frequency points. To estimate the filter linearity, two-tone test signals are injected, and the spectrum power of the DT filter’s output is measured by a power detector. By changing the sampling frequency, the DT filter can switch between the normal operation mode, which allows the two test tones to pass through, or the tone suppression mode, which notches the two test tones and exposes the IM3 tone power. The proposed on-chip linearity estimation methodology is experimentally verified. A comparison between the power measured in the proposed two modes reveals how well is the filter linearity. The proposed baseband chain is fabricated in 130-nm standard CMOS technology, occupying a 0.146-mm^{2} silicon area. Measurement results shows a suppression of 55 dB on the test tone power.]]>6638979082680<![CDATA[A 1-MHz-Bandwidth Gm-C-Based Quadrature Bandpass Sigma-Delta Modulator Achieving −153.7-dBFS/Hz NSD With Background Calibration]]>$Delta Sigma$ ) modulator for Internet-of-Things applications. In the presented $Delta Sigma $ modulator, a reconfigurable full-scale input amplitude assists the $Delta Sigma $ modulator, achieving a wide dynamic range (DR) and a low-noise floor. A following system-level supply voltage and temperature background tracking technique stabilizes the frequency response of the Gm-C-based quadrature bandpass $Delta Sigma $ modulator. Furthermore, the 1.5-bit feedback current DAC employs a PN-based semi-self-swapping logic to relax the matching requirement. The prototype $Delta Sigma $ modulator was fabricated in a 180-nm CMOS process with an active area of 0.28 mm^{2}. The $Delta Sigma $ modulator achieves a total DR of 93.7 dB with the reconfigurable full-scale input amplitude, resulting in a noise spectral density of −153.7 dBFS/Hz with a bandwidth of 1 MHz. The presented $Delta Sigma $ modulator consumes 2.0 mW with a power supply of 1.8 V and a sampling frequency of 32 MHz.]]>6639099193058<![CDATA[Clock Jitter Analysis of Continuous-Time <inline-formula> <tex-math notation="LaTeX">$SigmaDelta$ </tex-math></inline-formula> Modulators Based on a Relative Time-Base Projection]]>$Sigma Delta $ modulators. In this paper, we present the basic theory of this technique and its application to some practical examples, showing a good matching between prediction and numerical simulation.]]>6639209293118<![CDATA[Pixel Optimizations and Digital Calibration Methods of a CMOS Image Sensor Targeting High Linearity]]>$mu text{m}$ , 1-poly, and 4-metal CIS technology with a pixel array of $128 times 160$ is used to verify these linearity improvement techniques. The measurement results show that the proposed CTIA pixel has the best linearity result out of all pixel structures. Meanwhile, the proposed calibration methods further improved the linearity of the CIS without changing the pixel structure. The pixel mode method achieves the most significant improvement on the linearity. One type of 4T pixel attains a nonlinearity of 0.028% with pixel mode calibration, which is two times better than the state of the art. Voltage mode (VM) and current mode (CM) calibration methods get rid of the limitation on the illumination condition during calibration operation; especially, CM calibration can further suppress the nonlinearity caused by the integration capacitor $C_{textit {FD}}$ on the floating diffusion node, which is remnant in VM.]]>6639309402834<![CDATA[Synthesizable Memory Arrays Based on Logic Gates for Subthreshold Operation in IoT]]>$V_{mathrm {t}}$ for joint dynamic energy and leakage power reduction. Further, it enables fast turn-around times by IP reuse over technology nodes with minimal (re)design effort.]]>6639419544799<![CDATA[Physically Unclonable Functions Using Foundry SRAM Cells]]>6639559662011<![CDATA[Quadruple Cross-Coupled Latch-Based 10T and 12T SRAM Bit-Cell Designs for Highly Reliable Terrestrial Applications]]>$2times $ and $3.4times $ the minimum critical charge of the conventional 6T, respectively. Compared with most of the considered state-of-the-art SRAM cells, both QUCCE 10T and 12T have comparable or better soft error tolerance, time performance, read static noise margins, and hold static noise margins, and besides, QUCCE 10T also has similar or lower costs in terms of area and leakage power. The QUCCE 10T is designed for high-density SRAMs at the nominal supply voltage. Furthermore, the QUCCE 12T saves more than 50% the read access time compared with most of the referential cells including the 6T, making it suitable for high speed SRAM designs, and it also has the best read margin, except for the traditional 8T, in terms of $mu /sigma $ ratio in the near threshold voltage region among all the other considered cells which nearly have no write failure in that region. Hence, the QUCCE 12T is a promising candidate for future highly reliable terrestrial low-voltage applications.]]>6639679773441<![CDATA[Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS]]>$text{I}_{mathbf {on}}/text{I}_{mathbf {off}}$ ratio with increase in the number of cells per column. Previous approaches to solve these issues have been afflicted by low performance, data-dependent leakage, large area, and high energy per access. Therefore, in this paper, we present three iterations of SRAM bit cells with nMOS-only based read ports aimed to greatly reduce data-dependent read port leakage to enable 1k cells/RBL, improve read performance, and reduce area and power over conventional and 10T cell-based works. We compare the proposed work with other works by recording metrics from the simulation of a 128-kb SRAM constructed with divided-wordline-decoding architecture and a 32-bit word size. Apart from large improvements observed over conventional cells, up to 100-mV improvement in read-access performance, up to 19.8% saving in energy per access, and up to 19.5% saving in the area are also observed over other 10T cells, thereby enlarging the design and application gamut for memory designers in low-power sensors and battery-enabled devices.]]>6639789883976<![CDATA[Modified Dual-CLCG Method and its VLSI Architecture for Pseudorandom Bit Generation]]>$2^{n}$ . The proposed architecture is implemented using Verilog-HDL and prototyped on the commercially available FPGA device.]]>66398910023395<![CDATA[High-Speed ECC Processor Over NIST Prime Fields Applied With Toom–Cook Multiplication]]>$mu s$ at the cost of 30.3k LUTs and 48 DSPs. Synthesized with 180nm CMOS technology, the speed achieves 43.7 $mu s$ with 466k gate counts. These experimental results show a significantly better performance per area than previous works.]]>663100310161880<![CDATA[Signal Encoding and Processing in Continuous Time Using a Cascade of Digital Delays]]>663101710302202<![CDATA[An Adaptive Cascaded ILA- and DLA-Based Digital Predistorter for Linearizing an RF Power Amplifier]]>663103110413283<![CDATA[Area–Delay–Energy Efficient VLSI Architecture for Scalable In-Place Computation of FFT on Real Data]]>butterfly block which performs a set of butterfly operations in every clock cycle. From complexity analysis we find that in-place FFT structures with larger butterfly blocks are more efficient in terms of area-time complexity and energy consumption. The resolution of memory access conflict is however more challenging for higher butterfly block sizes. Therefore, we have analyzed the data-flow and memory footprint of in-place RFFT architectures for different throughput requirements, and based on that, we have proposed here a strategy to partition the storage unit into several banks of smaller sizes (without increasing the overall memory size) to resolve the memory access conflicts by concurrent data-swapping between the banks. Synthesis result shows that the proposed structure with butterfly block of size 4 and 8 involves (~44% and ~57%) less area-delay product and (~54% and ~57%) less energy per sample than those of existing similar structure on average for different FFT lengths, respectively.]]>663104210502617<![CDATA[Mean-Square Analysis of Multi-Sampled Multiband-Structured Subband Filtering Algorithm]]>663105110622167<![CDATA[Statistics-Based Approach for Blind Post-Compensation of Modulator’s Imperfections and Power Amplifier Nonlinearity]]>663106310753802<![CDATA[Event-Triggered Finite-Time Robust Filtering for a Class of State-Dependent Uncertain Systems With Network Transmission Delay]]>$H_infty $ and $L_{2}-L_infty $ filtering problems can be solved in a unified framework. An event-triggered scheme is also utilized to sift out the sampled signals so that both the communication resources and the network bandwidth can be saved as much as possible. By means of an appropriate Lyapunov–Krasovskii functional and the delay system approach, sufficient conditions guaranteeing the filtering error system being finite-time bounded with extended dissipativity are deduced. Based on the convex optimization, an explicit expression of the desired finite-time robust filter is derived. Finally, two numerical examples are provided to illustrate the effectiveness of the developed methods.]]>663107610891959<![CDATA[Network Science Meets Circuit Theory: Resistance Distance, Kirchhoff Index, and Foster’s Theorems With Generalizations and Unification]]>663109011031162<![CDATA[Proper Initial Solution to Start Periodic Steady-State-Based Methods]]>663110411152053<![CDATA[<inline-formula> <tex-math notation="LaTeX">${{H}_{infty}}$ </tex-math></inline-formula>Model Reduction for Interval Frequency Negative Imaginary Systems]]>$H_{infty }$ model reduction problem for interval frequency negative imaginary (IFNI) systems. For a given IFNI system, our goal is to find a reduced-order IFNI system satisfying a pre-specified $H_{infty }$ approximation error bound over the finite-frequency interval. Necessary and sufficient conditions in terms of matrix inequalities are derived for the existence and construction of an $H_{infty }$ reduced-order IFNI system. An improved iterative algorithm is provided to solve the matrix inequalities and to minimize the $H_{infty }$ approximation error. The proposed method is further clarified via the application to the electrical circuits, such as high-order Sallen–Key low-pass filter, piezoelectric tube scanner, and RLC circuit. The simulation results on these electrical circuits are compared with the finite-frequency interval Gramians-based model reduction method both in the frequency domain and time domain.]]>663111611291761<![CDATA[Network-Based Quantized Control for Fuzzy Singularly Perturbed Semi-Markov Jump Systems and its Application]]>$bar { sigma }$ -error stability of the corresponding system but also allows a higher upper bound of the singularly perturbed parameter. Sufficient conditions are developed to make sure that the applicable controller could be found. The further examination to demonstrate the feasibility of the presented method is given by designing a controller of a series DC motor model.]]>663113011401694<![CDATA[Synchronization of Multi-Layer Networks: From Node-to-Node Synchronization to Complete Synchronization]]>663114111525285<![CDATA[A Hilbert Transform Equalizer Enabling 80 MHz RF Self-Interference Cancellation for Full-Duplex Receivers]]>$mu text{m}$ CMOS process attains a measured 23 dB of SIC over an 80 MHz signal bandwidth at 900 MHz, and consumes 13 mW of clocking power independent of SIC equalizer settings. Its impact on the receiver noise figure is 1.4 dB. The equalizer and the receiver together consume 64.4 mW from a 1.2 V supply in an active area of 0.72 mm^{2}.]]>663115311653372<![CDATA[A −40 dB EVM, 77 MHz Dual-Band Tunable Gain Sub-Sampling Receiver Front End in 65-nm CMOS]]>2 and has a total power dissipation of 55.6 mW. The overall receiver chain shows a noise figure of 11.5 dB at the highest gain and an IIP_{3} of −8 dBm at the lowest gain.]]>663116611794378<![CDATA[A Low Power Receiver Front-End Design With Tunable Notch Filter for TX Leakage and Blocker Suppression]]>2/channel. Its noise contribution is within the NF measurement error, thus negligible. The design is intended and tested for transmitter self-interference and wideband ACS blockers.]]>663118011912311<![CDATA[Line Coding Techniques for Channel Equalization: Integrated Pulse-Width Modulation and Consecutive Digit Chopping]]>2.]]>663119212047932<![CDATA[An Integrated Message-Passing Detector and Decoder for Polar-Coded Massive MU-MIMO Systems]]>first soft-output message-passing detector (MPD), which is also integrated with a high-throughput polar decoder. The algorithm and architecture are designed concurrently to improve the hardware performance. The proposed techniques, including the adaptive variance estimation and reliable symbol detection, reduce the complexity of the MPD by 98.3%, and enable soft output for the outer polar decoder. Compared to the state-of-the-art hard-output design, the proposed MPD achieves a $5.86times $ higher throughput-to-area ratio (TAR) with 54.3% lower energy dissipation, despite the soft output. The proposed bidirectional-propagation belief propagation decoder is devised to reduce the critical path and to increase the throughput. The proposed polar decoder can improve the TAR by 35% with a comparable area and energy compared with the state-of-the-art polar decoder. A polar-coded massive MIMO receiver that supports a length-1024 rate-1/2 polar code, 128 receive antennas, and eight users is designed and implemented, and delivers a throughput of 7.61 Gb/s.]]>663120512184651<![CDATA[A (21150, 19050) GC-LDPC Decoder for NAND Flash Applications]]>two-phase local/global decoding procedure optimized for the proposed GC-LDPC code is introduced. Scenarios of collaborative decoding that leverages the special code structures are discussed. In the proposed decoder architecture, the pipelined processing elements with scheduling are employed to reduce the critical path and decoding latency as well. Implemented in UMC 65 nm process, the post-layout simulation shows a maximum decoding throughput of 4.32 Gb/s with the chip area 3.376 mm^{2}.]]>663121912303246<![CDATA[Variation Aware Design of 50-Gbit/s, 5.027-fJ/bit Serializer Using Latency Combined Mux-Dual Latch for Inter-Chip Communication]]>$471.6~mu text{W}$ and 93.9 ps, respectively, to provide a power delay product of 43.8 fJ only at a power supply of 1 V. An improved output swing of 904 mV is also noticed along with a data rate of 50 Gb/s and a BER of <10^{−12}. The entire design is proved to be a robust one after simulating it through Monte Carlo at five different process corners and also validated at lower process nodes such as 28-nm UMC.]]>663123112445438<![CDATA[An Accurate and Noise-Resilient Spread-Spectrum Clock Tracking Aid for Digitally-Controlled Clock and Data Recovery Loops]]>−12, which is a $1.57times $ improvement in comparison with a PLL-based second-order CDR, when tracking a 6-Gb/s data stream modulated with a 30-kHz, 50000-ppm extended triangular-shaped SSC profile.]]>663124512573312<![CDATA[Fully-Integrated Charge Pump Design Optimization for Above-Breakdown Biasing of Single-Photon Avalanche Diodes in 0.13-<inline-formula> <tex-math notation="LaTeX">$mu$ </tex-math></inline-formula>m CMOS]]>$mu text{m}$ CMOS process and is capable of generating a maximum regulated output voltage of 17.7 V from an input of 1.8 V. An ON–OFF regulation scheme with dynamic charging and discharging capability of the charge pump provides fast recovery of the output bias voltage during SPAD transients, where overshoot and undershoot must both be corrected during active quench and reset. Following a SPAD avalanche current pulse, the measured transient recovery time is 500 ns from a 150-mV overshoot and a 500-mV undershoot to reach 99% of steady-state output. The implemented SPAD bias generation system occupies 0.175-mm^{2} chip area, without requiring an off-chip load capacitor.]]>663125812692760<![CDATA[A 0.90–4.39-V Detection Voltage Range, 56-Level Programmable Voltage Detector Using Fine Voltage-Step Subtraction for Battery Management]]>$V_{mathrm {DETECT}}$ ). Thanks to the programmability, users can set an appropriate $V_{mathrm {DETECT}}$ for battery management considering the operating voltage of the battery. For batteries including Li-ion and NiMH batteries, a PVD is required to achieve wide programmed $V_{mathrm {DETECT}}$ range from 1.0 to 4.35 V with a fine voltage step of ±42 mV. Furthermore, the power consumption of the PVD must be minimized since the PVD is always operating in battery management. To achieve both the target programmability of $V_{mathrm {DETECT}}$ and the low power consumption of the PVD, a programmable voltage reference (PVREF) using a fine voltage-step subtraction (FVS) method is proposed. The FVS is a combination of fine and coarse programming for the output of the PVREF, which achieves a fine voltage step and a wide programmable range of $V_{mathrm {DETECT}}$ achieving both a low temperature coefficient of $V_{mathrm {DETECT}}$ and low power consumption of the PVD. The measurement results of the PVD fabricated in a 250-nm CMOS process show a current consumption of the PVD of 1.2 nA at 3.5 V and a temperature coefficient of $V_{mathrm {DETECT}}$ of 0.28 mV/°C. The PVD enables the widest programmable range of $V_{mathrm {DETECT}}$ from 0.90 to 4.39 V, fine $V_{mathrm {DETECT}}$ resolution of ±31.5 mV, and 56-level linear, monotonic programmability of $V_{mathrm {DETECT}}$ .]]>663127012792277<![CDATA[A New Design Technique for Sub-Nanosecond Delay and 200 V/ns Power Supply Slew-Tolerant Floating Voltage Level Shifters for GaN SMPS]]>$mu $ mV), which is an $1.7times $ improvement on the next best reported level shifter for this type of application.]]>663128012902841<![CDATA[Power Extracted From Piezoelectric Harvesters Driven by Non-Sinusoidal Vibrations]]>663129113033809<![CDATA[IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors]]>66313041304145<![CDATA[IEEE Circuits and Systems Society Information]]>663C3C3102