<![CDATA[ IEEE Transactions on Circuits and Systems I: Regular Papers - new TOC ]]>
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TOC Alert for Publication# 8919 2018May 24<![CDATA[Table of contents]]>656C1C4173<![CDATA[IEEE Transactions on Circuits and Systems—I:Regular Papers publication information]]>656C2C278<![CDATA[How to Make Analog-to-Information Converters Work in Dynamic Spectrum Environments With Changing Sparsity Conditions]]>656177517844278<![CDATA[A 250-MHz Pipelined ADC-Based <inline-formula> <tex-math notation="LaTeX">$f_{S}/4$ </tex-math></inline-formula> Noise-Shaping Bandpass ADC]]>$f_{S}/4$ bandpass $Delta Sigma$ -analog-to-digital converter (ADC) architecture is realized by feeding back the delayed quantization noise inherently produced by a pipelined ADC. Designed in a 55-nm global foundry (GF) LP-CMOS process, the prototype ADC sampling at 250 MHz achieves an Signal-to-Noise+Distortion Ratio of 72, 75.8, 80.1, and 85.3 dB in a 15.64-, 7.82-, 3.91-, and 1.953-MHz band, respectively, around a center frequency of 62.5 MHz with only first-order noise shaping, while consuming 103 mW of power, and achieving a maximum figure-of-merit of 158 dB.]]>656178517942638<![CDATA[A Fully Isolated Amplifier Based on Charge-Balanced SAR Converters]]>656179518042215<![CDATA[Design of High-Order Type-II Delay-Locked Loops With a Fast-Settling-Zero-Overshoot Step Response and Large Jitter-Rejection Capabilities]]>656180518184589<![CDATA[Analysis of Common-Mode Interference and Jitter of Clock Receiver Circuits With Improved Topology]]>ms jitter with a 620-$mu text{W}$ power at 1.2 V supply. With a similar CMI rejection and random jitter performance, the proposed CRC exhibits a 20-fold power reduction when compared with the state-of-art designs.]]>656181918292096<![CDATA[A Digital Phase-Locked Loop With Background Supply Voltage Sensitivity Minimization]]>2 where the supply voltage sensitivity controller occupies about 20%. The power consumption is 9.34 mW from a supply of 1.1 V wherein the supply voltage sensitivity controller consumes $840~mu text{W}$ . The output frequency of the DPLL is 5 GHz with a divider ratio of 64. The minimum measured supply voltage sensitivity is −0.0044 $[%-{f} _{mathrm {VCO}}/%-{V}_{mathrm {DD}}$ ]. With a 50-mV_{PP}, 100-kHz sinusoidal supply noise, the peak-to-peak jitter is reduced from 41.48 to 23.15 ps, and the rms jitter is reduced from 7.26 to 3.47 ps.]]>656183018392512<![CDATA[Analytic and Numerical Study of TCSC Devices: Unveiling the Crucial Role of Phase-Locked Loops]]>656184018491503<![CDATA[A SiGe BiCMOS Concurrent K/V Dual-Band 16-Way Power Divider and Combiner]]>${mu }text{m}$ SiGe BiCMOS process that works concurrently over 18–26 GHz (K-band) and 57–64 GHz (V-band) is presented. The 16-way K/V dual-band power divider integrates a two-way K/V dual-band Wilkinson-based power divider with a high-pass filter and multiple broad-band two-way lumped-element and transmission-line Wilkinson power dividers. The two-way dual-band power divider is designed by employing a slow-wave transmission line and two shunt-connected series LC resonators in each arm, leading to miniaturization and low loss with dual-band transmission in K- and V-band, decent return losses, and good isolation of larger than 20 dB over the dual-band. The developed 16-way K/V dual-band power divider possesses good performance over the dual-band. Specifically, it achieves measured insertion losses of 18.4 and 21 dB at 24 and 60 GHz, respectively, with good return losses. Furthermore, it also exhibits measured isolation larger than 20.1 and 17.7 dB between any two output ports at 24 and 60 GHz, respectively.]]>656185018614321<![CDATA[Theory and Design of Frequency-Tunable Absorptive Bandstop Filters]]>656186218742670<![CDATA[Planar Balanced-to-Unbalanced In-Phase Power Divider With Wideband Filtering Response and Ultra-Wideband Common-Mode Rejection]]>656187518862344<![CDATA[An On-Chip CMOS Temperature Sensor Using Self-Discharging P-N Diode in a <inline-formula> <tex-math notation="LaTeX">$Delta$ </tex-math></inline-formula>-<inline-formula> <tex-math notation="LaTeX">$Sigma$ </tex-math></inline-formula> Loop]]>$Delta$ -$Sigma$ ) loop. To determine the on-chip temperature, the temperature-dependent reverse-bias leakage current of the diode is measured. The sensor is implemented in a 0.18-$mu text{m}$ CMOS process and it occupies a small area of $550mu text{m}^{2}$ . Performance measurements demonstrate the on-chip sensor inaccuracies of ±0.1 °C ($3sigma$ ) with calibration, and ±0.5 °C ($3sigma$ ) without any calibration, over 35 °C–100 °C, which is the functional temperature range of current high-performance SoCs. The sensor, excluding the digital and any reference generators, consumes $4mu text{W}$ from a single 1.8-V supply. The worst case resolution of the sensor is 75 mK at 2-Hz bandwidth with the overall sensor figure of merit of 11 nJ°K^{2}.]]>656188718963043<![CDATA[A Scalable Low-Power Reconfigurable Accelerator for Action-Dependent Heuristic Dynamic Programming]]>656189719082706<![CDATA[A Low Power Self-healing Resilient Microarchitecture for PVT Variability Mitigation]]>$times16$ b MAC unit was fabricated using Global Foundry 65-nm technology with 18.26% area overhead and upto $1.65times $ speedup. At the typical conditions, the maximum frequency of the conventional MAC unit is about 375 MHz while the resilient MAC unit operates correctly at a frequency upto 620 MHz. In case of variations, the resilient MAC unit tolerates induced delays up to 50% of the clock period while keeping its throughput equal to the conventional MAC unit’s maximum throughput. At 375 MHz, the resilient MAC unit is able to scale down the supply voltage from 1.2 to 1 V saving about 29% of the power consumed by the conventional MAC unit.]]>656190919183027<![CDATA[VFAB: A Novel 2-Stage STTRAM Sensing Using Voltage Feedback and Boosting]]>$14.4sigma $ in typical corner and $4.7times $ reduction in read power compared to conventional voltage sensing.]]>656191919282502<![CDATA[Modular Design of High-Efficiency Hardware Median Filter Architecture]]>656192919403826<![CDATA[Efficient Hardware Architectures for Deep Convolutional Neural Network]]>656194119531975<![CDATA[An Efficient Bayesian Optimization Approach for Automated Optimization of Analog Circuits]]>656195419672849<![CDATA[Efficient Behavioral Simulation of Charge-Pump Phase-Locked Loops]]>656196819802739<![CDATA[NCL Synthesis With Conventional EDA Tools: Technology Mapping and Optimization]]>2 figure.]]>656198119932900<![CDATA[Lyapunov Conditions for Stability of Stochastic Impulsive Switched Systems]]>656199420041620<![CDATA[One Mbps 1 nJ/b 3.5–4 GHz Fully Integrated FM-UWB Transmitter for WBAN Applications]]>2 silicon area and consumes 987 $mu text{W}$ from a 1.2 V supply. It achieves an energy consumption of 0.987 nJ/bit at 1 Mbps data rate.]]>656200520142856<![CDATA[Analysis and Specification of an IR-UWB Transceiver for High-Speed Chip-to-Chip Communication in a Server Chassis]]>656201520232251<![CDATA[Compact Fast-Waking Light/Heat-Harvesting 0.18-<inline-formula> <tex-math notation="LaTeX">$mutext{m}$ </tex-math></inline-formula> CMOS Switched-Inductor Charger]]>$mu text{m}$ CMOS charger proposed here is 8.31% more efficient during wakeup than the smallest reported and 7.69% more efficient than the next best, but without a 1:60 off-chip transformer and without vibration energy. Although 3.27% less efficient than the most efficient, the system here uses three fewer off-chip inductors. And after waking, the system is 5% to 46% more efficient than the others. The key innovations are low-power management and design. The system in essence charges a 200-pF capacitor with just enough energy to transfer two energy packets per cycle: one to charge a 1.8-$mu text{F}$ battery and the other to replenish the 200 pF. This way, and with 100 nF across the source, the system charges a fully depleted 1.8-$mu text{F}$ battery to 0.9 V in 45 ms and draws in steady state 98.8%–99.7% of available input power to deliver 76%–86% of the 40–150 $mu text{W}$ drawn.]]>656202420342255<![CDATA[Four Monolithically Integrated Switched-Capacitor DC–DC Converters With Dynamic Capacitance Sharing in 65-nm CMOS]]>dynamic capacitance sharing (DCS) switched-capacitor converters that increase the range of efficient voltage regulation for multiple independent loads while reducing area overhead. Since maximum power dissipation is fixed for a single chip due to thermal constraints, the proposed converters consider the overall power budget of multiple voltage-scalable loads to dynamically share energy storage area, allowing the dynamic allocation of energy storage clusters on-demand. Our DCS converters utilize a feedback control scheme including both capacitance and frequency modulation, which leads to the order of 10–100ns voltage settling times. A test chip with 16 clusters and four regulator control loops is fabricated in 65-nm bulk CMOS process. For a 2.3V input, our DCS converters achieve 0.742V at 38.1mA to 1.367V at 298mA output with peak efficiency of 70.9% at 550-mW/mm^{2} power density. Regulator area for the four-load network is reduced by up to 70% when operating under a power constraint compared with the stand-alone per-load regulators capable of supporting an equivalent range of operating voltages.]]>656203520474614<![CDATA[Harvesting Energy From Aviation Data Lines: Implementation and Experimental Results]]>$mu text{m}$ (AMS) 3.3 V/5 V technology and the system performance is investigated under various conditions to improve its efficiency. From the experimental tests, an overall efficiency of 60 % was achieved and the harvesting device provided an output power of 10.08 mW for feeding sensors. Reported experimental results proved that the proposed power recovery scheme could serve as a power recovery unit to supply embedded sensors.]]>656204820572456<![CDATA[IEEE Transactions on Circuits and Systems - I:Regular Papers information for authors]]>6562058205853<![CDATA[IEEE Circuits and Systems Society Information]]>656C3C3105