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TOC Alert for Publication# 8919 2014April 17<![CDATA[Table of Contents]]>614C1C4161<![CDATA[IEEE Transactions on Circuits and Systems—I: Regular Papers publication information]]>614C2C2132<![CDATA[Digital Systems Power Management for High Performance Mixed Signal Platforms]]>6149619754228<![CDATA[Analysis and Design of Class-<formula formulatype="inline"> <img src="/images/tex/19509.gif" alt="{\rm E}_{\rm M}"> </formula> Power Amplifier]]>M power amplifier, taking into account the fundamental-frequency and harmonic components of output currents in the main and auxiliary circuits. By using the proposed expressions, design values for satisfying not only the class-E_{M} ZVS/ZDVS/ZCS/ZDCS conditions of the main circuit, but also the ZVS condition of the auxiliary circuit can be achieved without applying any tuning process. The analytical predictions agreed with experimental and PSpice-simulation results quantitatively, which showed the validity of analytical expressions given in this paper.]]>6149769862500<![CDATA[Modeling and Analysis of Class-E Amplifier With a Shunt Inductor at Sub-Nominal Operation for Any Duty Ratio]]>61498710003114<![CDATA[A 5-Gb/s Serial-Link Redriver With Adaptive Equalizer and Transmitter Swing Enhancement]]>614100110112118<![CDATA[Architecture of a Single-Chip 50 Gb/s DP-QPSK/BPSK Transceiver With Electronic Dispersion Compensation for Coherent Optical Channels]]>2 of second-order polarization-mode dispersion (SOPMD). Other key DSP functions of the receiver include carrier and timing recovery, automatic gain control, channel diagnostics, etc. A novel low-latency parallel-processing carrier recovery implementation which is robust in the presence of laser phase noise and frequency jitter is proposed. The chip integrates the transmitter, receiver, framer and host interface functions and features a 4-channel 25 Gs/s 6-bit ADC with a figure of merit (FOM) of 0.4 pJ/conversion. Each ADC channel is based on an 8-way interleaved flash architecture. The DSP uses a 16-way parallel processing architecture. Extensive measurement results are presented which confirm the design targets. Measured optical signal-to-noise ratio (OSNR) penalty when compensating 200 ps DGD and 8000 ps ^{2} is 0.1 dB, while OSNR penalty when compensating 55 ns/nm CD (corresponding to 3,500 km of standard single-mode fiber) is 0.5 dB.]]>614101210251879<![CDATA[A Novel 1.2–V 4.5-ppm/°C Curvature-Compensated CMOS Bandgap Reference]]>614102610352073<![CDATA[Ambient Light Organic Sensor in a Printed Complementary Organic TFT Technology <newline/>on Flexible Plastic Foil]]>614103610432654<![CDATA[A Study of Deterministic Jitter in Crystal Oscillators]]>614104410542628<![CDATA[High Precision Synthesis of a Richards Immittance Via Parametric Approach]]>-3. A complete synthesis package is developed in MatLab and successfully integrated with the Real Frequency Technique to design broadband matching networks. Examples are presented to show the merits of the new Richards synthesis tool.]]>614105510673443<![CDATA[A 10-Gb/s, 107-mW Double-Edge Pulsewidth Modulation Transceiver]]>-12 and is compared against NRZ schemes at the same rate. The inductor-less transmitter and receiver active circuitry respectively occupy an area of 93 × 94 and 218 × 160 μm^{2}, and consume a total 107 mW from a 1.2 V supply.]]>614106810803006<![CDATA[A 16-Core Processor With Shared-Memory and Message-Passing Communications]]>2 and operates fully functional at a clock rate of 750 MHz at 1.2 V and maximum 800 MHz at 1.3 V. Each core dissipates 34 mW under typical conditions at 750 MHz and 1.2 V while executing embedded applications such as an LDPC decoder, a 3780-point FFT module, an H.264 decoder and an LTE channel estimator.]]>614108110943679<![CDATA[Selective State Retention Power Gating Based on Gate-Level Analysis]]>614109511041414<![CDATA[A 0.6–107 µW Energy-Scalable Processor for Directly Analyzing Compressively-Sensed EEG]]>614110511183385<![CDATA[NAND Flash Memory/ReRAM Hybrid Unified Solid-State-Storage Architecture]]>614111911324399<![CDATA[An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator]]>614113311432314<![CDATA[Efficient Algorithm and Architecture for Elliptic Curve Cryptography for Extremely Constrained Secure Applications]]>m) and employ an efficient bit-level GNB multiplier. One advantage of this GNB multiplier is that we are able to reduce the hardware complexity through sharing the addition/accumulation with other field additions. We utilized the special property of normal basis representation and squarings are implemented very efficiently by only rewiring in hardware. We introduce a new technique for point addition in affine coordinate which requires fewer registers. Based on this technique, we propose an extremely small processor architecture for point multiplication. Through application-specific integrated circuit (ASIC) implementations, we evaluate the area, performance, and energy consumption of the proposed crypto-processor. Utilizing two different working frequencies, it is shown that the proposed architecture reaches better results compared to the previous works, making it suitable for extremely-constrained, secure environments.]]>614114411552011<![CDATA[Multifunction Residue Architectures for Cryptography]]>n) respectively, as well as a VLSI architecture of a dual-field residue arithmetic Montgomery multiplier are presented in this paper. An analysis of input/output conversions to/from residue representation, along with the proposed residue Montgomery multiplication algorithm, reveals common multiply-accumulate data paths both between the converters and between the two residue representations. A versatile architecture is derived that supports all operations of Montgomery multiplication in GF(p) and GF(2^{n}), input/output conversions, Mixed Radix Conversion (MRC) for integers and polynomials, dual-field modular exponentiation and inversion in the same hardware. Detailed comparisons with state-of-the-art implementations prove the potential of residue arithmetic exploitation in dual-field modular multiplication.]]>614115611693179<![CDATA[A Low Complexity Geometric Mean Decomposition Computing Scheme and Its High Throughput VLSI Implementation]]>614117011823379<![CDATA[Fuzzy Modelling and Consensus of Nonlinear Multiagent Systems With Variable Structure]]>614118311912823<![CDATA[Design-Oriented Analysis of Quantization-Induced Limit Cycles in a Multiple-Sampled Digitally Controlled Buck Converter]]>614119212053615<![CDATA[Digital Multiplierless Implementation of Biological Adaptive-Exponential Neuron Model]]>614120612193685<![CDATA[Synchronization of Nonlinear Dynamical Networks With Heterogeneous Impulses]]>614122012282457<![CDATA[Electronically Tunable Doherty Power Amplifier for Multi-Mode Multi-Band Base Stations]]>614122912402370<![CDATA[Low-Latency Successive-Cancellation Polar Decoder Architectures Using 2-Bit Decoding]]>614124112543507<![CDATA[A 5-Gb/s Noise Optimized Receiver Using a Switched TIA for Wireless Optical Communications]]>-12 at 5-Gb/s corresponding to 2.8 μA current at the input and at 4-Gb/s corresponding to 2.1 μA input current, in presence of 1 pF input capacitance representing the photodiode. The total power consumption including the on chip 50 Ω differential output buffer is 68 mW from 1.5 V DC supply. The die area including bonding pads and output buffer is 1106 μm × 895 μm.]]>614125512683363<![CDATA[A –<formula formulatype="inline"> <img src="/images/tex/21212.gif" alt="21.2"> </formula>-dBm Dual-Channel UHF Passive CMOS RFID Tag Design]]>614126912791670<![CDATA[A Compact Architecture for Simulation of Spatio-Temporally Correlated MIMO Fading Channels]]>614128012881889<![CDATA[Scalable Digital Power Controller With Phase Alignment and Frequency Synchronization]]>614128912971074<![CDATA[IEEE Transactions on Circuits and Systems—I: Regular Papers information for authors]]>61412981298121<![CDATA[Open Access]]>614129912991156<![CDATA[IEEE Xplore Digital Library]]>614130013001792<![CDATA[IEEE Circuits and Systems Society Information]]>614C3C3119