<![CDATA[ IEEE Transactions on Circuits and Systems I: Regular Papers - new TOC ]]>
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TOC Alert for Publication# 8919 2018August 20<![CDATA[Table of contents]]>659C1C4178<![CDATA[IEEE Transactions on Circuits and Systems—I:Regular Papers publication information]]>659C2C2111<![CDATA[A Low-Power, Wireless, Capacitive Sensing Frontend Based on a Self-Oscillating Inductive Link]]>$0.18~mu text{m}$ CMOS, and combined with an on-chip humidity sensing capacitor. The system was tested in a humidity chamber across a range of 20–90%rh. Measured results from the system demonstrate that capacitive changes as small as 28 fF, translating to <2%rh, can be resolved, with a power consumption of 1.44 mW.]]>659264526563512<![CDATA[A Full Ka-Band Power Amplifier With 32.9% PAE and 15.3-dBm Power in 65-nm CMOS]]>$k$ ) of the MCR can be determined from the no gain ripple condition. Fabricated in 65-nm CMOS process, the PA chip achieves 32.9% peak power added efficiency, 15.3-dBm saturated output power ($P_{mathrm {sat}}$ ), and 12.9-dBm output 1-dB compression point ($P_{mathrm {1,dB}}$ ). The fractional bandwidth of the PA is 63.3% from 21.6 to 41.6 GHz, which covers the full Ka-band (26.5 to 40 GHz).]]>659265726683024<![CDATA[A 7-GHz CMOS Bidirectional Variable Gain Amplifier With Low Gain and Phase Imbalances]]>$1848times 628,,mu text{m}^{2}$ including pads. The gains of the BVGA are 2.3–11.5 dB and return loss is <−6 dB at 7 GHz. The 3-dB bandwidth of the BVGA is 2 GHz that is from 6 to 8 GHz. The measured output 1-dB power compression point and minimum noise figure are 4.6 dBm and 6.7 dB. The measured gain and phase directional imbalances are <0.1 dB and <4° in the C-band. The power consumption of the BVGA is 72.5 mW.]]>659266926783644<![CDATA[A <inline-formula> <tex-math notation="LaTeX">$Ktext{-}/Ka$ </tex-math></inline-formula>-Band Concurrent Dual-Band Single-Ended Input to Differential Output Low-Noise Amplifier Employing a Novel Transformer Feedback Dual-Band Load]]>$mu text{m}$ BiCMOS process and exhibits the same single-ended-to-differential peak gains of 19.2 dB at 21.5 and 36 GHz in the low- and high-passband, respectively, with the stopband rejection ratio of 37.1 dB. In the single-ended input to single-ended output (single-ended) mode operation, the designed LNA exhibits the measured peak gains of 15.7/16.6 dB at 21.5 GHz and 15.7/16.7 dB at 36 GHz for the two signal paths. It achieves the best measured single-ended noise figures of 4.3/4.0 and 4.3/4.2 dB for the two signal paths in the respective low and high passbands. The LNA also attains the measured differential gain and phase imbalances of 0.9/1.0 dB and 0.5/10.4 degree in the low/high passband, respectively. This LNA is the first concurrent dual-band single-ended-to-differential LNA integrated on-chip operating in ${K}$ - and Ka-band.]]>659267926903764<![CDATA[A 2.5–5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection]]>2.]]>659269127023657<![CDATA[Expansion and Compression of Analog Pulses by Bandwidth Scaling of Continuous-Time Filters]]>2, 370 mW, 0.13 $mu text{m}$ prototype has a delay filter whose bandwidth can be switched between 870 and 472 MHz. It achieves $1.8times $ pulse expansion and $1.7times $ pulse compression with an rms error which is 33 dB below the peak-peak pulse amplitude.]]>659270327142788<![CDATA[Wideband Techniques for Outphasing Power Amplifiers]]>$Omega $ load. The L-S band (1.2~2.5GHz) amplifier was simulated, fabricated, and characterized. The fabricated HPA provides a peak output power of 43 dBm, gain of >15 dB with a peak PAE of >40% across the band. A 10 MHz, 64 QAM, long-term evolution signal is measured and achieves ACLR < −30 dBc, EVM = 4.8%-rms at an average output power and efficiency of 39.3 dBm and 33.1%, respectively.]]>659271527252049<![CDATA[Design and Hardware Implementation of Neuromorphic Systems With RRAM Synapses and Threshold-Controlled Neurons for Pattern Recognition]]>$0.31mu text{J}$ on average. The proposed system has been implemented on hardware, and has been experimentally demonstrated to show the capability of pattern recognition.]]>659272627389566<![CDATA[Hardware Implementation of an Event-Based Message Passing Graphical Model Network]]>$2.16 times 2.74$ mm^{2}. Each channel dissipates 46 uW. The output analog messages of the channels are encoded through the interspike intervals of the output spike streams or events. The system can be used to implement graphs with arbitrary variable distributions for its inputs and using constraint functions, such as “plus” and “equality”. Using Kullback–Leibler divergence, we show that the measured distributions from the implemented graphs on the hardware show close similarity to the theoretical distributions.]]>659273927523974<![CDATA[A CMOS Follower-Type Voltage Regulator With a Distributed-Element Fractional-Order Control]]>2. It operates in a harsh automotive environment with a temperature from −50 °C to 200 °C and shows a tight DC regulation, while being stable over the full range of the load current (from 0 to 100 mA) and with any load capacitance (allowing to use none or any external capacitor).]]>659275327637598<![CDATA[A Digitally Interfaced Analog Correlation Filter System for Object Tracking Applications]]>$24times 57$ correlation filter system for object tracking applications. While digital interfacing of the input and output data enabled a standard and flexible way of communication with pre- and post-processing digital blocks, the multiply-accumulate (MAC) operations were performed in the analog domain to save power and area. The proposed system utilizes non-volatile floating-gate memories to store filter coefficients. The chip was fabricated in a 0.13-$mu text{m}$ CMOS process and occupies 3.23 mm^{2} of silicon area. The system dissipates 388.4 $mu text{W}$ of power at a throughput of 11.3 kVec/s, achieving an energy efficiency of 25.2 pJ/MAC. Experimental results for a custom filter designed to detect vehicles are presented.]]>659276427733687<![CDATA[A Subthreshold Buffer-Based Biquadratic Cell and its Application to Biopotential Filter Design]]>${mu }text{m}$ CMOS process to serve electrocardiography readout systems. Measurement results show that the filter consumes 4.26-nW static power from a 0.9-V supply providing a 100-Hz cutoff frequency. The prototype chip occupies a silicon area of 0.11 mm^{2} and contributes an input-referred noise of $80.5~{mu }text{V}_{mathrm {rms}}$ . For a 60-Hz input frequency associated with −50-dB third-order harmonic distortion, a dynamic range of 48.2 dB is achieved. The lowest power supply rejection ratio of 40 dB was obtained at 100 Hz. Compared with the previous state-of-the-art designs in the category of nanopower filters, the proposed filter consumes the least power from the lowest supply voltage.]]>659277427832762<![CDATA[A Self-Powered Supply-Sensing Biosensor Platform Using Bio Fuel Cell and Low-Voltage, Low-Cost CMOS Supply-Controlled Ring Oscillator With Inductive-Coupling Transmitter for Healthcare IoT]]>$mu text{m}$ zero-$V_{text {th}}$ all-digital CMOS supply-controlled ring oscillator with a current-driven pulse-interval-modulated inductive-coupling transmitter. The fully digital, and current-driven architecture uses zero-$V_{text {th}}$ transistors, which enables low voltage operation and a small footprint, even in a cost-competitive legacy CMOS. This enables converterless self-powered operation using a bio fuel cell, which is ideal for disposable healthcare applications. To verify the effectiveness of the proposed platform, a test chip was fabricated using 0.25-$mu text{m}$ CMOS technology. The experimental results successfully demonstrate operation with a 0.23-V supply, which is the lowest supply voltage reported for proximity transmitters. A self-powered biosensing operation using organic bio fuel cells was also successfully demonstrated. In addition, an asynchronous inductive-coupling receiver and an off-chip inductor for performance improvement were successfully demonstrated.]]>659278427964093<![CDATA[A High-Voltage DAC-Based Transmitter for Coded Signals in High Frequency Ultrasound Imaging Applications]]>$mu text{m}$ high-voltage CMOS process provided by foundry, integrating the digital control circuitry and HVDAC on a single chip. By employing a fast-slewing DAC in conjunction with a standard DAC, the proposed circuit is optimized for high-speed operations even for a load with large capacitance, making it well suited for applications where piezoelectric transducers are utilized. With an output loading of 180 pF // $50~Omega $ , the HVDAC operates at a sampling rate of 150 MS/s, while providing a maximum output swing of 31.5 $text{V}_{mathrm {PP}}$ . The spurious-free dynamic range is 46 dB at 1-MHz output frequency and 31 dB at Nyquist frequency, which is analyzed in detailed and proved in good agreement with the measurement results. Tested with a chirp signal sweeping from 15.75 to 34.25 MHz in 2-$mu text{s}$ and a transducer model centered at 25 MHz with a 13.75-MHz bandwidth, the compressed pulse after matched filtering shows a −6-dB pulse width of 153 ns with a peak sidelobe of −40 dB, which successfully demonstrates the capability for coded signals excitation at high frequency.]]>659279728095869<![CDATA[A Wirelessly Powered CMOS Electrochemical Sensing Interface With Power-Aware RF-DC Power Management]]>$mu text{m}$ CMOS process. A novel, power-aware, multiple-path, RF-energy harvesting front end extends the high-efficiency (>20%) RF-powering range to 8.5 dB. In the sensor-readout interface, a chopper-stabilization potentiostat with an oscillator-based current readout achieves a 3.3-pA current resolution in the current range of 800nA and an $R^{2}$ linearity of 0.9987 while consuming only $4.4mu text{W}$ . The power efficiency of the electrochemical readout interface is 0.18, and the dynamic detection range is 107 dB.]]>659281028204325<![CDATA[A <inline-formula> <tex-math notation="LaTeX">$16times16$ </tex-math></inline-formula> CMOS Amperometric Microelectrode Array for Simultaneous Electrochemical Measurements]]>$mu text{m}$ ) that the signal cross-talk is only 12% between nearest neighbors in a ferrocene rich solution. The system opens up the possibility to use multiple independently controlled electrochemical sensors on a single chip for applications in DNA sensing, medical diagnostics, environmental sensing, the food industry, neuronal sensing, and drug discovery.]]>659282128312494<![CDATA[Modeling Random Clock Jitter Effect of High-Speed Current-Steering NRZ and RZ DAC]]>659283228411823<![CDATA[Impedance Matching and Reradiation in LPTV Receiver Front-Ends: An Analysis Using Conversion Matrices]]>$S_{11}$ of an LPTV circuit is non-trivial in general. Moreover, reflections at harmonic offsets from input frequencies can also be expected due to the time-varying nature of the circuit. This paper utilizes the conversion matrix-based analysis technique to compute the $S_{11}$ of a general LPTV circuit. Furthermore, it is shown that signal reradiation at harmonic shifts from input frequencies is also obtained as a natural consequence of this analysis. Examples related to mixer-first receivers, switched-capacitor receiver front-ends (with reset), and Filtering-by-Aliasing (FA)-based receivers are considered to verify the analysis. Design guidelines are provided to attain optimal $S_{11}$ in a few such scenarios. Explicit analytical expressions are derived for reradiation in ideal $N$ -path mixer-first receivers and FA-based receivers, while guidelines are provided for proper choice of conversion matrix expressions/sizes in case of numerical computation.]]>659284228552775<![CDATA[Design and Evaluation of Approximate Logarithmic Multipliers for Low Power Error-Tolerant Applications]]>659285628685926<![CDATA[A Low-Latency and Low-Complexity Point-Multiplication in ECC]]>$GF(2^{233})$ , $GF(2^{163})$ , and $GF(2^{283})$ show 62%, 46%, and 152% efficiency improvement, respectively. In addition, the LL architecture has 55%, 44%, and 76% reduction in point multiplication required time, respectively, over $GF(2^{233})$ , $GF(2^{163})$ , and $GF(2^{283})$ . Moreover, ASIC results show 100% energy improvement for the LC architecture implementation results over $GF(2^{163})$ . In addition, the LL architecture has 99% reduction in point multiplication required time, respectively, using a pentanomial.]]>659286928772082<![CDATA[FIR Filter Realization via Deferred End-Around Carry Modular Addition]]>${2}^{n} pm delta (delta ge 3)$ are commonly used. However, additional weighted ${2}^{i}(i>1)$ end-around carries (EACs) slow down and complicate the required modular adders in comparison to modulo-(${2}^{n}-1$ ) adders. For example, for $delta =3$ , the modular sum is obtained via $A+Bmp 3{c}_{mathrm {out}}$ , where ${A}$ and ${B}$ are modulo-(${2}^{n}pm 3$ ) operands and ${c}_{mathrm {out}}$ is the carryout of binary addition $A+B$ . In this paper, a new multioperand modular adder is proposed, where the key improvement is that all the required EAC additions (e.g., $+ 3c_{mathrm {out}}$ ) are postponed until after the last filter tap, whereby tens of addition operations take place without the EAC secondary addition; hence considerable savings of time, area consumption, and power dissipation. The proposed deferred EAC addition scheme has been applied to three previous relevant works. The corresponding synthesis results showed over 11%&#-
2013;32%, 27%–29%, and 21%–37%, reductions in delay, area, and power measures, respectively. This is achieved despite area and power overhead of the few appended stages into the pipelined architecture of the filter, which are nevertheless shown to become less significant as the number of filter taps grows.]]>659287828883675<![CDATA[A Hardware-Efficient Feedback Polynomial Topology for DPD Linearization of Power Amplifiers: Theory and FPGA Validation]]>3), the coefficients extractor could hardly be implemented efficiently in the field-programmable gate array (FPGA). Here, we propose a division-free line-searched-based recursive least square algorithm for adaptive linear and nonlinear coefficient estimation, relaxing the computational complexity to O(N) and supporting adaptive estimation in the FPGA. Our DPD experiments demonstrate both identification and predistortion procedures fully implemented in the FPGA. The measured error vector magnitude is reduced from 10.1% to <3.2%, and the adjacent channel leakage ratio (ACLR) is improved from −28.4 to −46.1 dBc, for a 20-MHz 64-QAM orthogonal frequency division multiplexing signal. For carrier-aggregation signals, the ACLR is improved from −35.8 to −45.3 dBc.]]>659288929023677<![CDATA[Analog Circuit Implementation of Fractional-Order Memristor: Arbitrary-Order Lattice Scaling Fracmemristor]]>659290329163049<![CDATA[A Phase Tunable Rotary Traveling Wave Oscillator: Analysis and Calibration]]>$mu$ m CMOS technology with a 1.8-V supply voltage. The evaluations show good agreement between analytical phase-error equations and simulation results. Also, appropriate simulations confirm the validity of the calibration method that is introduced in this paper.]]>659291729282365<![CDATA[Process Scalability of Pulse-Based Circuits for Analog Image Convolution]]>659292929382056<![CDATA[Generating the Closed-Form Second-Order Characteristics of Analog Differential Cells by Symbolic Perturbation]]>659293929501173<![CDATA[Observer-Based Adaptive SMC for Nonlinear Uncertain Singular Semi-Markov Jump Systems With Applications to DC Motor]]>659295129601485<![CDATA[New Approach to Fixed-Order Output-Feedback Control for Piecewise-Affine Systems]]>$mathscr {H}_{infty }$ setup. In particular, the conventional output-feedback closed-loop system is first augmented with the introduction of the input vector, and a descriptor presentation of PWA system is acquired. Then, a bounded real lemma is derived for the resulting PWA system, which is realized by the construction of a smooth piecewise Lyapunov function and application of the S-procedure. Furthermore, by availing oneself of the descriptor formulation, the fixed-order PWA output-feedback controller synthesis is carried out in a unified framework. An illustrative example is provided to show the efficacy and impact of the proposed control design methodology in a Chua’s circuit.]]>65929612969790<![CDATA[Robust Reconstruction of Continuously Time-Varying Topologies of Weighted Networks]]>659297029821754<![CDATA[Toward Stronger Robustness of Network Controllability: A Snapback Network Model]]>${q}$ -snapback network, is introduced. Basic topological characteristics of the network, such as degree distribution, average path length, clustering coefficient, and Pearson correlation coefficient, are evaluated. The typical 4-motifs of the network are simulated. The robustness of both state and structural controllabilities of the network against targeted and random node- and edge-removal attacks, with comparisons to the multiplex congruence network and the generic scale-free network, are presented. It is shown that the ${q}$ -snapback network has the strongest robustness of controllabilities due to its advantageous inherent structure with many chain and loop motifs.]]>659298329912343<![CDATA[Resilient Filtering for Linear Time-Varying Repetitive Processes Under Uniform Quantizations and Round-Robin Protocols]]>659299230042596<![CDATA[Finite Frequency Filtering Design for Uncertain Discrete-Time Systems Using Past Output Measurements]]>$mathcal H_{infty }$ filtering design for polytopic uncertain discrete-time systems using past output measurements. The noise is assumed to be restricted in a finite frequency range, i.e., the low, middle, or high frequency range. The objective is to design an admissible filter with past output measurements of the system, guaranteeing the asymptotic stability of the filtering error system with a prescribed finite frequency $mathcal H_{infty }$ disturbance attenuation level. Based on past output measurements together with the parameter-dependent Lyapunov function and projection lemma, a new sufficient condition for robust finite frequency $mathcal H_{infty }$ performance is first derived, and then, the filter synthesis is developed. It is shown that the filter gains can be obtained by solving a set of linear-matrix-inequalities. Finally, two examples are given to demonstrate the advantages and effectiveness of the proposed approach.]]>659300530131235<![CDATA[A 36-Gb/s 1.3-mW/Gb/s Duobinary-Signal Transmitter Exploiting Power-Efficient Cross-Quadrature Clocking Multiplexers With Maximized Timing Margin]]>2.]]>659301430265362<![CDATA[Near-Field MIMO Communication Links]]>659302730363176<![CDATA[A 3.9 mW Bluetooth Low-Energy Transmitter Using All-Digital PLL-Based Direct FSK Modulation in 55 nm CMOS]]>2. The phase noise is −119 dBc/Hz at a 1 MHz offset with frequency of 2.44 GHz. TX output power levels of 1.6 and 10 dBm have a power consumption of 3.9 and 18 mW, respectively. The power control ranges for the 1.6 and 10 dBm modes are 25 and 23 dB, respectively. With the RDF, when the output level is +1.6 dBm, the second, and third harmonic distortions at the TX output are −44 and −49 dBm, respectively. The proposed TX achieves an error vector magnitude of 3.48% at an output power level of +1.6 dBm.]]>659303730484503<![CDATA[A Continuous Sweep-Clock-Based Time-Expansion Impulse-Radio Radar]]>2. The measurements show that the echo pulses are recovered with a millimeter range resolution, while dissipating 30 mW. Respiration motions are successfully captured with the prototype radar.]]>659304930592461<![CDATA[A Mixed-Signal Technique for TX-Induced Modulated Spur Cancellation in LTE-CA Receivers]]>659306030734440<![CDATA[Hardware Implementation and Performance Analysis of Resource Efficient Probabilistic Hard Decision LDPC Decoders]]>659307430842538<![CDATA[Tri-Phasing Modulation for Efficient and Wideband Radio Transmitters]]>659308530984157<![CDATA[A Monolithic High-Voltage Li-Ion Battery Charger With Sharp Mode Transition and Partial Current Control Technique]]>$mu text{m}$ 1P3M bipolar-CMOS-DMOS HV process. With a 25-V input voltage, the output voltage (i.e., battery voltage) may range from 6 to 22 V and the maximum charging current is 2.5 A. The peak efficiency reaches 97%, occurring at 1-A charging current.]]>659309931094589<![CDATA[Dual-Phase-Shift Control Scheme With Current-Stress and Efficiency Optimization for Wireless Power Transfer Systems]]>659311031213341<![CDATA[IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors]]>6593122312273<![CDATA[IEEE Access]]>659312331231325<![CDATA[Introducing IEEE Collabratec]]>659312431242096<![CDATA[IEEE Circuits and Systems Society Information]]>659C3C3108