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TOC Alert for Publication# 8919 2015March 02<![CDATA[Table of Contents]]>623C1C4172<![CDATA[IEEE Transactions on Circuits and Systems—I: Regular Papers publication information]]>623C2C2131<![CDATA[Power Management Analysis of Inductively-Powered Implants with 1X/2X Reconfigurable Rectifier]]>$mu{rm m}$ CMOS process. Measurement results verify the correctness of the analysis and demonstrate the effectiveness of the matching compensation method.]]>6236176241982<![CDATA[Comparative Analysis of Simulation-Based Methods for Deriving the Phase- and Gain-Margins of Feedback Circuits With Op-Amps]]>6236256342040<![CDATA[A Low Phase Noise Injection-Locked Programmable Reference Clock Multiplier With a Two-Phase PVT-Calibrator for <formula formulatype="inline"><tex Notation="TeX">$DeltaSigma$</tex></formula> PLLs]]>$(DeltaSigma)$ noise of $DeltaSigma$ phase-locked loops (PLLs) is proposed. By adopting a two-phase PVT-calibrator that switches the calibration resolution, the clock multiplier can reduce the frequency-acquisition time, as well as tightly regulate the real-time degradation of the phase noise. To improve the performance of the calibration method utilizing two identical oscillators, the self-injection pulse generator that balances the loadings of two oscillators is proposed. In addition, this work presents a systematic design methodology that minimizes the degradation of the phase noise over the PVT variations, based on the phase noise analysis of injection-locking. The clock multiplier was designed with the prototype $DeltaSigma$ PLL in the 65-nm CMOS process. It can provide five reference frequencies, i.e., 19.2, 28.8, 48, 57.6, and 96 MHz. The phase noise of the 96-MHz signal was $-$130.0 and $-$131.8 dBc/Hz at 100 kHz and 1 MHz offsets, respectively; the performance of low phase noise was confirmed over temperature variations. The total active area was 0.062 mm2, and the power consumption was 1.6–1.9 mW. By switching the reference frequency from 19.2 to 96 MHz, the phase noise of the prototype PLL at the 10-MHz offset from the 4.4-GHz signal was improved from $-$120.1 to $-$138.6 dBc/Hz.]]>6236356442845<![CDATA[A 40-nm CMOS, 1.1-V, 101-dB Dynamic-Range, 1.7-mW Continuous-Time <formula formulatype="inline"><tex Notation="TeX">$SigmaDelta$</tex> </formula> ADC for a Digital Closed-Loop Class-D Amplifier]]>$SigmaDelta$ modulator designed for closing the feedback loop of a digital class-D audio amplifier. The closed-loop digital class-D amplifier fully exploits the potential of the used 40-nm CMOS technology to achieve at the same time the flexibility of digital implementations and the performance of analog solutions. The proposed $SigmaDelta$ modulator consumes 1.7 mW from a 1.1-V power supply, achieving 101-dB dynamic-range $(DR)$ and 72-dB peak signal-to-noise and distortion ratio $(SNDR)$. The active-RC implementation allows the 1.1-V $SigmaDelta$ modulator inputs to be directly connected to the 5-V class-D amplifier power stage outputs and inherently guarantees third-order anti-aliasing filtering.]]>6236456532182<![CDATA[PN-Assisted Deterministic Digital Background Calibration of Multistage Split-Pipelined ADC]]>A digital background calibration technique to treat capacitor mismatch, residue gain error, and nonlinearity in a pipelined ADC based on the split-ADC architecture is reported. Although multiple works have been reported before on the split- calibration of pipelined ADCs, none of them is comprehensive, i.e., capacitor mismatch, residue gain error, and nonlinearity are never treated in one work at the same time. We, also for the first time, recognize the multistage pipelined ADC with residue nonlinearity calibration as a Nonlinear Least Squares problem. Behavioral simulation results demonstrate the efficacy of the technique, in which the SNDR and SFDR performance of a 15-bit split-pipelined ADC are improved from 42 dB and 50 dB to 88 dB and 102 dB on average, respectively.]]>6236546612071<![CDATA[A 1.2-V 4.2-<formula formulatype="inline"> <tex Notation="TeX">$hbox{ppm}/^{circ}hbox{C}$</tex></formula> High-Order Curvature-Compensated CMOS Bandgap Reference]]>$hbox{ppm}/^{circ}hbox{C}$ over a wide temperature range of 160 $^{circ}hbox{C}$$(-hbox{40}sim hbox{120}~^{circ}hbox{C})$ at a power supply voltage of 1.2 V. The average TC for 8 random samples is approximately 9.3 $hbox{ppm}/^{circ}hbox{C}$. The measured power-supply rejection ratio (PSRR) of $-$30 dB is achieved at the frequency of 100 kHz. The total chip size is 0.063 ${rm mm}^{2}$ with a standard 0.13-$mu{rm m}$ CMOS process.]]>6236626702150<![CDATA[A Comparative Analysis of Phase-Domain ADC and Amplitude-Domain IQ ADC]]>6236716791552<![CDATA[Implementation of Quantized-State System Models for a PLL Loop Filter Using Verilog-AMS]]>$mu{rm m}$ CMOS phase-locked loop (PLL), and enables a truly event-driven simulation of the entire mixed-signal PLL circuit. First- and second-order (QSS and QSS2, respectively) models of the PLL loop-filter implemented in Verilog-AMS are first described in detail. These models do not rely on analog nets, and use only the event-based solver. Then, simulation results are compared to reference SPICE simulation results to prove the validity of the QSS method. The entire PLL circuit is finally simulated using the QSS model of the loop-filter, charge-pump and VCO, in conjunction with standard high-level models of the PLL digital circuits. To verify the proposed QSS method, measured phase noise is compared with simulated phase noise. It is shown that simulated phase noise accurately predicts the measured phase noise with improved accuracy, and an increase in simulation efficiency by more than 50 times. Measured and simulated results generally demonstrate the feasibility of the QSS modeling for mixed-signal circuit simulation and design.]]>6236806881540<![CDATA[A 6-to-10-Bit 0.5 V-to-0.9 V Reconfigurable 2 MS/s Power Scalable SAR ADC in 0.18 <formula formulatype="inline"> <tex Notation="TeX">$mu{rm m}$</tex></formula> CMOS]]>$mu{rm m}$ CMOS process covers 6–10 bit resolution and 0.5 V–0.9 V power supply range. At 10 bit mode and 0.5 V operation, the proposed SAR ADC achieves 56.36 dB SNDR and 67.96 dB SFDR with sampling rate up to 2 MS/s, corresponding to a figure-of-merit of 20.6 fJ/conversion-step. The proposed ADC core occupies an active area of about $300times 700~ mu{rm m}^{2}$.]]>6236896961606<![CDATA[An Ultra-Low Voltage Level Shifter Using Revised Wilson Current Mirror for Fast and Energy-Efficient Wide-Range Voltage Conversion from Sub-Threshold to I/O Voltage]]>$mu{rm m}$ show that compared with the Wilson current mirror based level shifter, the proposed level shifter improves the delay, switching energy and leakage power by up to $3times$, $19times$, $29times$ respectively, when converting 0.3 V to a voltage between 0.6 V and 3.3 V. More specifically, it achieves 1.03 (or 1.15) FO4 delay, 39 (or 954) fJ/transition and 160 (or 970) pW leakage power, when converting 0.3 V to 1.8 V (or 3.3 V), which is better than several state-of-the-art level shifters for similar range voltage conversion. The measurement results also show that the proposed level shifter has good delay scalability with supply voltage scaling and low sensitivity to process and temperature variations.]]>6236977061827<![CDATA[A Fully-Integrated Low-Dropout Regulator With Full-Spectrum Power Supply Rejection]]>$mu{rm A}$ of total quiescent current. For a 1.2 V input voltage and 1 V output voltage, the measured undershoot and overshoot is only 43 mV and 82 mV, respectively, for load transient of 0 $mu{rm A}$ to 10 mA within edge times of 200 ps. It achieves a transient response time of 1.15 ns and the figure-of-merit (FOM) of 5.74 ps. PSR is measured to be better than $-$12 dB over the whole spectrum (DC to 20 GHz tested). The prototype chip measures $260times 90 mu{rm m}^{2}$, including 140 pF of stacked on-chip capacitors.]]>6237077162674<![CDATA[Phase Noise Effect on Sine-Shaped Feedback DACs Used in Continuous-Time <formula formulatype="inline"><tex Notation="TeX">$SigmaDelta$</tex></formula> ADCs]]>$SigmaDelta$ ADCs for its immunity to clock jitter. However, in a sine-shaped DAC, the carrier is used as an analog signal to mix with the data, consequently, all the carrier noise appears in the sine-shaped data. The effect of carrier noise was studied before, but the analysis was based on the assumption of white noise, which is not true in real PLLs. In this work, we present a simple, intuitive, and accurate model that can predict the effect of the clock noise on the sine-shaped DAC. The model is generic and can be applied for any noise profile. We tried to keep it as close as possible to the noise profile of a real clock source. The analysis is verified by simulation and measurement results.]]>6237177242134<![CDATA[Optimal Tuning of Inductive Wireless Power Links: Limits of Performance]]>6237257321733<![CDATA[A Heterogeneous Reconfigurable Cell Array for MIMO Signal Processing]]>${rm mm}^{2}$ core area and is capable of running at 500 MHz. For illustration, three computationally intensive blocks, namely channel estimation, channel matrix pre-processing, and hard-output data detection, of a 4 $times$ 4 MIMO processing chain in a 20 MHz 64-QAM 3GPP long term evolution advanced (LTE-A) downlink are mapped and processed in real-time. Implementation results report a maximum throughput of 367.88 Mb/s with 1.49 nJ/b energy consumption. Compared to state-of-the-art designs, the proposed solution outperforms programmable platforms by several orders of magnitude in energy efficiency, and achieves similar level of efficiency to that of ASICs.]]>6237337421849<![CDATA[A 10-Gb/s, 1.24 pJ/bit, Burst-Mode Clock and Data Recovery With Jitter Suppression]]>$0.22{rm UI}_{rm pp}$ jitter stressed input data at 10 Gbps, the recovered clock jitter at 2 GHz is 2.94 ${rm ps}_{rm rms}$. The prototype is fabricated using 55 nm CMOS technology. The core area is 0.03 ${rm mm}^{2}$ only. It dissipates 12.4 mW from 1 V supply.]]>6237437511935<![CDATA[A 60 V Tolerance Transceiver With ESD Protection for FlexRay-Based Communication Systems]]>$mu{rm m}$ CMOS mixed-signal based generation II HV BCD process. The measurement results justify the functional correctness and 60 V tolerance of the proposed FlexRay transceiver design.]]>6237527602369<![CDATA[A High-Throughput VLSI Architecture for Hard and Soft SC-FDMA MIMO Detectors]]>$4.5times 10^{2}$ and $7times 10^{4}$ times fewer Euclidean distance (ED) calculations in the 16-QAM and 64-QAM schemes, respectively. The proposed design for the 16-QAM scheme is fabricated in a 0.13$mu{rm m}$ CMOS technology and fully tested, achieving a 1.332 Gbps throughput, reporting the first fabricated design for SC-FDMA MIMO detectors to-date. A soft version of the proposed architecture is also introduced, which is customized for coded systems.]]>6237617702511<![CDATA[Highly Reliable Coding Methods for Emerging Applications: Archive and Enterprise Solid-State Drives (SSDs)]]>$n$-out-of-8 level cell $(n{rm LC})$ is proposed for archival applications which require significantly long data-retention time with small write/erase cycle. On the other hand, for applications with large write/erase cycle and short data-retention time (enterprise application, etc.), universal asymmetric coding (UAC) is proposed. $n{rm LC}$ reduces the number of memory states to improve the reliability with low cost overhead. In 7LC, the bit-error rate (BER) reduction will be 79% after 1k-year data retention while seven memory states are efficiently used out of eight states. By considering $n{rm LC}$ with error-correcting codes (ECCs), the optimum number of cell levels $(n)$ can be determined to minimize the bit-cost with given acceptable data-retention time. In UAC, the coding method is changed according to the write/erase cycle and data-retention time to keep the BER low. As a result, BER is reduced by 52% at maximum, compared with the original random pattern.]]>6237717802412<![CDATA[Analysis and Design of a Core-Size-Scalable Low Phase Noise <formula formulatype="inline"><tex Notation="TeX">$LC$</tex> </formula>-VCO for Multi-Standard Cellular Transceivers]]>$LC$-voltage-controlled oscillator (VCO) for multi-standard cellular transceivers was fabricated in a 65-nm CMOS process. Theoretical analysis showed that when core current is small a VCO with a larger core-size can achieve lower phase noise. However, when core current is large, a VCO with a smaller core-size can lower phase noise. Based on the analysis, the effective core-size of the VCO was designed to be scalable according to the core current, by switching the secondary core-transistors on or off. Thus, the proposed VCO becomes adaptive to multi-standard cellular transceivers. By turning on the switch, the VCO can operate in the low power (LP) mode for standards that require moderate phase noise in a tight power budget. On the other hand, by turning off the switch, the VCO can operate in the low noise (LN) mode for standards that demand stringent phase noise in a relaxed power budget. When the core current is set to 4 mA, the VCO in the LP mode achieved the phase noise of $-$127.9 dBc/Hz at the 3 MHz offset from 3.3-GHz signals. When the core current was set to 15 mA, phase noise of the VCO in the LN mode was minimized to $-$137.5 dBc/Hz at the same offset. The figure of merit (FOM) was $-$184.8 and $-$186.5 dB, respectively.]]>6237817902673<![CDATA[Superregenerative Reception of Narrowband FSK Modulations]]>$-$114 dBm in the HF band, validate the proposed approach.]]>6237917981415<![CDATA[An 18.7-Gb/s 60-GHz OOK Demodulator in 65-nm CMOS for Wireless Network-on-Chip]]>${rm mm}^{2}$. A maximum data rate of 18.7 Gb/s with a bit-error rate less than $10^{-12}$ is demonstrated through measurements, which translates to a bit-energy efficiency of 0.25 pJ/bit.]]>6237998062071<![CDATA[Selective State Retention Power Gating Based on Formal Verification]]>6238078151510<![CDATA[An Analytical Approach to Thermal Design and Optimization With a Temperature-Dependent Power Model]]>6238168241569<![CDATA[Distributed Consensus of Multi-Agent Systems With Input Constraints: A Model Predictive Control Approach]]>6238258343073<![CDATA[Variations in Nanometer CMOS Flip-Flops: Part II—Energy Variability and Impact of Other Sources of Variations]]>6238358431705<![CDATA[Design Methodology for Highly Reliable, High Performance ReRAM and 3-Bit/Cell MLC NAND Flash Solid-State Storage]]>$R_{rm Ref}$ (CR), flexible $R_{rm Ref}$ (FR), adaptive asymmetric coding (AAC), verify trials reduction (VTR), bits/cell optimization (BCO), and balanced RAID-5/6 are proposed. CR, FR, AAC, and VTR are for ReRAM. CR and FR change the read-reference resistance $(R_{rm Ref})$ to reduce the BER. AAC first increases the population of Set and then Reset. The BER reduction with FR and AAC is 69 and 78% with 60 and 75% asymmetry, respectively. In VTR, by changing the number of acceptable bit-errors, the total Reset time is reduced by 97% at maximum with small ECC calculation overhead. The reliability of 3-bit/cell MLC NAND flash memory is improved by BCO and balanced RAID-5/6. BCO reallocates 3-bit/cell MLC to 2-bit/cell MLC and single-level cell (SLC) and the write/erase cycle increases by over 22-times. Balanced RAID-5/6 evenly allocates upper/middle/lower pages to a stripe to reduce the RAID failure rate by 98%.]]>6238448532407<![CDATA[Efficient Subquadratic Space Complexity Architectures for Parallel MPB Single- and Double-Multiplications for All Trinomials Using Toeplitz Matrix-Vector Product Decomposition]]>$GF(2^{m})$ for all trinomials can be realized efficiently by the recursive TMVP (RTMVP) formulation. To perform the three-operand multiplication with the RTMVP formulation, we have derived a new RTMVP decomposition scheme. The proposed single- and double-multiplications can, respectively, use TMVP and RTMVP decompositions to achieve subquadratic space complexity architectures. By theoretical analysis, it is shown that the proposed subquadratic multipliers involve significantly less space complexity and less computation time compared to the existing subquadratic multipliers using TMVP and Karatsuba algorithms. Moreover, our proposed double-multiplication design can be used in several applications involving successive multiplications, such as exponentiation, inversion, and elliptic curve point multiplication.]]>6238548622112<![CDATA[Fine-Grained Critical Path Analysis and Optimization for Area-Time Efficient Realization of Multiple Constant Multiplications]]>6238638721706<![CDATA[SoC-Based Architecture for an Ultrasonic Phased Array With Encoded Transmissions]]>$pm hbox{64}^{circ}$ .]]>6238738802186<![CDATA[Low-Latency High-Throughput Systolic Multipliers Over <formula formulatype="inline"><tex Notation="TeX">$GF(2^{m})$</tex> </formula> for NIST Recommended Pentanomials]]>$GF(2^{m})$ for National Institute Standard Technology (NIST) pentanomials are not so abundant. In this paper, we present two pairs of low-latency and high-throughput bit-parallel and digit-serial systolic multipliers based on NIST pentanomials. We propose a novel decomposition technique to realize the multiplication by several parallel arrays in a 2-dimensional (2-D) systolic structure (BP-I) with a critical-path of $2T_{X}$, where $T_{X}$ is the propagation delay of an XOR gate. The parallel arrays in 2-D systolic structure are then projected along vertical direction to obtain a digit-serial structure (DS-I) with the same critical-path. For high-throughput applications, we present another pair of bit-parallel (BP-II) and digit-serial (DS-II) structures based on a novel modular reduction technique, where the critical-path is reduced to $(T_{A}+T_{X})$, $T_{A}$ being the propagation delay of an AND gate. A strategy for data sharing between a pair of processing elements (PEs) of adjacent systolic arrays has been proposed to reduce area-complexity of BP-I and BP-II further. From synthesis results, it is shown that the proposed multipliers have significantly lower latency and higher throughput than the existing designs. To the best of authors' knowledge, this is the first report on low-latency systolic multipliers for finite fields where latency is independent of field-order.]]>6238818903737<![CDATA[A Generic Model of Memristors With Parasitic Components]]>$A$ and frequency $f$ of the input signal. This deviation from the ideal case is often caused by parasitic circuit elements exhibited by real memristive devices. In this paper, we propose a generic memristive circuit model by adding four parasitic circuit elements, namely, a small capacitance, a small inductance, a small DC current source, and a small DC voltage source, to the memristive device. The adequacy of this model is verified experimentally and numerically with two thermistors (NTC and PTC) memristors.]]>6238918982579<![CDATA[Synchronizing a Weighted and Weakly-Connected Kuramoto-Oscillator Digraph With a Pacemaker]]>6238999051878<![CDATA[FPAA/Memristor Hybrid Computing Infrastructure]]>6239069152123<![CDATA[Impedance-Based Local Stability Criterion for DC Distributed Power Systems]]>6239169252772<![CDATA[IEEE Transactions on Circuits and Systems—I: Regular Papers information for authors]]>623926926121<![CDATA[IEEE membership can help you reach your personal goals]]>6239279272607<![CDATA[Expand your professional network with IEEE]]>6239289282237<![CDATA[IEEE Circuits and Systems Society Information]]>623C3C3118