<![CDATA[ IEEE Transactions on Circuits and Systems I: Regular Papers - new TOC ]]>
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TOC Alert for Publication# 8919 2018April 19<![CDATA[Table of contents]]>655C1C4175<![CDATA[IEEE Transactions on Circuits and Systems—I:Regular Papers publication information]]>655C2C260<![CDATA[Analysis of the Effect of Source Capacitance and Inductance on $N$ -Path Mixers and Filters]]>$R-C$ passive $N$ -path mixers and filters enable interference-robust radio receivers with a flexibly programmable center frequency defined by a digital multi-phase clock. The radio frequency (RF) range of these circuits is limited by parasitic shunt capacitances, which introduce signal loss and degrade noise figure. Moreover, the linear periodically time varying nature of switch $R-C$ circuits results in unwanted signal folding which needs to be suppressed by linear time- invariant (LTI) prefiltering by passive LC filters. This paper analyzes the interaction between capacitive or inductive LTI prefiltering and an $N$ -path mixer or filter, leveraging an analysis technique based on the impulse response of the adjoint network. Previously reported results for an inductive source impedance are derived in a simpler fashion, while providing circuit intuition. Moreover, new results for $N$ -path receivers with a shunt capacitor, and a combination of a series inductor and shunt capacitor are derived, as well as design criteria to minimize loss and frequency shifting in the peak response of these circuits.]]>655146914802413<![CDATA[The Impact of LO Phase Noise in N-Path Filters]]>655148114944298<![CDATA[Transformer-Based Input Integrated Matching in Cascode Amplifiers: Analytical Proofs]]>655149515043338<![CDATA[TIME—Tunable Inductors Using MEmristors]]>655150515152176<![CDATA[Theory and Demonstration of Noisy Oscillator Samplers for Clock Jitter and Phase Delay Measurement]]>2 and consuming 0.89 mW, achieves a root mean square error of 0.1 and 0.31 ps in externally referenced and self-referenced jitter measurements, respectively.]]>655151615282422<![CDATA[An RF-Powered Wireless Temperature Sensor for Harsh Environment Monitoring With Non-Intermittent Operation]]>$1.05~mutext{W}$ at room temperature, which enables continuous operation of the sensor from an incident energy of −16 dBm. The sensor is tested between −10 °C to 100 °C exhibiting a minimum sensitivity of 238 Hz/°C at −10 °C and a maximum sensitivity of 31.648 kHz/°C at 100 °C. The predicted temperature error is −2.6 °C to 1.3 °C using a two-point calibration within the range of 10 °C to 100 °C. With a conversion time of 25 ms, 0.046 °C (rms) resolution is achieved. Fabricated in IBM’s 130-nm CMOS technology, the proposed sensor occupies a die area of 0.23 mm^{2}.]]>655152915424219<![CDATA[A Miniaturized Two-Axis Ultra Low Latency and Low-Power Sun Sensor for Attitude Determination of Micro Space Probes]]>$ {88~mu s}$ . The sun sensor consumes $ {6.3~mu W}$ in normal operation, and has a precision of 0.98°, and a field of view of 144°. The high temporal resolution, low power consumption, and small QFN64 package make this sun sensor suitable for space probe and sounding rocket applications, where low temporal latency and payload size are essential. This sun sensor is designed to be employed in the sounding rocket attitude determination system as part of the 4DSpace research initiative to study ionospheric plasma disturbances.]]>655154315542827<![CDATA[Exposure-Programmable CMOS Pixel With Selective Charge Storage and Code Memory for Computational Imaging]]>$10 times 10$ -pixel prototype chip is fabricated in a 0.13-$mu text{m}$ 8-metal 1-poly CMOS process with shared pixel output wires and two 3.3-V power supplies. Each computational pixel is $12.1~ mu text {m} times 12.2 ~mu text {m}$ with a fill factor of 33.2%. Measurement results confirm that at a frame rate of 60 f/s, the proposed pixel is capable of performing both temporal and spatial exposure encoding. The proposed pixel design paves a promising path to achieve on-chip temporal-spatial exposure encoding directly on the sensor focal plane for computational imaging.]]>655155515662937<![CDATA[A Near-Threshold Voltage Oriented Digital Cell Library for High-Energy Efficiency and Optimized Performance in 65nm CMOS Process]]>655156715803153<![CDATA[Auto-Erasable RRAM Architecture Secured Against Physical and Firmware Attacks]]>655158115903490<![CDATA[A Low-Overhead Dynamic TCAM With Pipelined Read-Restore Refresh Scheme]]>655159116013942<![CDATA[Joint Sparsity and Order Optimization Based on ADMM With Non-Uniform Group Hard Thresholding]]>$ell _{0}$ and non-uniform overlapped group $ell _{0}$ norms, which are not convex, a global optimal solution is difficult to obtain. To find an approximate solution of the non-convex problem, existing approaches repeat the following steps: 1) approximate the cost function; 2) find candidates of zero coefficients by minimizing the cost function; and 3) set them to zero. On the other hand, this paper directly solves the optimization problem, without any approximation to the cost function, by using the alternating direction method of multipliers with the pseudo-proximity operators of $ell _{0}$ and non-uniform non-overlapped group $ell _{0}$ norms. Experimental results show that resulting filters designed by the proposed method have sparser coefficients and lower orders, while satisfying filter specifications, such as an error from a desired frequency response.]]>655160216131987<![CDATA[Optimized Fundamental Signal Processing Operations For Energy Minimization on Heterogeneous Mobile Devices]]>655161416272995<![CDATA[CIPRNG: A VLSI Family of Chaotic Iterations Post-Processings for $mathbb {F}_{2}$ -Linear Pseudorandom Number Generation Based on Zynq MPSoC]]>655162816412099<![CDATA[Data and Hardware Efficient Design for Convolutional Neural Network]]>$300times sim 600times $ compared with the non-reused case. The whole CNN implementation of the target network is generated optimally for both hardware and data efficiency under design resource constraints, which can be run-time reconfigured by the layer optimized parameters to achieve real-time and end-to-end CNN acceleration. An implementation example for AlexNet consumes a 1.783 M gate count for 216 MACs and a 142.64 kb internal buffer with TSMC 40 nm process, and achieves 99.7 and 61.6 f/s under 454 MHz clock frequency for the convolutional layers and the whole AlexNet, respectively.]]>655164216514894<![CDATA[Definition of Simplified Frequency-Domain Volterra Models With Quasi-Sinusoidal Input]]>655165216632224<![CDATA[Improving Time-Efficiency of Fault-Coverage Simulation for MOS Analog Circuit]]>655166416741397<![CDATA[Brushing Up on the Urbanek Black Box Arc Model]]>6) as quenching medium. It has the unique characteristic to account for the dielectric breakdown that possibly reignites the arc. We show some of its main features that have been almost hidden from the first publication of the model in the literature. The conductance in the Urbanek model plays two roles: 1) it effectively represents the conductance of the burning arc when positive and 2) it is a thermodynamic indicator when negative. This thermodynamic indicator is used to eventually trigger a restrike of the arc. We show that this switching behavior can be formally analyzed by considering the model as an hybrid dynamical system. In this paper, we reconsider it and show its main dynamic properties through some case studies.]]>655167516831152<![CDATA[Output Group Synchronization for Networks of Heterogeneous Linear Systems Under Internal Model Principle]]>virtual reference generators. Finally, simulations are carried out to validate the theoretical findings.]]>655168416952440<![CDATA[Leader-Following Consensus of Multi-Agent Systems With Switching Networks and Event-Triggered Control]]>655169617062645<![CDATA[Fault Detection for Linear Discrete Time-Varying Systems Subject to Random Sensor Delay: A Riccati Equation Approach]]>$mathcal {H}_{-}/mathcal {H}_{infty }$ or $mathcal {H}_{infty }/mathcal {H}_{infty }$ FD performance index, which aims to enhance the ratio of fault sensitivity/disturbance attenuation. The other one is to find the filter parameter matrices such that the error between the residual and the fault is minimized in the $mathcal {H}_{infty }$ sense. By employing stochastic analysis and introducing some adjoint operator based optimization approaches, analytical solutions to the aforementioned FDF design problem are derived via solving recursive Riccati equations. An illustrative example is given to show the effectiveness of the proposed methodologies.]]>655170717161318<![CDATA[A 1.58 Gbps/W 0.40 Gbps/mm2 ASIC Implementation of MMSE Detection for $128times 8~64$ -QAM Massive MIMO in 65 nm CMOS]]>$128times 8~64$ -QAM massive MIMO system. First, a diagonal-based systolic array with single-sided input is adopted; this array eliminates the throughput limitation. Second, a weighted Jacobi-iteration-based architecture is proposed to iteratively achieve matrix inversion, thereby reducing the computational load and exploiting the potential parallelism of the matrix inversion. Third, an approximated architecture is proposed to compute the log-likelihood ratio. This architecture is verified on an FPGA and fabricated onto a 2.57 mm^{2} silicon with TSMC 65 nm CMOS technology, thereby achieving a 1.02 Gbps data rate at 680 MHz while dissipating 646 mW. The results indicate an energy efficiency of 1.58 Gbps/W and an area efficiency of 0.40 Gbps/mm^{2}, which are $2.93times $ and $2.86times $ that of state-of-the-art similar designs with CMOS technology, respectively.]]>655171717302607<![CDATA[Successive Approximation RF Reflectometer for Antenna Tuning in Cellular Handheld Devices]]>$850times 850~mu text{m}^{2}$ in 130-nm CMOS technology and consumes a maximum supply current of 400 $mu text{A}$ from a 2.8 V supply during detection. The device does not require frequency and temperature calibration when operating in scalar mode. A method for operating the same integrated circuit (IC) in vector detection mode is briefly introduced. The target application for the presented reflectometer IC is impedance sensing in antenna tuning RF front-ends.]]>655173117434419<![CDATA[A Sub-10 mV Power Converter With Fully Integrated Self-Start, MPPT, and ZCS Control for Thermoelectric Energy Harvesting]]>$5~Omega $ , the chip can provide a maximum output power of $229~mu text{W}$ with end-to-end efficiency of 71.5%.]]>655174417574026<![CDATA[An Active Diode Full-Wave Charge Pump for Low Acceleration Infrastructure-Based Non-Periodic Vibration Energy Harvesting]]>$100~{mu }text{F}$ capacitors. These large capacitors create a stable power supply for start-up from one low voltage AC input based off of bridge vibrations that are random and infrequent. Its rectification circuitry is fabricated in 180 nm CMOS on a 1.2 mm^{2} die. The circuit inputs, generated using a shaker table, are periodic sine-waves or non-periodic mechanical frequency up-converted vibration harvester outputs. Measurements show that the diode drop reduction allows cold start-up and boosting to >1.5 V with low power ($sim 8.5~{mu }text{W}$ ) non-periodic harvester outputs or 220 mV open circuit voltage periodic (~100 Hz) inputs. This IC demonstrates ~50% efficiency with an up-conversion-based harvester and ${sim } 1~{mu }text{W}$ active power dissipation.]]>655175817705340<![CDATA[IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors]]>6551771177153<![CDATA[IEEE Access]]>65517721772774<![CDATA[Introducing IEEE Collabratec]]>655177317732110<![CDATA[IEEE Foundation]]>65517741774200<![CDATA[IEEE Circuits and Systems Society Information]]>655C3C3105