<![CDATA[ IEEE Transactions on Circuits and Systems I: Regular Papers - new TOC ]]>
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TOC Alert for Publication# 8919 2019April 25<![CDATA[Table of contents]]>665C1C4189<![CDATA[IEEE Transactions on Circuits and Systems—I:Regular Papers publication information]]>665C2C277<![CDATA[Guest Editorial Special Issue on the IEEE International Symposium on Circuits and Systems 2018]]>6651669166968<![CDATA[A Study of Phase Noise and Frequency Error of a Fractional-N PLL in the Course of FMCW Chirp Generation]]>$mu text{s}$ at a carrier frequency of 62GHz. The noise measurements are in good agreement with the developed phase noise model. A programmable loop filter capacitance is suggested to accommodate the static phase offset and the resulting noise performance to the ramp slope.]]>665167016802864<![CDATA[Benefits of Using VCO-OTAs to Construct TIAs in Wideband Current-Mode Receivers Over Inverter-Based OTAs]]>$2.6times $ power reduction of the TIA resulting in up to $2times $ power reduction of the receiver for similar B1dB performance.]]>665168116913411<![CDATA[A Novel Convolution Computing Paradigm Based on NOR Flash Array With High Computing Speed and Energy Efficiency]]>$20times 20$ is executed using the NFA structure. We also prove the NOR Flash-driven convolution computing is capable of processing the image with a larger size. This paper presents a new approach to realize convolution computing with high speed and energy efficiency for the signal processing and convolution neural network.]]>665169217035586<![CDATA[A Fully Flexible Circuit Implementation of Clique-Based Neural Networks in 65-nm CMOS]]>2 silicon surface area. The proper functioning of the circuit is illustrated using two application cases: a keyword recovery application and an electrocardiogram classification. The neurons outputs are updated 83 ns after a stimulation, and a neuron needs an energy of 115 fJ to propagate a change at the input to its output.]]>665170417154671<![CDATA[A 10-Bit 200-kS/s 1.76-<inline-formula> <tex-math notation="LaTeX">$mu$ </tex-math></inline-formula>W SAR ADC With Hybrid CAP-MOS DAC for Energy-Limited Applications]]>${mu }text{m}$ CMOS technology achieves a signal-to-noise-and-distortion ratio / spurious-free dynamic range of 56.91 /68.56 dB at 99-kHz input under a 0.6-V power-supply, while consumes $1.76~{mu }text{W}$ at 200 kS/s for a figure of merit of 15.38 fJ/step. The peak DNL and INL are +0.27/−0.21 LSB and +0.43/−0.45 LSB, respectively. The ADC occupies a small active area of 0.097 mm^{2}.]]>665171617273096<![CDATA[A 1-MHz Relaxation Oscillator Core Employing a Self-Compensating Chopped Comparator Pair]]>$mu text{m}$ CMOS process, occupying the area of 0.032 mm^{2} and consuming around 160 $mu text{W}$ while running at 1 MHz. Employing a self-compensating chopped comparator structure, the designed oscillator exhibits a significant improvement in the frequency stability and control linearity, at the same time retaining a fast start-up and having a minimal overhead in the power consumption and area. Measured on 8 test chips, the frequency variation against temperature is ±0.26% in the temperature range from −40 to 125 °C, and the line sensitivity is ±0.08 %/V with the supply voltage changing from 3.0 to 4.5 V. The typical distortion parameters of the control characteristic are HD_{2} = −61.7 dB and HD_{3} = −93.2 dB at $Delta f_{text {osc}}=500 $ kHz. The measured jitter and phase noise at 10 kHz carrier offset are 235 ppm and −92 dBc/Hz, respectively, while the Allan deviation floor is 15 ppm.]]>665172817363173<![CDATA[A Novel Single-Inductor Injection-Locked Frequency Divider by Three With Dual-Injection Secondary Locking]]>2.]]>665173717451812<![CDATA[A Nanopower Biopotential Lowpass Filter Using Subthreshold Current-Reuse Biquads With Bulk Effect Self-Neutralization]]>$mu text{m}$ CMOS process occupying 269 $mu text{m},,times $ 383 $mu text{m}$ chip area. Measurements verify that the filter can operate from a 1.5-V single supply and consumes 5.25 nW, while providing a cutoff frequency of 100 Hz and input-referred noise of $39.38~mu text{V}_{mathrm {rms}}$ . The intermodulation-free dynamic range of 51.48 dB is obtained from a two-tone test of 50 and 60 Hz input frequencies. Compared with state-of-the-art nanopower lowpass filters using the most relevant and reasonable figure of merit, the proposed filter ranks the best.]]>665174617573646<![CDATA[Wide-Bandwidth, High-Linearity, 2.8-GS/s, 10-bit Accurate Sample and Hold Amplifier in 130-nm SiGe BiCMOS]]>2 and consumes an average power of 1.26 W. The SHA is a pseudo-differential open-loop design that includes two cascaded track-and-hold amplifiers, a high-speed clock driver, and externally adjustable current mirror biases. The high-speed clock drivers and buffers add 170 mW to the total power consumption. The measurements of the fabricated SHA show a 10-bit effective resolution across the 1-GHz IF bandwidth and < −61-dBc HD_{2} and HD_{3}.]]>665175817684788<![CDATA[ChipNet: Real-Time LiDAR Processing for Drivable Region Segmentation on an FPGA]]>665176917792424<![CDATA[Power and Area Efficient FPGA Building Blocks Based on Ferroelectric FETs]]>$16times $ , respectively, while compared with resistive random-access memory (RRAM)-based equivalents, the proposed designs improve the PDP by 1.14–$1.8times $ . The area of an FeFET-based FPGA is 8% smaller than a conventional CMOS-based FPGA.]]>665178017933301<![CDATA[A Low-Power Deep Neural Network Online Learning Processor for Real-Time Object Tracking Application]]>$1.33times $ higher throughput than the previous state-of-the-art DNN learning processor. Second, the new algorithms, binary feedback alignment (BFA), and dynamic fixed-point based run-length compression (RLC), are proposed and reduce power consumption through the reduction of external memory accesses (EMA). The BFA and dynamic fixed-point-based RLC reduce the EMA by 11.4% and 32.5%, respectively. Third, the new data feeding units, including an integral RLC (iRLC) decoder and a transpose RLC (tRLC) decoder, are co-designed to maximize throughput alongside the proposed algorithms. Finally, a dropout controller in this processor reduces redundant power consumption coming from the unified core and the data feeding architecture by the proposed dynamic clock-gating scheme. This enables the proposed processor to operate DNN online learning with 38.1% lower power consumption. Implemented with 65 nm CMOS technology, the 3.52 mm^{2} DNN online learning processor shows 126 mW power consumption and the processor achieves 30.4 frames-per-second throughput in the object tracking application.]]>665179418042929<![CDATA[CAR-Lite: A Multi-Rate Cochlear Model on FPGA for Spike-Based Sound Encoding]]>665180518172240<![CDATA[A CMOS V-Band PLL With a Harmonic Positive Feedback VCO Leveraging Operation in Triode Region for Phase-Noise Improvement]]>665181818304376<![CDATA[A <inline-formula> <tex-math notation="LaTeX">$64times64$ </tex-math></inline-formula> Pixel Vision Sensor for Local Binary Pattern Computation]]>$64times64$ pixel vision sensor embedding local binary pattern (LBP) computation implemented at pixel-level. The proposed technique is applied on four neighbours within a $3times3$ pixel kernel, while the operations are executed on-the-fly, during the sensor exposure time. Thanks to the pixel-level autoexposure control, processing over extended dynamic range is achieved. The number of transistors per pixel has been minimized in order to preserve the fill factor while keeping a reduced pixel size. The resulting binary information is stored on a dynamic memory and read out in a standard raster-scan mode. The proposed technique for the LBP estimation is made in the time domain and uses two voltage comparators per pixel. While the chronological order of comparators toggling identifies the brighter pixel, the voltage difference between the two thresholds sets the LBP sensitivity. The sensor is implemented in a CMOS $0.35~mu text{m}$ , featuring a 17-$mu text{m}$ pitch with 15% fill factor. The chip consumes $35~mu text{W}$ at 15 frames/s, powered at 3.3 V for the analog part and 1.5 V for the digital part.]]>665183118392219<![CDATA[Design of a 0.20–0.25-V, Sub-nW, Rail-to-Rail, 10-bit SAR ADC for Self-Sustainable IoT Applications]]>2. Measurement results show that the ADC achieves stable performance in the VDD range. At 0.225 V, the DNL and INL are within +1.04/−0.66 and +0.97/−1.04 LSB in the rail-to-rail input range, respectively. The measured peak SNDR at the Nyquist input frequency is 49.2 dB at 450 S/s. The whole ADC totally consumes 0.85 nW at 0.225 V including circuit leakages. The sub-nW power consumption makes it well suited for self-sustainable Internet-of-Things applications.]]>665184018522419<![CDATA[Novel Radiation Hardening Read/Write Circuits Using Feedback Connections for Spin–Orbit Torque Magnetic Random Access Memory]]>$40times $ smaller than the previous work, and restoring time is reduced by 30.6% with negligible area overhead.]]>665185318622409<![CDATA[Integrated Wide-Band CMOS Spectrometer Systems for Spaceborne Telescopic Sensing]]>665186318733603<![CDATA[A Generic Foreground Calibration Algorithm For ADCs With Nonlinear Impairments]]>665187418852525<![CDATA[Pulse Compression in Nondestructive Testing Applications: Reduction of Near Sidelobes Exploiting Reactance Transformation]]>665188618964825<![CDATA[Using Modified Bessel Functions for Analysis of Nonlinear Effects in a MOS Transistor Operating in Moderate Inversion]]>665189719072122<![CDATA[Computation-Performance Optimization of Convolutional Neural Networks With Redundant Filter Removal]]>665190819213655<![CDATA[Second-Order Trajectory Sensitivity Analysis of Hybrid Systems]]>665192219341332<![CDATA[Analysis of Parasitic Effects in Filamentary-Switching Memristive Memories Using an Approximated Verilog-A Memristor Model]]>2 devices implemented in a 250-nm BiCMOS IHP technology.]]>665193519473234<![CDATA[On Basic Boolean Function Graphene Nanoribbon Conductance Mapping]]>$V_{text {DD}}=$ 0.2 V outperform 7 nm @$V_{text {DD}}=$ 0.7 V CMOS counterparts by 2 to 3, 1 to 2, and 3 to 4, orders of magnitude in terms of delay, power consumption, and power-delay product, respectively, while requiring 2 orders of magnitude less active area. Subsequently, we investigate the effect of $V_{{text {DD}}}$ variations and the $V_{{text {DD}}}$ value lower bound. We demonstrate that the NOR butterfly GNR structures are quite robust as their conductance and delay are changing by no more than 2% and 6%, respectively, and that AND and NOR GNR geometries can operate even at 10 mV. Finally, we consider the aspects related to the practical realization of the proposed structures and conclude that even if there are still hurdles on the road ahead the latest graphene fabrication technology developments, e.g., surface-assisted synthesis, our proposal opens an alternative towards effective carbon-based nanoelectronic circuits and applications.]]>6651948195958605<![CDATA[Stability Test for Complex Matrices Over the Complex Unit Circumference via LMIs and Applications in 2D Systems]]>66519601969778<![CDATA[A 2.2-GHz Configurable Direct Digital Frequency Synthesizer Based on LUT and Rotation]]>665197019803586<![CDATA[Solar Cell Photo-Luminescence Modulation for Optical Frequency Identification Devices]]>$1.6times 10^{-3}$ at a rate of 10 kb/s and at a distance of 50 cm.]]>665198119923415<![CDATA[IEEE Transactions on Circuits and Systems-I: Regular Papers information for authors]]>66519931993111<![CDATA[IEEE Access]]>66519941994467<![CDATA[Introducing IEEE Collabratec]]>665199519952098<![CDATA[IEEE Foundation]]>66519961996202<![CDATA[IEEE Circuits and Systems Society Information]]>665C3C3137