<![CDATA[ IEEE Transactions on Power Electronics - new TOC ]]>
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TOC Alert for Publication# 63 2022January 17<![CDATA[Table of Contents]]>374C13684123<![CDATA[IEEE Power Electronics Society]]>374C2C231<![CDATA[An ESR Quasi-Online Identification Method for the Fractional-Order Capacitor of Forward Converters Based on Variational Mode Decomposition]]>374368536902687<![CDATA[Current Detection and Control of Synchronous Rectifier in High-Frequency <italic>LLC</italic> Resonant Converter]]>LLC converters. This letter presents a method to detect the SR current for cycle-by-cycle SR control. The resonant current and the magnetizing current are detected through magnetic coupling, and then the SR current is obtained by subtracting the two. This method requires only a few passive components and has advantages, such as high bandwidth, strong anti-interference ability, and easy implementation. This letter illustrates the working principle and implementation of the proposed method in detail and then verifies the proposed method through experiments. The proposed method can be applied to SR control in an LLC circuit, suitable for high frequency and large current situations.]]>374369136963213<![CDATA[Capacitor Condition Monitoring for the Low-Capacitance StatCom: An Online Approach]]>374369737011941<![CDATA[Suppressing the Maximum EMI Spectral Peak Through Asynchronous Carriers in the Three-Phase Inverter With the Periodic CFM]]>374370237073208<![CDATA[A Four-Phase Hybrid Step-Up/Down Converter With RMS Inductor Current Reduction and Delay-Based Zero-Current Detection]]>I_{L}). The delay-based ZCD determines the zero-current point of I_{L} with a five-bit binary signal to compensate for the propagation delay between the control and the output signals of the driver. The system is fabricated using 180-nm CMOS technology. The power density is 1.838 A/mm^{2}, and the peak efficiency is measured at 89.49% and 86.83% in the step-down and step-up mode, respectively, with a load current range of up to 2 A.]]>374370837122139<![CDATA[Coupled Inductor Based Bidirectional Resonant Converter With Sine Wave Modulation in Wide Voltage Range]]>374371337182811<![CDATA[Short-Circuit and Over-Current Fault Detection for SiC <sc>MOSFET</sc> Modules Based on Tunnel Magnetoresistance With Predictive Capabilities]]>mosfet modules based on tunnel magnetoresistance (TMR). The TMR sensor is integrated into an SiC mosfet module to noninvasively measure its current. The measured current is compared with a threshold to detect short-circuit and over-current faults. The TMR sensor is installed in a chosen location, where the TMR sensor gain is automatically doubled in the event of short-circuit fault. As a result, a short-circuit fault can be predicted, i.e., the fault is detected before the actual short-circuit current reaches the threshold. Besides, only one TMR sensor is required to detect both short-circuit and over-current faults for a half-bridge power module. According to the experimental results, the short-circuit fault is detected when the fault current reaches half of the fault threshold current. The experimental results indicate general superiority over desaturation technology and better performance in detection time, reaction time, and total protection time compared with Rogowski switch-current sensor-based technology.]]>374371937232319<![CDATA[Demonstration of Picosecond 4H-SiC Diode Avalanche Shaper With Voltage Rise Rate of 11.14 kV/ns and Peak Power Density of 62 MW/cm<inline-formula><tex-math notation="LaTeX">$^2$</tex-math></inline-formula>]]>${p^+/p^-/n^+}$ multilayer epitaxial structure is experimentally demonstrated and characterized. For fabrication of our 4H-SiC DAS, the multilayer epitaxial stacks have been designed in detail and grown using continuous multilayer epitaxial wafer growth. To excite the delayed avalanche breakdown (DAB) effect, the electric field profile in multilayer epitaxial stacks has been numerically simulated in detail to suppress the surface electric field crowding and premature breakdown during the overvoltage pulse applied. A 2.5-kV, 1-ns pulsed power generator is adopted to drive our fabricated SiC DAS, the output on a 50 $Omega$ load is 1860 V, 100 ps, lead a voltage rise rate of 11.14 kV/ns, and a peak power density of 62 MW/cm$^2$. Furthermore, the fabricated SiC DAS operates stably in multipulse mode at 1 MHz. To the best of our knowledge, this is the first experimental result reported for picosecond DAS based on the 4H-SiC. This article is significant for developing 4H-SiC-based ultrafast closing switches.]]>374372437271671<![CDATA[A Hybrid Model-Based Diagnosis Approach for Open-Switch Faults in PMSM Drives]]>374372837322143<![CDATA[Altitude Readiness of High-Voltage IGBTs Subjected to the Partial Discharge at Harsh Environmental Conditions for Hybrid Electric Aircraft Propulsion]]>374373337362306<![CDATA[Packaged <inline-formula><tex-math notation="LaTeX">$beta$</tex-math></inline-formula>-Ga<sub>2</sub>O<sub>3</sub> Trench MOS Schottky Diode With Nearly Ideal Junction Properties]]>$_2$O$_3$) has attracted great interest as a material for efficient power devices. Yet, experimental studies rather concentrate on the investigation of bare dies and lack the analysis of devices in industry-standard packages. Furthermore, while Ga$_2$O$_3$ trench MOS Schottky barrier diodes (SBDs) appear to be promising candidates, temperature-dependent measurements previously revealed inhomogeneous junctions. In this letter, a vertical $beta$-Ga$_2$O$_3$ trench MOS SBD is presented. The diode exhibits a homogeneous Schottky junction and nearly ideal thermionic current flow. This indicates better junction properties than previously observed for trench as well as non-trench Ga$_2$O$_3$ SBDs, with only a slight influence of interface states at high temperatures. As a next step toward application, the chip is successfully bonded in an industry-standard TO-247 package. The molded discrete is operational at low temperatures of −50 °C and up to high temperatures of 150 °C while exhibiting a lower increase in on-resistance with rising temperature than SiC Schottky diodes.]]>37437373742816<![CDATA[2.41 kV Vertical P-Nio/n-Ga<sub>2</sub>O<sub>3</sub> Heterojunction Diodes With a Record Baliga's Figure-of-Merit of 5.18 GW/cm<sup>2</sup>]]>β-Ga_{2}O_{3} heterojunction diodes (HJDs) with composite terminal structures, a p-NiO junction termination extension (JTE), and a small-angle beveled field plate (BFP) are demonstrated. By implementing a p-NiO JTE structure, the optimal breakdown voltage (V_{br}) of β-Ga_{2}O_{3} HJD increases from 955 to 1945 V, and the integration of the small-angle BFP further boosts the breakdown voltage up to 2410 V. An 80-nm thin p-NiO layer is adopted in the heterojunction to reduce the specific on-resistance (R_{on,sp}), while the composite terminal structures have little effect on R_{on,sp}, due to the super-large lateral spread resistance. The β-Ga_{2}O_{3} HJD with composite terminal structures achieves a low R_{on,sp} of 1.12 mΩ·cm^{2}, yielding the highest direct-current Baliga's figure-of-merit (FOM = V_{br}^{2}/R_{on,sp}) among all reported β-Ga_{2}O_{3} diodes with a value of 5.18 GW/cm^{2}_{,} which is about 15% of the theoretical value. These results suggest that the electrical field engineering with a composite terminal structure is a viable and effective technological strategy to enable the realization of β-Ga_{2}O_{3} bipolar power rectifiers.]]>374374337461263<![CDATA[Accurate Modeling of PLL With Frequency-Adaptive Prefilter: On the Positive Feedback Effect]]>374374737521379<![CDATA[Self-Powered Dual-Inductor MI-PSSHI-VDR Interface Circuit for Multi-PZTs Energy Harvesting]]>374375337623268<![CDATA[A Novel High Power Hybrid Rectifier With Low Cost and High Grid Current Quality for Improved Efficiency of Electrolytic Hydrogen Production]]>374376337683022<![CDATA[An Online Compensation Method of VSI Nonlinearity for Dual Three-Phase PMSM Drives Using Current Injection]]>dq subspace (the torque subspace) thanks to the multiple decoupling subspaces of dual three-phase PMSM. The experiments have been given to verify the validity of the proposed method.]]>374376937742179<![CDATA[Periodic Energy Control for Wireless Power Transfer System]]>374377537801327<![CDATA[Proper Pulsewidth Setting to Avoid Underestimated Switching Loss in HV-IGBT Characterization]]>on-state pulsewidth during the test needs to be set long enough to characterize the switching-off of devices correctly. IGBT modules made by the leading European, Japanese, and Chinese manufacturers with voltage ratings spanning 3.3, 4.5, and 6.5 kV are tested for validation and guidance purposes. Moreover, the mechanism and impact factors of this pulsewidth effect are also investigated.]]>374378137853312<![CDATA[Switching Transition Analysis and Optimization for Bidirectional <italic>CLLC</italic> Resonant DC Transformer]]>CLLC resonant converter operating at the resonant frequency is considered a promising candidate for DCX with a constant voltage transfer ratio. To solve unsmooth bidirectional power flow and current distortion in the traditional CLLC-DCX with synchronization rectification (SR) modulation, a dual-active-synchronization (DAS) modulation is adopted with identical driving signals on both sides. First, the switching transition of this modulation is fully analyzed with the consideration of large device output capacitances. After comparison of different transitions, a so-called “Sync-ZVS” transition is found more desirable with ZVS, no deadtime conduction loss, and almost load-independent voltage gain. In order to achieve this switching transition, an “Axis and Center Symmetric” (ACS) method is proposed. Based on this method, an overall design procedure of CLLC-DCX with DAS modulation is also proposed. Finally, the “Sync-ZVS” transition and the proposed “ACS” method are both verified by three 750-V/375-V or 750-V/750-V 18-kW 500-kHz prototypes with a 98.7% peak efficiency. This article is accompanied by one video demonstrating the load-changing test.]]>374378638006880<![CDATA[Passivity Enhancement for <italic>LCL</italic>-Filtered Inverter With Grid Current Control and Capacitor Current Active Damping]]>LCL-filtered inverter with grid current control and capacitor current active damping. It reveals that although an optimal damping gain can theoretically ensure the passivity, it is susceptible to both the lagging phase of the current regulator and the fluctuations of filter parameters. After thoroughly assessing the impacts of these two factors, proper phase compensations are proposed to enhance the passivity. It is found that a phase-lead or phase-lag compensator is needed, depending on the relation of the one-sixth of the sampling frequency to the resonance frequency of inverter-side inductor and filter capacitor. The guidelines on the compensation selection and parameter design are provided. Simulation and experimental results are conducted to verify the theoretical analysis.]]>374380138124828<![CDATA[Adaptive Virtual Resistance for Postfault Oscillation Damping in Grid-Forming Inverters]]>374381338244779<![CDATA[A Novel Synchronous Rectifier Driving Scheme for <italic>LLC</italic> Converter Based on Secondary Rectification Current Emulation]]>LLC SR driving scheme based on secondary rectification current emulation is proposed. An auxiliary winding of the transformer and an auxiliary winding of the resonant inductor located on the secondary side are in series to generate a superposed voltage signal. The secondary rectification current is emulated out according to the superposed voltage signal by an integration circuit. After that the SR driving signal, which is not affected by parasitic inductance, is generated with a logic circuit. Detailed theoretical analysis and circuit implementation have been presented. Finally, a 400 V input and 12 V/20 A output half-bridge LLC resonant converter prototype has been built up to verify the feasibility of the proposed SR driving scheme.]]>3743825383510249<![CDATA[Control and Modulation of a Single-Phase AC/DC Converter With Smooth Bidirectional Mode Switching and Symmetrical Decoupling Voltage Compensation]]>374383638538563<![CDATA[Differential Input Current Regulation in Parallel Output Connected Battery Power Modules]]>$N$ parallel output connected BPMs that operate in boost mode is presented. This article shows the effect of paralleling and differential currents on the individual input current regulation loops. Simulations and experiments verify the analysis. Experimental validation using a 300-W prototype consisting of three parallel output connected battery modules in an active BMS is presented.]]>374385438644156<![CDATA[Natural Boundary Transition and Inherent Dynamic Control of a Hybrid-Mode-Modulated Dual-Active-Bridge Converter]]>3743865387712014<![CDATA[Adaptive Fuzzy-Neural-Network Power Decoupling Strategy for Virtual Synchronous Generator in Micro-Grid]]>374387838914455<![CDATA[General Multi-Frequency Small-Signal Model for Resonant Converters]]>374389239123688<![CDATA[High-Performance Resonant Controller Implemented in the Discrete-Time Domain for Voltage Regulation of Grid-Forming Converters]]>374391339266976<![CDATA[Latest Advances of Model Predictive Control in Electrical Drives—Part I: Basic Concepts and Advanced Strategies]]>374392739422829<![CDATA[New Modulation Strategy for Five-Phase High-Frequency VSI Based on Sigma–Delta Modulators]]>$Sigma Delta$) modulators. This modulation strategy of five-phase large–medium-zero vectors $Sigma Delta$ (5P-LMZV-$Sigma Delta$) applies the same switching states as the two large and two medium space vector modulation (2L+2M SVM). Because $Sigma Delta$ modulations are designed to operate at high switching frequencies, using wide-bandgap devices, therefore, improves the efficiency of the VSI, despite its operating at these high switching frequencies. We analyze the use of single-loop and double-loop $Sigma Delta$ modulators (SL-5P-LMZV-$Sigma Delta$ and DL-5P-LMZV-$Sigma Delta$, respectively), and additionally modify the proposed modulation strategy to use all the vectors in order to analyze the effects from applying small vectors. The proposed modulation techniques allow minimizing switching losses due to the reduced switching operations, mitigating low-order harmonics, decreasing the amplitude of high-frequency harmonics, and reducing common-mode voltage dv/dt transitions. We analyze the performance of the proposed modulation technique using MATLAB/Simulink and PLECS, and then compare it with 2L+2M SVM. Using a VSI with silicon carbide mosfet, we obtained our experimental results demonstrating these characteristics, by which we conclude that our proposed strategy is an-
improvement over 2L+2M SVM.]]>374394339534515<![CDATA[Comparative Study of Symmetrical Controlled Grid-Connected Inverters]]>$alpha beta$ reference frame as single-input single-output systems. In addition, to reveal the similarity between different control methods and emphasize their differences, the admittance models are constructed by using the same framework. The admittance modeling is verified using frequency-scan, and the control performance is tested using MATLAB/Simulink Simscape Power System and experimental prototype. Finally, the stability criterion based on the proposed admittance modeling is verified by simulation results carried out in real-time simulation platform RTLAB from Opal-RT.]]>374395439689087<![CDATA[Minimization of Capacitor Voltage Difference for Four-Leg Inverter Dual-Parallel IM System]]>$pi$, which is first presented in this scheme. An angle regulator is proposed to control the electrical angle by adjusting stator flux amplitude. DVOE is realized by injecting a compensatory voltage vector, which is simplified in this scheme to avoid the voltage filter or additional coordinate transformation in the conventional method. Experiment results verify the effectiveness of the proposed scheme.]]>374396939793079<![CDATA[An Improved Impedance Modeling Method of Grid-Tied Inverters With White-Box Property]]>dq impedances strengthened. After that, dominated relationships between terms of GTI's impedance matrix and its internal physical parts are explicitly revealed to represent white-box property of the proposed impedance model. Specifically, the influence and effect mechanism of feedforward voltage compensation, current controller, phase lock loop, and power points (I_{d}, I_{q}) are emphasized based on the proposed impedance model. Finally, perturbations generated independent with PLL are injected into a hardware in-loop experiment platform, and impedance measurement results are provided to verify the conclusions drawn from the improved modeling method.]]>374398039894593<![CDATA[Review and Classification of MTPA Control Algorithms for Synchronous Motors]]>374399040072362<![CDATA[Online Efficiency Optimization of a Closed-Loop Controlled SiC-Based Bidirectional Boost Converter]]>off current. This results in the converter achieving zero-voltage switching quasi-square wave (ZVS-QSW) operation with minimum inductor current ripple. The optimal timing parameters are determined online by fit functions based on sensed input/output voltages and inductor current, and applied to the converter in a low-bandwidth feed-forward loop operating in conjunction with closed-loop regulation of the converter output voltage. The fit functions are developed from multivariate curve fitting of the analytical solutions of the minimum-conduction ZVS-QSW state plane over the complete range of operation. The proposed approach enables bidirectional operation with efficiencies greater than 97.5% for input voltages ranging from 200 to 400 V, step-up conversion ratios up to 2.5, and power levels between 2 and 8 kW. The converter also achieves efficiencies greater than 99% over wide power levels at boost conversion ratios lower than 2.]]>374400840215872<![CDATA[Control Design of a 99% Efficiency Transformerless EV Charger Providing Standardized Grid Services]]>LCL filter are analyzed and optimized for a better performance of grid interface. Grid service functions are designed for the EV charger to provide grid-voltage/frequency compensations. High power (22 kW) and high efficiency ($>$99%) are achieved with low-leakage current ($<$ 20 mA). The experiments are implemented to verify the proposed EV charger system.]]>374402240388931<![CDATA[Multiple Adaptive Current Feedback Technique for Small-Gain Stages in Adaptively Biased Low-Dropout Regulator]]>$mu$m process. The measured results show that the designed LDO realizes 30.75-mV transient performances with a step of 10 ns.]]>374403940496189<![CDATA[Improved Model Predictive Control for Three-Phase Dual-Active-Bridge Converters With a Hybrid Modulation]]>374405040647712<![CDATA[Neural Predictor-Based Low Switching Frequency FCS-MPC for MMC With Online Weighting Factors Tuning]]>374406540794697<![CDATA[Online-Parameter-Estimation-Based Control Strategy Combining MTPA and Flux-Weakening for Variable Flux Memory Machines]]>dq-axis inductances are estimated by employing the recursive least squares algorithm. In the proposed strategy, VFMM is controlled by using only two magnetization states (MSs), namely highest and lowest MSs, to avoid frequent MS manipulation. In the high-speed region of each MS, a continuous d-axis current is applied to stator windings to weaken the air-gap flux for further speed range extension by combining the feedforward and feedback FW approaches. The design procedure of the LADR-FFD current controller and the online estimation methods of the PM flux linkage and dq-axis inductances are first introduced. The proposed online-parameter-estimation-based control strategy is subsequently interpreted with the help of formulas and diagrams. The feasibility and effectiveness of the proposed control strategy are verified through experimental measurements on a hybrid magnetic circuit VFMM prototype.]]>374408040903530<![CDATA[A Double-PLLs-Based Impedance Reshaping Method for Extending Stability Range of Grid-Following Inverter Under Weak Grid]]>d–q small-signal impedance model is introduced to show the destabilizing factors. Then, an initial small-signal impedance reshaping method is proposed to counteract the major destabilizing factor caused by the PLL. Based on the initial impedance reshaping method, an improved control scheme is proposed. Through exhaustive mathematical analysis, it is proved that the dynamic power limit can be extended almost to the static power limit by using this proposed method. Finally, simulation and experimental results verify the effectiveness of the proposed method.]]>374409141048170<![CDATA[A Review of DC Shipboard Microgrids—Part II: Control Architectures, Stability Analysis, and Protection Schemes]]>374410541202895<![CDATA[A Periodic-Steady-State Analysis Model in Time Domain for Dual Active Bridge Converter]]>374412141323638<![CDATA[Evaluation of Ultrahigh-Voltage 4H-SiC Gate Turn-OFF Thyristors and Insulated-Gate Bipolar Transistors for High-Power Applications]]>off (GTO) thyristors designed for 20–50 kV blocking voltage capability. The simulated forward voltage drops of 20–50 kV device designs range between 3.1 and 5.6 V for P-i-N diodes, 4.2–10.0 V for IGBTs, and 3.4–7.8 V for GTO thyristors at 20 A/cm^{2} for room temperature operation. Moreover, with a low switching frequency application (i.e., 150 Hz) in mind, the switching energy losses using a 30 kV SiC GTO thyristor design are approximately E_{ON}/E_{OFF}__{GTO} = 268/640 mJ, E_{ON}/E_{OFF}__{FWD} = 388/6 mJ diode recovery losses, and E_{ON}/E_{OFF}__{SNUB} = 954/22 mJ snubber component losses. The corresponding values for an SiC IGBT design are E_{ON}/E_{OFF}__{IGBT} = 983/748 mJ, both operated at 448 K, τ_{A} = 20 μs, and with 30 A/cm^{2}. The simulation output is used in a benchmark evaluation for a 1 GW, 640 kV application case, employing modular multilevel high-power converter legs comprising series-connected UHV SiC devices and state-of-the-art -
.5 kV Si bi-mode insulated-gate transistors. It is concluded that the high-voltage SiC power electronic building blocks present promising alternatives to existing high-voltage Si device counterparts in terms of system compactness and efficiency.]]>3744133414710517<![CDATA[Robustness of Cascode GaN HEMTs in Unclamped Inductive Switching]]>mosfets can dissipate surge energy via avalanche, the GaN high-electron-mobility transistor (HEMT) has no avalanche capability and withstands surge energy by its overvoltage capability. However, a comprehensive study into the surge-energy robustness of the cascode GaN HEMT, a composite device made of a GaN HEMT and an Si mosfet, is still lacking. This article fills this gap by investigating the failure and degradation of 650-V-rated cascode GaN HEMTs in single-event and repetitive unclamped inductive switching (UIS) tests. The cascode was found to withstand surge energy by the overvoltage capability of the GaN HEMT, accompanied by avalanche in the Si mosfet. In single-event UIS tests, the cascode failed in the GaN HEMT at a peak overvoltage of 1.4–1.7 kV, which is statistically lower than the device's static breakdown voltage (1.8–2.2 kV). In repetitive UIS tests, the device failure boundary was found to be frequency dependent. At 100 kHz, the failure boundary (∼1.3 kV) is even lower than the single-event UIS boundary. After 1 million cycles of 1.25-kV UIS stresses, devices show large but recoverable parametric shifts. All these failure and degradation behaviors can be explained by the buffer trapping in the GaN HEMT and the resulted change in its dynamic breakdown voltage. Moreover, the GaN buffer trapping is believed to be assisted by the Si mosfet avalanche. An analytical model was also developed to extract the charges and losses produced in the Si avalanche in a UIS cycle. These results provide new insights into the surge-energy and overvoltage robustness of cascode GaN HEMTs.]]>374414841606672<![CDATA[A Highly Integrated PCB Embedded GaN Full-Bridge Module With Ultralow Parasitic Inductance]]>374416141738129<![CDATA[Improved Balance Technique for Common-Mode Noise Suppression of PCB-Based PFC]]>et al., 2018) has been demonstrated effectively to suppress CM noises for isolated converter with PCB-based transformer design. However, for nonisolated converters, such as power-factor correction circuits, none of the techniques mentioned above is deemed applicable or justifiable. Recently, the balance technique has been demonstrated effectively to suppress CM noises up to a point where the parasitic ringing between the inductor and its winding capacitor is observed (Wang et al., 2007), (Yang, 2018). This article presents an improved balance technique in a PCB-based coupled inductor design that compensates the detrimental effect of the interwinding capacitors. In the given example, CM noise suppression is effective in the frequency range of interest up to 30 MHz. A CM noise model is established to substantiate the measurement results.]]>374417441822903<![CDATA[Passive Capacitor Voltage Balancing of SiC-Based Three-Level Dual-Active-Bridge Converter Using Hybrid NPC-Flying Capacitor Structure]]>374418341948624<![CDATA[Line-Frequency-Isolation Flexible AC-Link Converter Based on Direct AC-AC Choppers]]>374419542106488<![CDATA[A Novel Dual Buck and Boost Transformer-Less Single-Phase Grid-Tied Inverter]]>mosfet switches at line frequency are adopted to be instead of the two individual capacitors of the conventional DBBI-SIDS. Different from the conventional DBBI-SIDS, the new inverter works in the pure full bridge mode. The detailed principle of operation is presented through equivalent circuits. The static characteristics and the control strategy of the proposed inverter will be also introduced in detail. A 110-V/50-Hz/550-W prototype has been developed in the laboratory, where experimental results have verified the desired performance of the proposed inverter.]]>374421142247020<![CDATA[Predictive Finite-State Control—When to Use and When Not]]>374422542321256<![CDATA[Medium Voltage Flying Capacitor DC–DC Converter With High-Frequency TCM-Q2L Control]]>on for a wide operating range, lowering power losses, and providing the possibility to operate at higher frequencies. The proposed novel control converges the advantages of these both methods leading to very high efficiency with high power density. Performance of the flying capacitor converter with the proposed control method is illustrated with a model-based Saber simulation at first, and then, an experimental model operating at wide frequency range (40 ÷ 250 kHz) and in medium voltage range was designed and constructed. A series of laboratory tests at up to 1.5 kV dc and 10 kW confirmed the noteworthy characteristics of the converter. The voltage between the power devices is balanced and the efficiency achieved reached as high as 99.1%. Therefore, the proposed converter can be competitively employed against classical two-level, as well as three-level and series connection-based counterparts.]]>374423342485829<![CDATA[An H5-Bridge-Based Laddered <inline-formula><tex-math notation="LaTeX">$CLLC$</tex-math></inline-formula> DCX With Variable DC Link for PEV Charging Applications]]>$CLLC$ converter. By configuring the switch pattern, the H5-bridge can form the modes of single half-bridge, dual half-bridge, half full-bridge, and dual full-bridge, respectively. Correspondingly, six gain curves can be derived. Combined with the variable dc-link framework, the converter constrains the switching frequency in the vicinity of the resonant frequency with optimal efficiency. The converter achieves an ultrawide battery voltage range with a squeezed dc-link span. A bidirectionally synchronous rectification method is proposed to improve the efficiency further. To verify the proposed concept, a 1-kW rated prototype with a 320–420 V dc link is built and tested. It validates the battery voltage 55–420 V for charging and 230–420 V for discharging. Zero-voltage turn-on and zero-current turn-off are achieved in the rectifying mosfets. The prototype exhibits 98.04% peak efficiency and good overall efficiency performance.]]>374424942607416<![CDATA[Advanced 2<italic>N</italic>+1 Submodule Unified PWM With Reduced DC-Link Current Ripple for Modular Multilevel Converters]]>N+1 submodule unified pulsewidth modulation (SUPWM) is attractive for modular multilevel converters (MMCs). To generate 2N+1 voltage levels, the SUPWM results in voltage pulses imposed on the arm inductors, which produces large high-frequency current ripple in the dc link of the MMC and deteriorates the dc-link performance. In this article, the dc-link high-frequency current ripple under 2N+1 SUPWM is analyzed and a reduced dc-link current ripple control method is proposed for advanced 2N+1 SUPWM. By regulating the phase angles of the three-phase carriers in each carrier period, the resulted voltage pulses on the arm inductors of three phases can be counteracted, and therefore the dc-link high-frequency current ripple is suppressed. With the proposed method, the MMC has much reduced dc-link current ripple, which effectively improves the performance of the MMC under 2N+1 SUPWM. Simulations and experiments are conducted to verify the validity and effectiveness of the proposed control.]]>374426142746592<![CDATA[Monopolar Symmetrical DC–DC Converter for All DC Offshore Wind Farms]]>374427542878898<![CDATA[Harmonic Optimization Strategy for CPS-PWM Based MMCs Under Submodule Capacitor Voltage Reduction Control]]>374428843006133<![CDATA[DC Impedance Modeling and Design-Oriented Harmonic Stability Analysis of MMC-PCCF-Based HVDC System]]>374430143196064<![CDATA[Analysis and Mitigation of DC Voltage Imbalance for Medium-Voltage Cascaded Three-Level Neutral-Point-Clamped Converters]]>374432043367097<![CDATA[Buck-Based Active-Clamp Circuit for Current-Fed Isolated DC–DC Converters]]>374433743453660<![CDATA[Single-Phase ZVS Quasi-Z-Source Inverter With High Voltage Gain]]>LC filter, adopting the unipolar SPWM control strategy with instantaneous feedback of output voltage and energy storage capacitor voltage. The impedance network is comprised of an energy storage inductor and two same diode–inductor–capacitor–capacitor cells; the ZVS auxiliary network includes a resonant inductor, a clamping capacitor, and an auxiliary switch, which provides the ZVS condition for power switches. The experimental results of a 1-kVA prototype verify that the proposed inverter features a high voltage gain, ZVS of all switches, high conversion efficiency, high output power quality, and strong load adaptability and has an important prospect in single-phase inversion with low input voltage or wide input voltage range.]]>374434643574539<![CDATA[A High Efficiency and High Power Density Integrated Two-Stage DC-DC Converter Based on Bipolar Symmetric Phase Shift Modulation Strategy]]>LLC isolated dc–dc converter is suitable for wide-voltage regulation range, high-frequency and high-efficiency application. However, the choke inductor current of buck-boost stage injecting into LLC stage will cause nonsinusoidal resonant current and asymmetric secondary current under the conventional modulation strategy. This will result in synchronous rectification problems. Traditionally, a large resonant inductor is utilized to improve the situation, but it sacrifices power density and efficiency. Therefore, this article proposes a bipolar symmetric phase shift modulation strategy to reduce the resonant inductance and correct resonant current with high power density and high efficiency. Moreover, LLC stage is improved. The RMS current of primary switches is decreased by the entrance of the choke inductor current. Zero-voltage-switching is achieved by choke inductor current instead of magnetizing current, so that the transformer can be designed without air gap and has lower winding loss caused by leakage flux. With minimum magnetizing current, the resonant current is minimized. The conduction loss of primary switches and winding loss of transformer shows 75% and 26% reduction, respectively. Finally, a 500 kHz 400-W prototype with 97.6% peak efficiency and 142W /in^{3} power density is built up. The experimental results verify that the proposed modulation strategy corrects resonant current effectively and improves efficiency and power density.]]>374435843737384<![CDATA[Sizing Equations for a Square Voltage Pulse Power Supply for Dielectric Barrier Discharges]]>374437443841862<![CDATA[SPICE-Based Circuit Analysis of Power Flow Coupling Effect in Double-Input Cuk--Buck DC–DC Converters]]>374438543964360<![CDATA[High-Bandwidth Combinational Rogowski Coil for SiC <sc>MOSFET</sc> Power Module]]>mosfet module power stage and it is shown that the switching transient current waveform is faithfully captured.]]>374439744054356<![CDATA[Crosstalk Suppression Method for GaN-Based Bridge Configuration Using Negative Voltage Self-Recovery Gate Drive]]>374440644188168<![CDATA[Multiple Sine-Wave Superposition Drive for the Doubly Salient Motor Based on Fourier Linearization Modeling]]>374441944306038<![CDATA[Online MTPA Operation of IPMSM Based on Dual-Loop Control in Polar Coordinates]]>374443144416027<![CDATA[Rotor Position Error Compensation in Sensorless Synchronous Reluctance Motor Drives]]>374444244526278<![CDATA[Space-Vector-Optimized Predictive Control for Dual Three-Phase PMSM With Quick Current Response]]>374445344623831<![CDATA[Estimated Position Error Suppression Using Novel PLL for IPMSM Sensorless Drives Based on Full-Order SMO]]>374446344745947<![CDATA[A Multilayer Perception Trained Method in Speed Control of a Linear Switched Reluctance Motor]]>374447544831933<![CDATA[An Adaptive Angle Error Compensator for IPMSMs With Periodic Loads in the Flux Weakening Region]]>374448444968610<![CDATA[Rotor Flux Estimator Design With Offset Extractor for Sensorless-Driven Induction Motors]]>374449745109667<![CDATA[Impedance Modeling of Three-Phase Grid-Connected Voltage Source Converters With Frequency-Locked-Loop-Based Synchronization Algorithms]]>374451145255645<![CDATA[A Novel Thyristor-Based Bidirectional SSCB With Controllable Current Breaking Capability]]>374452645343533<![CDATA[A <italic>DQ</italic>-Frame Asymmetrical Virtual Impedance Control for Enhancing Transient Stability of Grid-Forming Inverters]]>dq-frame asymmetrical virtual impedance control scheme for preventing grid-forming (GFM) inverters from the loss of synchronization with the grid under large disturbances. The approach exploits the two degrees of freedom in the dq-frame virtual impedance synthesis of GFM inverters, and introduces a virtual transient impedance (VTI) scheme to improve the power transmission capability and, thus, restoring equilibrium points of GFM inverters during the large disturbances. The transient stability of GFM inverters with the different kinds of virtual impedance setting is analyzed to formulate the design guideline of VTI method. Simulations and experimental tests are presented to validate the effectiveness of the approach.]]>374453545445995<![CDATA[Measurement-Based Identification of DC-Link Capacitance of Single-Phase Power Electronic Devices for Grey-Box Modeling]]>374454545522290<![CDATA[A Novel Converter-Level IGBT Junction Temperature Estimation Method Based on the Bus Voltage Ringing]]>on-state voltage-based IGBT junction temperature monitoring method. Besides, the proposed method reduces the circuit complexity, size, and cost, and it is easy to install. Moreover, the proposed method has a fast response and high resolution, and it does not disturb the normal operation. The proposed method is independent of bond wire degradation of the IGBT module.]]>374455345637234<![CDATA[Aging Condition Monitoring for Aluminum Electrolytic Capacitor in Variable Speed Drives]]>LCR network composed of a dc choke, an AEC, and a braking branch. The condition of the AEC is monitored through the capacitance value and the equivalent series resistor (ESR) value. The capacitance value and the ESR value are identified by the LCR network response, i.e., magnitude gain and phase shift of the network. The existing components of the VSD are fully utilized instead of adding additional current sensors and active devices. Some potential disturbances in field application, such as three-phase voltage unbalances, are also considered. Experiments are carried out in a 10-kW general-purpose VSD with different AECs. The maximum errors of capacitance value and ESR values identifications are 1.1% and 5.48%, respectively.]]>374456445742389<![CDATA[Data-Driven Fault Diagnosis of Lithium-Ion Battery Overdischarge in Electric Vehicles]]>374457545888584<![CDATA[Fault-Tolerant System Design for Doubly Salient Electromagnetic Machine Under Loss of Excitation]]>374458945995955<![CDATA[Submodule Open-Circuit Fault Detection For Modular Multilevel Converters Under Light Load Condition With Rearranged Bleeding Resistor Circuit]]>374460046138640<![CDATA[Temperature-Balancing Control for Modular Multilevel Converters Under Unbalanced Grid Voltages]]>374461446255820<![CDATA[A Novel Approach to Model and Analyze Uneven Temperature Distribution Among Multichip High-Power Modules and Corresponding Method to Respecify Device SOA]]>374462646407763<![CDATA[EMI Filter Robustness in Three-Level Active Neutral-Point-Clamped Inverter]]>374464146579995<![CDATA[Investigation and On-Board Detection of Gate-Open Failure in SiC MOSFETs]]>mosfets. First, the mosfet's behavior under various possible gate-open failure scenarios is analyzed in detail through simulations. Several SiC mosfets are aged on a dc power cycling setup and gate-open failure mechanism is verified through systematic multistep failure analysis, which includes on-board characterization, nondestructive C-SAM analysis, decapsulation, and optical inspection followed by scanning electron microscopy analysis of the failed devices. To understand the potential mechanism behind gate-open failure in SiC mosfets, thermo-mechanical finite element analysis analysis is performed on a high-fidelity model that shows interfacial shear stress at gate-bond. Furthermore, a robust on-board technique for reliable cycle-by-cycle detection of gate-open faults is proposed. The proposed technique is experimentally verified for all possible fault scenarios and shown to detect faults in as low as $text{150};text{ns}$. It is shown that compared to the traditional DESAT protection scheme, the proposed mechanism can prevent potential shoot-through events that may be caused by gate-open failure.]]>374465846717178<![CDATA[Analytical Method for <italic>RC</italic> Snubber Optimization Design to Eliminate Switching Oscillations of SiC MOSFET]]>mosfet seriously deteriorate its high-reliability applications. By viewing from the terminals of both SiC mosfet and diode for the turn-on and turn-off oscillation not only the two-port networks be formed to carry out more accurate analysis about the system characteristics but also the characteristic equations of the system can be deduced, thereby reliably guiding the RC snubber design. Since the oscillation is essentially caused by the imaginary part of poles, with the assistance of the two-port networks, an optimized design method of an RC snubber circuit is developed by the way of actively assigning poles. Different from existing analytical techniques, no necessity is needed to reduce the order of characteristic equations to yield the mathematical expressions of RC snubbers. Instead, RC snubber regions where oscillations can be completely suppressed are determined directly by an exhaustion method. An overlapping area is found, which means that both the turn-on and turn-off oscillation can be eliminated simultaneously by the same snubber circuit. Moreover, the related discussions about existence conditions of the snubber region, sensitivity to parameters, and the limitation in choosing RC are illustrated in detail. Finally, standard double-pulse tests are conducted on both the LTspice simulation and the laboratory experiment to verify the effectiveness of the analysis and proposed method.]]>374467246847159<![CDATA[Mitigation of Interturn Short-Circuits in IPMSM by Using MTPCC Control Adaptive to Fault Severity]]>$dq$ current plane, it is shown that for a specific fault severity and machine speed, the operating points with the same CC form a circle, and for constant torque with ITSC is a hyperbola. ITSC is a fast-developing fault that implies the fault severity continues to increase with time, and the positions of the CC circle and torque hyperbola change with the increasing fault severity in the $dq$ current plane. The MTPCC control updates the mitigation operating point automatically, depending on the positions of the CC circle and torque hyperbola with respect to the circle of the machine's maximum current, to produce the maximum possible torque as the fault severity changes, which shows that it is adaptive to the variation of fault severity. The proposed mitigation control is validated through experiments.]]>374468546965260<![CDATA[Passive and Online DC Bus Status Monitoring for Back-to-Back Converters Applied to Doubly Fed Induction Machines]]>$R_s$, inductance $L_s$, and capacitance $C$) used in doubly fed induction machines for wind applications. This kind of machines is widely adopted as generators for wind applications, where predictive maintenance is an important cost-reduction driver. Two implementations are described, plug-in or parallel, depending on whether the algorithm runs in the application digital control platform or as a standalone diagnostic device. Neither requires maintenance shutdown or dc current measurements to estimate bus parameters. In the plug-in operation, the proposed method relies only on the electrical quantities required by the control system, i.e., stator-side and rotor-side voltages and currents. Conversely, in parallel mode, dedicated external voltage and current sensors are used. In both cases, the series $RLC$ estimation is based on a recursive least squares algorithm that works for the full speed range of regular operation required in wind energy applications. In this way, the replacement of deteriorated capacitors can be performed by monitoring the estimated parameters. The validity of the proposal is discussed based on a theoretical analysis, simulation results, and experimental validations.]]>374469747074559<![CDATA[Unknown Input Observer-Based Series DC Arc Fault Detection in DC Microgrids]]>374470847184157<![CDATA[Analysis and Detection of Rotor Eccentricity in Permanent Magnet Synchronous Machines Based on Linear Hall Sensors]]>374471947294072<![CDATA[An Improved Hybrid DC Circuit Breaker With Self-Adaptive Fault Current Limiting Capability]]>374473047414565<![CDATA[Control of Distributed Photovoltaic Inverters for Frequency Support and System Recovery]]>374474247502151<![CDATA[A Current Limiting Method for Single-Loop Voltage-Magnitude Controlled Grid-Forming Converters During Symmetrical Faults]]>374475147636417<![CDATA[PV Panel to PV Panel Transfer Method for Modular Differential Power Processing]]>374476447783880<![CDATA[The Modular Current-Fed High-Frequency Isolated Matrix Converters for Wind Energy Conversion]]>374477947915786<![CDATA[Line Voltage Sensorless Control of Grid-Connected Inverters Using Multisampling]]>LCL-filtered inverters. In this article, a multisampling is performed on the inverter-side current, and the linear regression of the multisampled current during zero vectors of inverter-modulation voltage is employed to estimate the filter capacitor voltage. Consequently, the cost of line voltage sensors is reduced and the failure of line voltage sensors is prevented when using multisampling current control. Furthermore, to address start-up transients, the line voltage can still be estimated by temporarily locking the upper arms of the inverter, and dc-link voltage can be precharged to the target value at the same time. Experimental results validate the effectiveness of the method on a down-scale inverter.]]>374479248037132<![CDATA[A Switched-Capacitor-Based Six-Level Inverter]]>374480448166380<![CDATA[Research on Input-Parallel Single-Switch Wireless Power Transfer System With Constant-Current and Constant-Voltage Output]]>LC-resonant circuit is a combination of trapezoidal wave and half-sine wave; there is no relevant research on parallel connection of single-switch LC-resonant circuit. Therefore, this article presents a novel input-parallel single-switch LC-resonant circuit; this topology adopts switchable secondary networks for constant-current (CC) and constant-voltage (CV) output, and prevents shoot-through of power switches. The decoupling between transmitters simplifies the analysis and calculation. The input-parallel structure avoids the unbalanced input voltage of each inverter and improves the stability of the wireless power transfer system. CC and CV output modes can be achieved by controlling one relay without adding dc–dc converters or changing the switching frequency. This article includes decoupling equivalent analysis of coils, topologies analysis of CC mode and CV mode, calculation of equivalent input ac voltage source, design of magnetic coupler, and circuit parameters. Finally, a 1-kW experimental prototype is built to verify the theoretical analysis; the maximum efficiency can reach up to 92.5%.]]>374481748304332<![CDATA[Wireless Energy Trading in Traffic Internet]]>374483148418478<![CDATA[A 6.6-kW High-Frequency Wireless Power Transfer System for Electric Vehicle Charging Using Multilayer Nonuniform Self-Resonant Coil at MHz]]>2 power density. The system demonstrates the first 6.6-kW wireless power transfer system for EV charging using compact self-resonant coils at MHz.]]>374484248567734<![CDATA[Review Map of Comparative Designs for Wireless High-Power Transfer Systems in EV Applications: Maximum Efficiency, ZPA, and CC/CV Modes at Fixed Resonance Frequency Independent From Coupling Coefficient]]>-current/voltage supply to the load. Basic single- and double-resonance blocks based on LC-resonant circuits are analyzed. Then, resonant S- and T-blocks are recommended as the best transmission blocks for competitive designs. The proposed approach is applied to map recent developments on the wireless charging technologies for electric vehicles (EVs), especially for weak-coupling systems and dynamic-charging technologies. The proposed design approach offers a systematic and effective methodology to quickly evaluate current technologies and solutions for WHPTs in EVs applications. In extension, this article indicates different control strategies for WHPTs, especially for optimal-efficiency tracking. Design guidelines and control strategies are provided to achieve the maximum efficiency at a standard resonance frequency against variations from loads and coupling coefficients in operation which can easily map to recent research works and future research directions. Experimental verifications of dominant designs are also presented to validate the proposed approach. The map for comparative designs and control structures presented in this article aims to serve as a guideline and to ease the initial steps for other researchers in this area.]]>374485748767021<![CDATA[Systematic Design of a 100-W 6.78-MHz Wireless Charging Station Covering Multiple Devices and a Large Charging Area]]>$^2$ transmitter coil is demonstrated. The measured magnetic field variation on the charging surface is 15.9%. And the system shows no cross-channel disturbance when charging two 50-W receivers. The measured dc-to-dc efficiency is 92.8%.]]>374487748893760<![CDATA[Compensation Optimization of the Relay Coil in a Strong Coupled Coaxial Three-Coil Wireless Power Transfer System]]>374489049023449<![CDATA[Induced Voltage Estimation From Class EF Switching Harmonics in HF-IPT Systems]]>374490349163418<![CDATA[IEEE Power Electronics Society]]>374C3C334<![CDATA[Administrative Committee]]>374C4C427