<![CDATA[ IEEE Transactions on Power Electronics - new TOC ]]>
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TOC Alert for Publication# 63 2021June 17<![CDATA[Table of Contents]]>369C19692122<![CDATA[IEEE Power Electronics Society]]>369C2C230<![CDATA[Series-Resonator Buck Converter—Viability Demonstration]]>C_{s}. All switches turn on at zero voltage, and the low-side switches turn off at zero current. The resonant tank generates additional loss and increases the voltage stress of the low-side switches. A 2-MHz prototype with a peak efficiency of 98.5%, 48 V at the input and 7 V, 20 A at the output was built to demonstrate the viability of the topology.]]>369969396971409<![CDATA[An SMES-Based Current-Fed Transformerless Series Voltage Restorer for DC-Load Protection]]>369969897032560<![CDATA[Artificial Intelligence-Aided Minimum Reactive Power Control for the DAB Converter Based on Harmonic Analysis Method]]>369970497102768<![CDATA[Pulsewidth-Modulator-Based Transfer Function Measurement Method for Variable Frequency-Controlled Half- and Full-Bridge Converters]]>369971197161574<![CDATA[Impedance Strengthening and Weakening Networks for Power Converter Analysis and Design]]>369971797212704<![CDATA[Mission Profile Emulator for Individual Submodule in Modular Multilevel Converter With Nearest Level Control]]>369972297302984<![CDATA[An Active Voltage Balancing Method for Series Connection of SiC MOSFETs With Coupling Inductor]]>369973197361709<![CDATA[Voltage Oscillation Suppression for the High-Frequency Bus in Modular-Multiactive-Bridge Converter]]>dv/dt and parasitic elements, have been becoming a challenge in modern power electronics. Modular-multiactive-bridge (MMAB) converter, in which active bridge modules are linked with high-frequency transformers, is a typical power converter with a large number of switching semiconductor and magnetic devices. The mechanism of HFO in MMAB is studied by the analysis of the oscillation tank first. Then, from the perspective of the oscillation tank and the excitation source itself, two suppression strategies, including the passive voltage clamping method and active selected harmonic elimination general phase-shift modulation method, are proposed, respectively. Finally, the effectiveness of both methods is verified and compared by experimental results. The research results in this letter can be utilized in other topologies, such as dual active bridge, and may provide some inspiration to solve the similar HFO problem.]]>369973797422365<![CDATA[A Control Strategy for Dual-Input Neutral-Point-Clamped Inverter-Based Grid-Connected Photovoltaic System]]>369974397574192<![CDATA[A Dual-Vector Model Predictive Control Method With Minimum Current THD]]>369975897622431<![CDATA[A Double-Sided Bidirectional Power Module With Low Heat Concentration and Low Thermomechanical Stress]]>T_{jmax} and the maximum thermomechanical stress of the attachment between the IGBT-1 and the spacer by ∼9% and ∼35%, respectively. Furthermore, it was proved by the power cycling tests that the lifetime of the double-side BDS module using the bridge buffering spacer can be at least two times longer, i.e., more than 200 k cycles, than the one using the traditional brick buffering spacer under the same load and ∼21% longer under the same T_{jmax} and ΔT_{j}.]]>369976397662192<![CDATA[An Efficient and Reliable Solid-State Circuit Breaker Based on Mixture Device]]>off its thyristors without reverse voltage stress, which eliminates the severe reverse overvoltage problem in the fault-interrupting process, and hence further enhances the reliability of the breaker. Detailed operation principle and design guidelines of the MD-SSCB are discussed through mathematical modeling. The feasibility of the proposed breaker is validated by experimental results.]]>369976797712456<![CDATA[Fringing-Effect Losses in Inductors by Thermal Modeling and Thermographic Measurements]]>369977297869232<![CDATA[Series DC Arc Fault Detection Method for PV Systems Employing Differential Power Processing Structure]]>369978797955790<![CDATA[A Physics-Based Empirical Model of Dynamic <italic>I</italic><sub>OFF</sub> Under Switching Operation in <italic>p</italic>-GaN Gate Power HEMTs]]>off-state leakage current (I_{OFF}) under switching operation in p-GaN gate high-electron-mobility transistors is established based on its underlying physical mechanism. The impacts of relevant switching conditions, including switching frequency, duty cycle, off-state delay time, gate drive voltage, and temperature are all considered in the modeling of dynamic I_{OFF}. A good agreement between the modeled dynamic I_{OFF} and experimental results is achieved. Based on this model, the off-state power consumption (E_{OFF}) and off/on-state power consumption ratio (E_{OFF}/E_{ON}) under dynamic switching operation can be predicted for various switching conditions. As the device worked at a high switching frequency (e.g., 1 MHz and duty cycle: 50%) with a gate drive voltage of 7 V and temperatures from 25 to 150 °C, the E_{OFF}/E_{ON} ratio is calculated from 0.53% to 0.07%, which is three to two orders of magnitude higher than what is projected from static off-state current characteristics.]]>369979698055150<![CDATA[Thermal Performances and Annual Damages Comparison of MMC Using Reverse Conducting IGBT and Conventional IGBT Module]]>369980698256174<![CDATA[Accurate Online Junction Temperature Estimation of IGBT Using Inflection Point Based Updated I–V Characteristics]]>$T_j$) estimation of the insulated gate bipolar transistor (IGBT) is important for reliable operation of the power converters in various applications. For $T_j$ estimation, on-state collector-emitter voltage ($v_{ce}$) at higher collector currents ($i_c$) is widely used temperature sensitive electrical parameter (TSEP). For real-time $T_j$ estimation, this TSEP is calibrated using the I–V characteristics of the new IGBT. Due to bond-wire degradation, the original I–V characteristics of IGBT changes resulting in inaccurate $T_j$ estimation. In this article, a technique is proposed to update the I–V characteristics of the degraded IGBT, without affecting the normal operation of the power converter. It is achieved by estimating the increment in bond-wire resistance ($triangle R_{con}$) by using real-time samples of $v_{ce}$ and inductor current. The mathematical analysis is also presented to find an error in estimated $triangle R_{con}$. The major contributions of this article are as follows: a) it enables the accurate $T_j$ estimation of the IGBT throughout its lifetime; and b) it also provides the parameter $triangle R_{co-
}$, which could be utilized in condition monitoring of the IGBT. Further no additional circuitry is required. The proposed technique is validated on experimental setup, which is developed in the laboratory. The error in $T_j$ estimation is observed within $1$ °C the degraded IGBT, which shows the effectiveness of the proposed scheme.]]>369982698362468<![CDATA[Wireless Power Supply Design for Precharging Circuit of SST in Railway Vehicles]]>P_{L} = 30 and 12 W at d_{c} = 30 mm, respectively. As a result, the proposed control method without communication circuits between Tx and Rx sides has been successfully verified when coil distance and load resistance are widely varied.]]>369983798538213<![CDATA[An Inductive Coupler Array for In-Motion Wireless Charging of Electric Vehicles]]>N+1 switches are required to independently energize N primary IPT couplers. Any number of couplers can be activated simultaneously in the array without proportionally increasing the current stress on the switches. A state-space model is developed and implemented in PLECS to investigate the efficiency and power transferred to an EV traveling over the proposed PPCA while considering the variation in the coupling and the self-inductances of the couplers. A 3.3-kW scaled prototype PPCA consisting of three primary couplers and two secondary couplers has been implemented to validate the performance of the proposed configuration.]]>369985498635148<![CDATA[A 2.4-GHz CMOS Differential Class-DE Rectifier With Coupled Inductors]]>LC networks. We use a coupled inductor structure to reduce the cost overhead of the differential topology and discuss its design considerations. To maintain the ZVS/ZCS operation within a wide input power range, we employ an adaptive bias circuit to adjust the gate bias voltages with the input power. Additionally, we discuss the imperfections caused by load variation. The chip, fabricated in a 65-nm CMOS process, measures the peak power conversion efficiency (PCE) of 68.5% at a 9-dBm input power with a 250-Ω load resistance. The measured input power range when PCE > 40% is 16 dB.]]>369986498756314<![CDATA[Precise Modeling of Mutual Inductance for Planar Spiral Coils in Wireless Power Transfer and Its Application]]>369987698851534<![CDATA[Minimizing Current in Inductive Power Transfer Systems With an Asymmetrical Factor for Misalignment Tolerance and Wide Load Range]]>369988698966186<![CDATA[General Pathways to Higher Order Compensation Circuits for IPT Converters via Sensitivity Analysis]]>369989799061867<![CDATA[A Novel Analysis Method Based on Quadratic Eigenvalue Problem for Multirelay Magnetic Coupling Wireless Power Transfer]]>369990799174308<![CDATA[A 6.78-MHz Single-Stage Wireless Power Receiver With Ultrafast Transient Response Using Hysteretic Control and Multilevel Current-Wave Modulation]]>μm CMOS process using 3.3-V devices can regulate the output voltage to 3.3 V and deliver 1.98-W maximum power with a measured peak efficiency of 92.14%. An instant load-transient response is observed for a load current step between 12 and 600 mA.]]>369991899263692<![CDATA[Development of a Fit-to-Surface and Lightweight Magnetic Coupler for Autonomous Underwater Vehicle Wireless Charging Systems]]>369992799407741<![CDATA[A 50-kW Three-Channel Wireless Power Transfer System With Low Stray Magnetic Field]]>369994199545713<![CDATA[Highly Efficient 11.1-kW Wireless Power Transfer Utilizing Nanocrystalline Ribbon Cores]]>369995599696103<![CDATA[Steady-State Characterization of <italic>LLC</italic>-Based Single-Stage AC/DC Converter Based on Numerical Analysis]]>LLC-based single-stage ac/dc converter can achieve zero voltage switching under full load range, which offers a very attractive solution to realize high efficiency, low cost, and extreme compactness of ac/dc power conversion. However, with the introduction of LLC resonant tank in this ac/dc conversion, it becomes very challenging to accurately analyze the steady-state characterization of the converter due to its complex resonant circuit behaviors and time-varying ac input voltage. Although some analysis methods, like first-order harmonics approximation (FHA), extended FHA, and multiharmonic approximation, etc., can be adopted to analyze this converter, they cannot obtain the accurate gain curves, especially when the switching frequency deviates far from the resonant frequency. In this situation, the numerical analysis method is offered to cope with the difficulties resulting from time-varying ac input and dc output fluctuation. A set of equations describing resonant circuit behaviors, power conservation, inductor current, and capacitor voltage are presented. Also, the numerical analysis procedure is given in detail. The numerical calculation results are found that they match with those results in PSIM simulation pretty well. A 1-kW 48-V output prototype is built to verify the effectiveness of the numerical analysis.]]>369997099835432<![CDATA[Analysis and Optimization of Modulation Transitions in Medium-Voltage High-Power Converters]]>369998499936948<![CDATA[Hierarchical Modeling Scheme for High-Speed Electromagnetic Transient Simulations of Power Electronic Transformers]]>3699994100042360<![CDATA[An Investigation Into High-Voltage Spiral Generators Utilizing Thyristor Input Switches]]>36910005100198832<![CDATA[A Comprehensive Assessment of Multiwinding Transformer-Based DC–DC Converters]]>36910020100364681<![CDATA[Component-Level Reliability Assessment of a Direct-Drive PMSG Wind Power Converter Considering Two Terms of Thermal Cycles and the Parameter Sensitivity Analysis]]>10 and B_{1} lifetimes can easily be observed from the cumulative distribution functions. Moreover, different standard deviations are assumed for parameters in the Bayerer's lifetime model, and by using several parallel Monte Carlo algorithms, parameter sensitivity to the final lifetime evaluation is analyzed.]]>36910037100505423<![CDATA[A Highly Reliable Single-Phase AC to Three-Phase AC Converter With a Small Link Capacitor]]>36910051100647186<![CDATA[Interleaved Single-Stage <italic>LLC</italic> Converter Design Utilizing Half- and Full-Bridge Configurations for Wide Voltage Transfer Ratio Applications]]>LLC resonant converter of 3.6 kW for this purpose. While LLC converters are usually not suitable to cover such a wide voltage range (the input voltage between 240 and 420 V and the output voltage between 8 and 16 V), this LLC converter is operated in a full-bridge mode for large gains and in a half-bridge mode for low gains. For intermediate gains and loads, the LLC employs the phase-shift mode. To operate the interleaved LLCs at equal switching frequencies enabling output current ripple cancellation to reduce the output capacitor, again, the phase-shift mode is utilized to balance the power transfer during the full-bridge mode while the asymmetrical duty-cycle mode is proposed for power balancing during the half-bridge mode. This article analyzes the converter design for these modes of operation and provides a comprehensive design procedure allowing the designer to simultaneously analyze all stress values for various resonant tank designs. A 3.6-kW prototype employing Si superjunction MOSFETs achieves a power density of 2.1 kW/L. The maximum efficiency reaches 96.5%, while for most operating points, it is kept well above 90%. The experimental measurement results validate the analysis and show that phase-shift operation and asymmetrical duty-cycle mod-
lation can be utilized for power balancing for full-bridge and half-bridge configurations, respectively, such that a much smaller output capacitor can be employed.]]>36910065100806087<![CDATA[A Single-Stage Dual-Active-Bridge AC–DC Converter Employing Mode Transition Based on Real-Time Calculation]]>36910081100884574<![CDATA[A New Design of Z-Source Capacitors to Ensure SCR's Turn-Off for the Practical Applications of ZCBs in Realistic DC Network Protection]]>off function. In this article, a new specific method for calculating Z-source capacitances is developed based on the reverse-recovery characteristics of SCR, which was not considered in the prior-art solution properly. The proposed method can ensure the turn-off action of SCR in ZCB's practice for realistic dc network protection. At first, it is revealed that the problem in the prior-art solution of ZCB parameter identification, which does not handle the SCR's reverse recovery well, and thus, could result in a failure of tripping action. To solve the problem, the specific method is proposed to adjust the Z-source capacitances, in order to accumulate enough electrons for the postfault depletion region buildup in SCR, and thus, guarantee the SCR's turn-off for a successful dc circuit protection. In the specific derivation, the required tripping time of ZCB is also considered and can remain unaltered after Z-source capacitance adjustment. Finally, experimental tests have verified the problem solving by comparing the proposed to the prior-art solution and proven its accuracy. The proposed method can be added as a supplement to the prior-art solution for the practical design of ZCB. This research article helps to increase the technology readiness level of ZCB solution and practice in realistic dc network protection.]]>36910089100963119<![CDATA[Design Method of <italic>LCL</italic> Filter for Grid-Connected Inverter Based on Particle Swarm Optimization and Screening Method]]>LCL parameter design. Its efficiency is low and it is difficult to obtain the optimal parameter. Furthermore, due to the lack of detailed analysis of the high-frequency harmonics in the inverter output voltage, the designed LCL filter cannot effectively filter them, resulting that the quality of the grid-connected current cannot fully meet IEEE 519 standard. Based on the above-mentioned problems, the high-frequency harmonics of inverter output voltage is analyzed in detail in this article, and the multiobjective optimization function, including five optimization objectives, is constructed. Combined with the particle swarm optimization, a screening method is proposed to realize the multiobjective optimization process. Under the proposed method, the LCL parameter, which happens to meet the requirement of IEEE 519 for the high-frequency harmonic distortion rate of the grid-connected current, can be obtained, and the greatest tradeoff of LCL filtering performance and filter cost is achieved. In addition, the proposed method considers the problem of weak grid and provides a complete engineering solution for LCL parameter design in different degrees of weak grid. Finally, the effectiveness and accuracy of the proposed design method are verified by contrast simulation and experiment.]]>369100971011310587<![CDATA[Harmonic Virtual Impedance Design for Optimal Management of Power Quality in Microgrids]]>36910114101263187<![CDATA[A Single-Input Multiple-Output Unity Power Factor Rectifier]]>N-output (N-switch) rectifier is explained, and its general large-signal and small-signal models are developed. It is further illustrated using a single-input dual-output (SIDO) rectifier. Of the two dc outputs, one dc output voltage is higher, and one is lower than the peak voltage of the ac input. The small-signal model and the control scheme to enforce output voltage regulation and UPF operation are discussed. Experimental results are provided to validate the proposed topology and the control scheme.]]>36910127101418090<![CDATA[Enhanced Sizing Methodology for the Renewable Energy Sources and the Battery Storage System in a Nearly Zero Energy Building]]>36910142101562771<![CDATA[Design Methodology for Symmetric CLLC Resonant DC Transformer Considering Voltage Conversion Ratio, System Stability, and Efficiency]]>36910157101707582<![CDATA[Coordination Control Between Excitation and Hydraulic System During Mode Conversion of Variable Speed Pumped Storage Unit]]>369101711018511435<![CDATA[Vienna Rectifier-Fed Squirrel Cage Induction Generator Based Stand-Alone Wind Energy Conversion System]]>36910186101985738<![CDATA[Distributed Control of Islanded Series PV-Battery-Hybrid Systems With Low Communication Burden]]>PQ decoupling control is introduced, enabling the control of individual converters with only local measurements. Then, a droop controller is implemented in the battery converter, allowing the system to participate in regulating the islanded grid (voltage and frequency). A reactive power distribution method is subsequently introduced to equalize power sharing among the converters. Additionally, two anti-overmodulation loops are developed to address the overmodulation issue of both PV converters and the battery converter. With the proposed method, only a few variables with very slow dynamics should be transmitted, and the communication burden can be significantly reduced, leading to higher reliability to some extent. Experimental results have validated the effectiveness of the proposal.]]>36910199102139461<![CDATA[Analysis, Design, and Implementation of a Differential Power Processing DMPPT With Multiple Buck–Boost Choppers for Photovoltaic Module]]>36910214102233551<![CDATA[A Min–Max Closed-Loop PLL-GSPWM for Circulating Leakage Currents Attenuation in PV Station]]>36910224102385829<![CDATA[Panel-to-Substring Differential Power Processing Converter With Embedded Electrical Diagnosis Capability for Photovoltaic Panels Under Partial Shading]]>36910239102504066<![CDATA[Optimal Controller Design for Transient Stability Enhancement of Grid-Following Converters Under Weak-Grid Conditions]]>36910251102645077<![CDATA[Overvoltage Suppression Strategy for Sending AC Grid With High Penetration of Wind Power in the LCC-HVdc System Under Commutation Failure]]>36910265102774371<![CDATA[Broadband Impedance Shaping Control Scheme of MMC-Based STATCOM for Improving the Stability of the Wind Farm]]>36910278102928368<![CDATA[A Novel Generalized Common-Ground Switched-Capacitor Multilevel Inverter Suitable for Transformerless Grid-Connected Applications]]>36910293103066382<![CDATA[A New Current Source Converter Using AC-Type Flying-Capacitor Technique]]>36910307103167504<![CDATA[Switched-Capacitor-Based Multilevel Inverter for Grid-Connected Photovoltaic Application]]>36910317103299110<![CDATA[Interleaved LCLC Resonant Converter With Precise Current Balancing Over a Wide Input Voltage Range]]>36910330103427384<![CDATA[An Effective Integration of APM and OBC With Simultaneous Operation and Entire ZVS Range for Electric Vehicle]]>36910343103549474<![CDATA[Design of a Wide-Input-Voltage PCB-Embedded Transformer Based Active-Clamp Flyback Converter Considering Permeability Degradation]]>3) integrated ACF converter prototype based on GaN devices operating at 1 MHz is built and demonstrated for this purpose.]]>36910355103655241<![CDATA[A Single-Stage Isolated AC–DC Converter Based on the Impedance Control Network Architecture]]>rms), 20-V output, 330-W, 400-kHz ICN ac–dc converter prototype is built and tested. This prototype achieves a power density of 37.9 W/in^{3} and peak efficiencies of 91.7%, 92.2%, 93.2%, and 93.4% at 90, 120, 230, and 265 V_{rms} input, respectively.]]>36910366103827208<![CDATA[High-Efficiency High-Order <italic>CL-LLC</italic> DC/DC Converter With Wide Input Voltage Range]]>CL–LLC converter can realize soft switching in the full-load range. This article introduces the operating principle of the converter and the method of the parameters design. Finally, a 350–500 V input and 24 V/400-W prototype is designed to verify the correctness of the theory.]]>36910383103944769<![CDATA[A Modified Bi-Quad Filter Tuning Strategy for Mechanical Resonance Suppression in Industrial Servo Drive Systems]]>on is proposed to smooth the switching process. In the end, the validity and effectiveness of the proposed modification strategies are verified by experimental results.]]>36910395104087647<![CDATA[Modulation Technique for a <inline-formula><tex-math notation="LaTeX">$3 times 5$</tex-math></inline-formula> Matrix Converter Achieving a Maximum Input Reactive Power Range Based on Load Information]]>$3 times 5$ MC) to achieve a maximum input reactive power, whose superiority can be illustrated visually through a 2-D modulation graph. This article first derives the modulation matrix and its inherent constraints in the framework of duty-cycle calculation. After that, a constrained optimization problem for maximizing the reactive power is formulated; with the aforementioned constraints mapped to the 2-D modulation graph, the solution can be obtained without a substantial computational burden. The main contribution of this article is the adoption of a 2-D modulation graph to solve the constrained optimization problem for maximizing the input reactive power of a $3 times 5$ MC, which presents a new viewpoint by employing load information in modulation constraints. Finally, experiment results are presented for assessing the performance of the proposed modulation algorithm.]]>36910409104197187<![CDATA[Jet Impingement Cooling in Power Electronics for Electrified Automotive Transportation: Current Status and Future Trends]]>36910420104353056<![CDATA[A Novel Power and Signal Composite Modulation Approach to Powerline Data Communication for SRM in Distributed Power Grids]]>off angle of the SRM to produce voltage ripples on the power transmission line, whereas autoregressive power spectrum density method is innovatively utilized to demodulate useful data from the powerline. Hardware experimentation is conducted in this article, which verifies the effectiveness of the proposed PSCM method.]]>36910436104464673<![CDATA[Design Techniques of Sub-ns Level Shifters With Ultrahigh <italic>dV/dt</italic> Immunity for Various Wide-Bandgap Applications]]>dV/dt immunity is necessary for signal conversion among different voltage domain areas. This article presents design techniques for the sub-ns delay level shifter with ultrahigh dV/dt immunity. The propagation delay of the proposed floating level shifter is dramatically reduced by utilizing the edge detection technique. In order to further improve the performance, auxiliary pull-up circuit, promoting delay matching, and self-calibration techniques are adopted, which make the proposed level shifters more suitable for high-frequency wide-bandgap applications. The level shifter is fabricated in a 0.5 μm bipolar CMOS DMOS (BCD) process, whose results demonstrate the final level shifter achieves zero static power consumption, a 0.024 mm^{2} active area, and dV/dt immunity up to 250 V/ns. The measurement results show that the sub-ns delay level shifter can be realized, and the minimum delay is only 664 ps at VSSH 25 V. Its figure of merit is just 0.044 ns/(μm × V), which is optimal among previous level shifters. The level shifters are also simulated at the 0.18 μm BCD process, and the propagation delay can be decreased by more than 60%.]]>36910447104607301<![CDATA[MOSFET Gate Driver Circuit Design for High Repetitive (200 kHz) High Voltage (10 kV) Solid-State Pulsed-Power Modulator]]>us, maximum pulse repetition rate of 200 kHz, and average output power of 10 kW. The operation principle of the designed MOSFET gate driver is analyzed in detail. Experimental results show that the modulator operates stably at a high repetition rate of 10 kV and 200 kHz and the feasibility of this proposed circuit for high repetition rate operation are verified.]]>36910461104695053<![CDATA[A High-Precision and High-Efficiency PMSM Driver Based on Power Amplifiers and RTSPSs]]>36910470104807454<![CDATA[Dual-Gap Dual-Pole Composite Machine for Mechanical Rotor Position Estimation]]>36910481104895815<![CDATA[General Approach for Modeling and Control of Multiphase PMSM Drives]]>36910490105036297<![CDATA[The Mechanism for Suppressing High-Frequency Vibration of Multiphase Surface Permanent Magnet Motors via PWM Carrier Phase Shifting]]>36910504105135857<![CDATA[Model Predictive Control for PMSM Drives With Variable Dead-Zone Time]]>36910514105255108<![CDATA[Direct Flux Vector Control of Synchronous Motor Drives: A Small-Signal Model for Optimal Reference Generation]]>36910526105355407<![CDATA[Current Vector Angle Adaptive Adjustment Based Rotor Position Offset Error Suppression Method for Sensorless PMSM Drives]]>36910536105475812<![CDATA[Design and Optimization of a 200-kW Medium-Frequency Transformer for Medium-Voltage SiC PV Inverters]]>36910548105606806<![CDATA[Integrated Magnetics Design for a Three-Phase Differential-Mode Rectifier]]>36910561105706727<![CDATA[Single-Stage Converter Based on the Boost-PFC Rectifier Employing a Current-Source Charge-Pump for Power LEDs Applications]]>36910571105837690<![CDATA[Five-Degree-of-Freedom Modulation Scheme for Dual Active Bridge DC–DC Converter]]>36910584106018143<![CDATA[Extended Virtual Signal Injection Control for MTPA Operation of IPMSM Drives With Online Derivative Term Estimation]]>36910602106113227<![CDATA[A Dynamic-Segment-Alternating SVPWM for a Five-Level NNPP Converter With Neutral-Point Voltage Control]]>369106121062614743<![CDATA[EMI Mitigation of a Ćuk-Based Power-Electronic System Using Switching-Sequence-Based Control]]>mosfet under higher power with increasing switching frequencies, which is usually desirable for increased power density and reduced switching losses. Here, a hardware Ćuk–PES operated with GaN–FETs is fabricated and is used for case illustration. It is shown by experimental results how SBC mitigate DM and CM EMI noise-
of the PES while maintaining regulation even for the higher order nonminimum phase PES, while reducing sensor requirements using state observer derived from the switching model of the PES.]]>36910627106445537<![CDATA[Switching-Table-Based Direct Torque Control of Dual Three-Phase PMSMs With Closed-Loop Current Harmonics Compensation]]>36910645106595711<![CDATA[Current Limiting in Overload Conditions of an <italic>LLC</italic>-Converter-Based DC Transformer]]>LLC converter operated in open loop near resonant frequency have several crucial advantages compared to other topologies. These advantages are the stiff voltage ratio with a natural power flow, the dc grid isolation via medium-frequency transformer, and the high efficiency due to the resonant converter nature. Despite these advantages, the open-loop operation does not provide any options to limit the transferred current during overload conditions in the dc grid. This is critical, since it prevents the grid from recognizing that either some local primary regulation or load shedding is required. This article proposes a closed-loop control method that utilizes variable duty cycles to limit the current once the overload situation is detected. An applicable control scheme is derived and implemented. Since the duty-cycle modulation increases the losses of the converter, an online thermal model is implemented to protect the dc transformer during the overload conditions. The proposed current-limiting mode with the thermal model are validated using an exemplary low-voltage dc transformer prototype, demonstrating the general feasibility and overall good performance.]]>36910660106722959<![CDATA[A New Dead Time Regulation Synchronous Rectification Control Method for High Efficiency <italic>LLC</italic> Resonant Converters]]>LLC resonant converter applications, a synchronous rectification (SR) is essential component for high efficiency and high power density. However, stray inductances in MOSFET package and printed circuit board (PCB) pattern make premature turn-off of SR gate and large SR dead time. To compensate the stray inductance effect and increase system efficiency, a hysteresis band dead time regulation control method is proposed. In the proposed control method, SR dead time is regulated to predetermined dead time target regardless of the stray inductances by using a mixed signal, which includes instantaneous drain voltage information and previous cycle dead time information. As a result, the proposed control method can provide lower conduction losses by the dead time regulation and better transient characteristic by the instantaneous drain voltage information. To verify the validity of the proposed control method, 234-W prototype is built and experimented with the proposed controller, which is implemented with 0.25-μm BCDMOS technology.]]>36910673106835429<![CDATA[Inverter Nonlinearity Compensation Through Deadtime Effect Estimation]]>36910684106945567<![CDATA[Current-Based Open-Circuit Fault Diagnosis for PMSM Drives With Model Predictive Control]]>αβ-current average values and phase angles of residual current vectors are utilized to locate the exact faulty switch in each fault type. Consequently, a total of 21 possible combinations of faulty switches can be correctly detected and located. Finally, the effectiveness in fault diagnoses and the robustness against operating point variations are verified by the experimental results.]]>36910695107043941<![CDATA[Improved Model Predictive Control With New Cost Function for Hybrid-Inverter Open-Winding PMSM System Based on Energy Storage Model]]>36910705107154504<![CDATA[Margin Balancing Control Design of Three-Phase Grid-Tied PV Inverters for Stability Improvement]]>36910716107282956<![CDATA[An Asymmetric Control Method for Switched-Capacitor-Based Resonant Converters]]>36910729107412573<![CDATA[A Robust Deadbeat Predictive Controller With Delay Compensation Based on Composite Sliding-Mode Observer for PMSMs]]>36910742107524974<![CDATA[A Generalized Selective Harmonic Elimination PWM Formulation With Common-Mode Voltage Reduction Ability for Multilevel Converters]]>m_{a}) range and with an optimal third-harmonic injection in high m_{a} range. With the proposed formulation, the amplitude of CMV can be effectively reduced for all types of MLCs over the whole m_{a} range. Besides, two kinds of solving algorithms, i.e., off-line and real-time based, are introduced to provide efficient solution tools targeted at the proposed model. In this article, a case study with three-level neutral-point clamped inverters is discussed in detail to better illustrate the proposed formulation and the coupling effects between the CMV reduction and capacitor voltage balancing objectives of MLCs. Simulation and experimental results based on multiple MLC topologies are carried out to validate the effectiveness of this generalized SHE-PWM formulation with reduced CMV values.]]>36910753107657535<![CDATA[An Overview of Saturable Inductors: Applications to Power Supplies]]>3691076610775577<![CDATA[A Novel On-Board Electrochemical Impedance Spectroscopy System for Real-Time Battery Impedance Estimation]]>36910776107872123<![CDATA[Enhancing Inductive Operation of Low-Capacitance Cascaded H-Bridge StatComs Using Optimal Third-Harmonic Circulating Current]]>36910788108004610<![CDATA[Backstepping Control of High-Frequency Link Matrix Rectifier for Battery Chargers]]>369108011081421239<![CDATA[Analysis of Instability in Torque Control of Sensorless PMSM Drives in Flux Weakening Region]]>36910815108265979<![CDATA[An Improved Quadrangle Control Method for Four-Switch Buck-Boost Converter With Reduced Loss and Decoupling Strategy]]>36910827108417036<![CDATA[Three-Phase Phase-Locked Loop Algorithms Based on Sliding Modes]]>36910842108514906<![CDATA[Novel IPOx Architecture for High-Voltage Microsecond Pulse Power Supply Using Energy Efficiency and Stability Model Design Method]]>36910852108655552<![CDATA[Modulation for Cascaded Multilevel Converters in PV Applications With High Input Power Imbalance]]>36910866108783987<![CDATA[A New Virtual Oscillator Control Without Third-Harmonics Injection For DC/AC Inverter]]>36910879108883010<![CDATA[Split Parallel Semibridge Switching Cells for Full-Power-Range Efficiency Improvement]]>off. Accordingly, the switching loss and the reverse-recovery loss can be significantly reduced. The operating principle of the proposed paralleling scheme is characterized by two complementary operation modes: desynchronized mode with soft-switching (lower switching loss) and synchronized mode with lower conduction loss. Compared with conventional soft-switching schemes, this solution features zero auxiliary switches, constant switching frequency, and improved full-power-range efficiency enabled by the dual operation modes. Furthermore, design guidelines of the PCI are presented where a novel winding arrangement is proposed and verified to obtain a controllable DM inductance. The operation principles and advantages of the proposed paralleling structure are comprehensively validated on both buck and boost dc–dc converters with Si/SiC power MOSFETs and diodes.]]>36910889109055261<![CDATA[Motor Speed Control With Convex Optimization-Based Position Estimation in the Current Loop]]>369109061091911517<![CDATA[Accurate and Stable Hardware-in-the-Loop (HIL) Real-Time Simulation of Integrated Power Electronics and Power Systems]]>36910920109323115<![CDATA[An Optimized Digital Synchronous Rectification Scheme Based on Time-Domain Model of Resonant CLLC Circuit]]>36910933109486536<![CDATA[IEEE Power Electronics Society]]>369C3C334<![CDATA[Administrative Committee]]>369C4C426