<![CDATA[ IEEE Transactions on Power Electronics - new TOC ]]>
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TOC Alert for Publication# 63 2021September16<![CDATA[Table of Contents]]>3612C113348120<![CDATA[IEEE Power Electronics Society]]>3612C2C231<![CDATA[A Novel Thin Film Cascade Matrix Coupled Inductor for Integrated Voltage Regulators]]>2 floor area and provides 19.5 nH phase inductance with 120 mΩ dc resistance. The saturation current for each phase is up to 0.4 A when the phase inductance drops by approximately 20%. The coupling coefficient between any two phases of the proposed CMC inductor is 0.27, much higher and more controllable than that of toroid core-based coupled inductors.]]>361213349133541644<![CDATA[A Concept for Detection of Humidity-Driven Degradation of IGBT Modules]]>36121335513359819<![CDATA[An Integration Method of Resonant Switched-Capacitor Converters Based on Parasitic Inductance]]>361213360133641777<![CDATA[A Second Look on Nonfrequency-Dependent Transport Delay-Based PLL: Performance Enhancement Under Frequency Deviations]]>361213365133711605<![CDATA[A Fully Resilient Cyber-Secure Synchronization Strategy for AC Microgrids]]>361213372133781418<![CDATA[A Digital Signal Processing Based Detection Circuit for Short-Circuit Protection of SiC MOSFET]]>MOSFETs). The proposed SCD circuit incorporates a digital circuit for processing the voltage induced at the parasitic inductance of the source of SiC MOSFET to obtain an improved stable turn-off operation of the SiC MOSFET under SC condition. Compared with that of the conventional analog signal processing based SCD circuits, the proposed circuit has the advantages of having a turn-off operation which is robust to process, voltage, and temperature variations, being fully integrated without the use of external components and ease of design. The proposed circuit was implemented in a 350-nm Bipolar-CMOS-DMOS process. For functional verification, an SC test board integrating the proposed SCD circuit was developed. Experimental result validates that the proposed SCD circuit effectively functions under SC condition.]]>361213379133821561<![CDATA[Common-Source Inductance Induced Voltage Overshoot and Oscillation in Active Bidirectional Devices]]>on phenomenon during the device turn-off transient in a simple buck converter. Yet there is lack of literature investigating the impact of CSI in circuits using bidirectional devices. This letter aims to first demonstrate and then reveal the mechanism of a unique turn-off voltage overshoot and oscillation phenomenon in converters using active bidirectional devices. The issue is found to be associated with the CSI in the bidirectional devices and can result in more than 100% voltage overshoot and significantly higher switching loss during the turn-off transient. Practical solutions are also provided to attenuate or eliminate the detrimental effects. The phenomenon and provided analysis are demonstrated and verified on a custom-built SiC-based matrix converter phase-leg.]]>361213383133883274<![CDATA[Enabling Resonant Commutated Pole in Parallel Power FET Bridge Legs]]>on prior to the remaining main legs. A resonant commutated pole (RCP) mode is then created, which enables the high-side FET of the auxiliary leg to achieve zero-current switching (ZCS) or quasi-ZCS and the remaining FETs to achieve zero-voltage switching. Thus, we can significantly reduce the switching loss that normally dominates the total power loss of high-frequency hard-switching converters particularly at partial and light loads. Experimental results from three parallel GaN high-electron-mobility transistor legs validate the effectiveness of this RCP-enabled solution in reducing switching losses and improving power conversion efficiencies. This article is accompanied by supplementary JIF and PDF files demonstrating the operational details of the RCP mode.]]>361213389134036399<![CDATA[Modified VIENNA Rectifier III to Achieve ZVS in All Transitions: Analysis, Design, and Validation]]>$_I$ (total harmonic distortion) and 0.9996 PF (power factor) at nominal power, ultimately showing very good agreement to the simulation results. This article is accompanied by a video demonstrating experimental operation of the proposed rectifier at nominal input voltage, output voltage, and output power.]]>361213404134227798<![CDATA[High-Frequency Voltage Injection-Based Fault Detection of a Rotating Rectifier for a Wound-Rotor Synchronous Starter/Generator in the Stationary State]]>361213423134333778<![CDATA[A Fault-Tolerant SoC Estimation Method for Series–Parallel Connected Li-Ion Battery Pack]]>3612134341344810687<![CDATA[Fast Reliability Assessment of Neutral-Point-Clamped Topologies Through Markov Models]]>361213449134594803<![CDATA[A Voltage Vector Residual Estimation Method Based on Current Path Tracking for T-Type Inverter Open-Circuit Fault Diagnosis]]>3612134601347712701<![CDATA[A Transferrable Data-Driven Method for IGBT Open-Circuit Fault Diagnosis in Three-Phase Inverters]]>361213478134885639<![CDATA[Online Health Monitoring of DC-Link Capacitors in Modular Multilevel Converters for FACTS and HVDC Applications]]>361213489135036163<![CDATA[Efficient Hybrid-Modulated Single-Stage Wireless Power Receiver With Continuous DC Current]]>on of switches and zero-current switching turn-off of diodes for mitigating switching loss, while the PWM modulation performs good regulation of the output voltage of the rectifier. Experimental results of our constructed 100-kHz, 12-V output voltage, 35-W output power prototype show a fairly constant dc output current with 71% current ripple reduction as compared with that of a regular single-phase buck converter, good output regulation with less than 1% regulation error, and efficient ac–dc conversion with a peak efficiency of 96%.]]>361213504135144849<![CDATA[Triple-Coil-Structure-Based Coil Positioning System for Wireless EV Charger]]>Q_{M}). Thereafter, an RSS fingerprint positioning algorithm is proposed for obtaining coordinates in x-, y-, and z-direction. Specific considerations are also given for designing the exciting frequency and the coil parameters. Finally, the proposed positioning system is tested on a 3.3-kW wireless charger. The RSS of the proposed positioning system has been proved to be 3.2 times as that of the state-of-the-art one, whereas the excitation current is reduced by more than half. A number of positioning cases, with the targeted coil placed in an area of 32 cm × 32 cm, are tested in the lab. The experimental results show that more than 95% of these test cases have been well positioned with test errors less than 1.5 cm.]]>361213515135256188<![CDATA[Interleaved Capacitive Coupler for Wireless Power Transfer]]>361213526135354709<![CDATA[Wireless Shaded-Pole Induction Motor With Half-Bridge Inverter and Dual-Frequency Resonant Network]]>361213536135453697<![CDATA[Design of High-Efficiency Inductive Charging System With Load-Independent Output Voltage and Current Tolerant of Varying Coupling Condition]]>361213546135617392<![CDATA[Constant Current/Voltage Charging for Primary-Side Controlled Wireless Charging System Without Using Dual-Side Communication]]>3612135621357714282<![CDATA[PWM-Controlled Series Resonant Converter for Universal Electric Vehicle Charger]]>361213578135883876<![CDATA[Variable Output Voltage Switching Rectifier for Cathodic Protection Applications With DC–DC Variable Frequency and Duty-Cycle Full-Bridge Converter]]>361213589136024208<![CDATA[An Input-Series Output-Parallel Modular Three-Phase AC–AC Capacitive-Link Power Converter]]>361213603136205576<![CDATA[Multi Open-/Short-Circuit Fault-Tolerance Using Modified SVM Technique for Three-Level HANPC Converters]]>361213621136336935<![CDATA[Improved Auxiliary Triggering Topology for High-Power Nanosecond Pulse Generators Based on Avalanche Transistors]]>M × N-stage Marx bank circuits (MBCs). However, as the number of modified stages increases, the output voltage drops significantly, which makes it not achievable to adopt ATT at each stage. The transistors in nonmodified stages still have a certain failure rate when operating at a high repetition rate. Moreover, the previous ATT is only applicable in the negative polarity MBC. In this article, an improved ATT is proposed to solve the above problems. First, its operating principle is analyzed, and the feasibility of its application in both negative and positive MBCs is verified by simulations. Then, the effects of the improved ATT on M × N-stage MBCs are experimentally studied, and the results show that the improved ATT can be used in all stages of MBC without reducing the output voltage. It can also reduce the minimum operating voltage of transistors and widen the regulating range of output voltage. In addition, it can improve the synchronous conduction of parallel-connected transistors. Finally, two nanosecond pulse generators with positive and negative polarity, respectively, are developed and used to drive the atmospheric pressure plasma jet. The amplitude of output voltage can be adjusted in the range of 5–10 kV, measuring at the open end of a coaxial cable with 75 Ω impedance, and the maximum repetition rate is up to 7 kHz.]]>361213634136445616<![CDATA[Optimization Scheme Based on High-Frequency Link Interconnection of Submodules]]>361213645136596318<![CDATA[1200 V/650 V/160 A SiC+Si IGBT 3L Hybrid T-Type NPC Power Module With Enhanced EMI Shielding]]>v/dt and di/dt) generate electromagnetic interference (EMI) noise, requiring a larger and complicated filter stage design. To solve this problem, an optimized 3L T-type neutral point clamped power module has been proposed with a hybrid combination of the switch (SiC mosfet + Si IGBT) rated for 1200 V/160 A. Two direct bonded copper (DBC) substrates have been stacked to have a vertical power loop using laser-drilled vias, which provides low commutation loop inductance as low as 4.6 nH for the major CCLs including the wire bond. Other associated CCLs have also been identified and optimized. Additional DBC in the package will be acting as an EMI shield. The EMI noise has been compared to a traditional power module and a 21 dB reduction of common-mode noise has been observed.]]>361213660136739165<![CDATA[Variable Switching Frequency PWM for Three-Phase Four-Wire Split-Capacitor Inverter Performance Enhancement]]>361213674136855660<![CDATA[Flexible Nearest Level Modulation for Modular Multilevel Converter]]>361213686136966982<![CDATA[Effects of Noncharacteristic Harmonics on AC Losses of High-Temperature Superconducting Coils]]>361213697137052300<![CDATA[Model-Based Voltage Quality Analysis and Optimization in Post-Fault Reconfigured N-Level NPC Inverter]]>361213706137153331<![CDATA[Mirror-Bridge Phase-Shift Modulation With Low Common-Mode Noise for Single-Phase CHB PFC]]>361213716137253576<![CDATA[HVDC Circuit Breakers: A Comprehensive Review]]>36121372613739549<![CDATA[A Novel Dual-Mode Switched-Capacitor Five-Level Inverter With Common-Ground Transformerless Concept]]>361213740137536405<![CDATA[Leakage Current Suppression in Multilevel Cascaded H-Bridge Based Photovoltaic Inverters]]>361213754137627661<![CDATA[Ultrawide Voltage Gain Range Microconverter for Integration of Silicon and Thin-Film Photovoltaic Modules in DC Microgrids]]>361213763137788184<![CDATA[A Universal ZVT Design for a Family of Multiphase Interleaved High Step-Up Converters With Minimized Voltage Stress and Wide Operating Range]]>on and turn-off for the main switches and zero-current switching (ZCS) turn-off for all the diodes. Besides, the auxiliary switches turn on under ZCS. All the SS is accomplished within a wide duty cycle and power rating. From the comprehensive comparison, the constructed converters’ performance exceeds that of ZVS converters published in the recent literature. Furthermore, the extendable high voltage gain, low input current ripple, low voltage stress, and simple parameter design characteristics of HS MIBD converters are also conserved. Finally, a 320-W laboratory prototype is implemented to validate the theoretical analysis.]]>361213779137917654<![CDATA[An Effective Islanding Detection Method With Wavelet-Based Nuisance Tripping Suppressing]]>361213792138012749<![CDATA[An Improved ZVS High Step-Up Converter Based On Coupled Inductor and Built-In Transformer]]>361213802138165909<![CDATA[Voltage Track Optimizer Based Maximum Power Point Tracker Under Challenging Partially Shaded Photovoltaic Systems]]>P–V and I–V curves. Furthermore, the initial operating voltage is exploited to accelerate the tracking speed. By doing so, the voltage track length is drastically reduced, which results in reducing the tracking time. The performance of the proposed method is evaluated against two recent GMPPT methods, namely improved team game optimization and modified maximum power trapezium through MATLAB/Simulink environment. Besides, the simulation results are verified experimentally via a buck-boost converter. The obtained results prove the superiority of the proposed algorithm against the compared algorithms in terms of voltage track length, tracking speed, and transient energy losses.]]>361213817138253730<![CDATA[Self-Tuning MPPT Scheme Based on Reinforcement Learning and Beta Parameter in Photovoltaic Power Systems]]>$beta$ is introduced to constrain the exploration space. Simulation and experimental test are applied to validate the superior performance of the proposed solution following the EN50530 dynamic test procedure.]]>361213826138389586<![CDATA[Averaged Modeling and SRF-Based Closed-Loop Control of Single-Phase ANPC Inverter]]>$dq$-based controller is developed and implemented in a digital signal processor. In addition, the strength of the model is demonstrated by comparing the simulation waveforms and computational times required for simulating an ANPCI-based solar PV system using switching circuit model and the proposed averaged model.]]>361213839138546991<![CDATA[A Two-Phase Three-Level Buck Converter With Cross-Connected Flying Capacitors for Inductor Current Balancing]]>FLY). The proposed converter suppresses the unbalanced inductor currents in a two-phase operation, through the alternate connection of flying capacitors across the branches. Meanwhile, two-phase and three-level techniques help to achieve a fast transient response and a small output ripple. In addition, we derive the transfer function of the proposed generalized multiphase three-level buck converter with interconnected C_{FLY} for analysis, and design accordingly its power stage and feedback loop. Finally, we validate the proposed converter through the fabrication in a 65 nm CMOS GP process. It achieves a low unbalanced current close to 5 mA and a small output ripple of 50 mV for a load current around 110 mA, and a peak efficiency of about 86%.]]>361213855138668092<![CDATA[Single-Input Relay Charging Switched-Capacitor Topology for High-Bandwidth Envelope Tracking Power Supply]]>n (n ∊ N), significantly promoting the high-bandwidth tracking capability. However, multiple isolated voltage sources are required, leading to increased system complexity. Based on the PEID method, this article proposes a switched-capacitor ET power supply, which employs supplementary switches to flexibly link all the switched capacitors so that more charging loops are created and the relay charging mechanism is formed, which can equivalently extend the charging time and achieve more balanced voltage levels between the switched capacitors. Thus, with only one input, all the switched capacitors can maintain a stable and equal voltage and, thus, competently serve as the isolated voltage sources. To verify the proposed configuration and control method, a prototype with 2–27 V output voltage range, 54 W peak output power, and 10 MHz tracking bandwidth has been built and tested. The experimental results validate the proposed scheme.]]>361213867138774346<![CDATA[A 10 MHz DC/DC Converter With Zero-Phase Difference Synchronous Driving Signal]]>361213878138885036<![CDATA[Synthesis of DC–DC Converters From Voltage Conversion Ratio and Prescribed Requirements]]>3612138891390212623<![CDATA[A Voltage-Fed Soft-Switched Push–Pull Topology With Phase-Shifted Power Transfer Using Coupled LC Snubber]]>LC regenerative snubber-based energy recovery circuit reclaims the trapped energy in the leakage inductance. The snubber circuit also ensures soft-switched operation and reduces the voltage stress across the semiconductor switches. The power-flow equation is characterized and experimentally verified for the proposed converter. The gate control signals are implemented using an field-programmable gate array (FPGA). A 240-W prototype validates the steady-state behavior and snubber design equations.]]>361213903139168152<![CDATA[Dynamic Response of Buck Converter With Auxiliary Current Control: Analysis and Design of Practical Implementation]]>361213917139298228<![CDATA[Three-Phase Modular Multilevel Converter With Optimized Capacitor Sizing for Low-Voltage Applications]]>361213930139434470<![CDATA[Switching-Cell Buck–Boost AC–AC Converter With Common-Ground and Noninverting/Inverting Operations]]>RC snubbers or soft-commutation strategies, removing the need for pulsewidth modulation deadtimes. External fast recovery diodes are utilized, avoiding the high-frequency conduction of MOSFET's body diodes and eliminating their slow reverse recovery problem and corresponding power loss. The proposed converter shares a common ground between input and output ports, offers support for reactive loads, draws continuous sinusoidal current from ac mains, and delivers a continuous output current. The converter is suitable for ac voltage regulation applications, notably as a dynamic voltage restorer, compensating extensive magnitudes of both grid voltage sags and swells. Circuit operation and analysis are provided for all the proposed modes of operation. Experimental results obtained using a 400-W laboratory-scale hardware verify the theoretical analysis.]]>361213944139578315<![CDATA[Switched-Capacitor-Based Five-Level T-Type Inverter (SC-5TI) With Soft-Charging and Enhanced DC-Link Voltage Utilization]]>361213958139677182<![CDATA[GaN-Based High-Power-Density AC–DC–AC Converter for Single-Phase Transformerless Online Uninterruptible Power Supply]]>3.]]>361213968139845681<![CDATA[A Low-Cost Cell-Level Differential Power Processing CMOS IC for Single Junction Photovoltaic Cells]]>361213985140013917<![CDATA[Capacitor-Voltage Self-Balance Seven-Level Inverter With Unequal Amplitude Carrier-Based APODPWM]]>361214002140134604<![CDATA[Planar Transformer With Asymmetric Integrated Leakage Inductance Using Horizontal Air Gap]]>361214014140286401<![CDATA[Impedance Analysis and Design of IPT System to Improve System Efficiency and Reduce Output Voltage or Current Fluctuations]]>C filter also increases, which may have some negative effects on the characteristics of the inductive power transfer (IPT) system. This article presents an impedance analysis method for C-filter rectifiers in continuous conduction mode. The calculation formula of critical load resistance is given and the relevant values are calculated. An improved C-filter rectifier circuit is proposed to reduce the phase angle of the IPT system. A very tiny capacitance is connected in parallel at the input end of the rectifier to reduce the impedance angle as load resistance changes, with hardly increased costs. This improved method not only improves the system efficiency, but also reduces the fluctuation of output voltage or current. Simulation and experiment results verify the feasibility of the proposed topology. A 1 kW prototype with primary series, secondary series compensation topology was built. The maximum system efficiency from dc power supply to the load is 94.5%. The efficiency under rated load is as high as 93%. Compared with traditional method, it has increased by 0.6%.]]>361214029140382849<![CDATA[Overmodulation Strategy for Seven-Phase Induction Motors With Optimum Harmonic Voltage Injection Based on Sequential Optimization Scheme]]>361214039140506743<![CDATA[Fast Fault-Tolerant Control for Improved Dynamic Performance of Hall-Sensor-Controlled Brushless DC Motor Drives]]>361214051140617529<![CDATA[A Rotor Position and Speed Estimation Method Using an Improved Linear Extended State Observer for IPMSM Sensorless Drives]]>361214062140736699<![CDATA[Three-Dimension Space Vector Based Finite Control Set Method for OW-PMSM With Zero-Sequence Current Suppression and Switching Frequency Reduction]]>$alpha beta {0}$ coordinate system, this article proposes a three-dimension space vector (TDSV) based MPC method under ABC three-phase coordinate system for OW-PMSM with ZSC suppression and switching frequency optimization strategy. Benefiting from the three-phase voltages decoupling feature of OW-PMSM, TDSVs in ABC coordinate system are regularly distributed in a space cube. A simple optimal TDSV selection method is proposed based on subcubes division. TDSV contains the predicted $alpha -,beta -,0 - $axis voltages information, so ZSC suppression is achieved automatically. Furthermore, utilizing the switch states redundancy feature of dual-inverter system, a cost function is designed to optimize the switch states change and reduce the switching frequency without affecting the optimal TDSV selection. The performance and switching frequency reduction effect of the proposed method are verified and compared with the existing methods through experiments.]]>361214074140866639<![CDATA[An Enhanced Linear Active Disturbance Rejection Controller for High Performance PMBLDCM Drive Considering Iron Loss]]>361214087140978022<![CDATA[An Offline Parameter Self-Learning Method Considering Inverter Nonlinearity With Zero-Axis Voltage]]>dq-axis inductance surface by considering the inverter nonlinearity characteristics. A variable amplitude square-wave injection (VASI) scheme is proposed for the dq-axis inductance identification. The VASI method achieves the inductance identification with a novel data sampling strategy. Meanwhile, it can also establish the inductance surfaces by only a few identified data points with a polynomial fitting algorithm, which greatly reduces the identification time compared with the existing methods. The resistance identification is realized by a slope signal injection method, in which the effect of IGBT voltage drop is analyzed. In order to improve the identification accuracy, the inverter nonlinearities are compensated by a self-learning method considering the zero-axis voltage at different rotor positions. At the same time, the sampling error in zero current zones of abc-phases is researched. In order to verify the effectiveness and generality, the proposed method is carried out on two different test machines and confirmed by finite element analysis.]]>361214098141095431<![CDATA[Predictive Torque Control Strategy for Speed Adaptive Flux Observer Based Sensorless Induction Motor Drive in Flux-Weakening Region]]>361214110141184209<![CDATA[A Smart Gate Driver IC for GaN Power HEMTs With Dynamic Ringing Suppression]]>di/dt and dv/dt control and gate protection techniques for gallium nitride (GaN) power transistors usually employ external controllers, isolation circuits, discrete pull-up, and pull-down resistors. With large number of components, power modules become more complex and may introduce additional parasitic. Gate driver ICs with segmented output stages and dynamic gate driving have been reported previously to be effective in simultaneously suppressing gate ringing and overshoot voltage while maintaining fast switching speed. However, the programming for dynamic gate driving is rather complicated, requiring the user to load a sequence of driving patterns obtained from trial and error ahead of time. This article presents a gate driver IC for E-mode GaN power transistors with seven segmented output stages. More importantly, it offers a simplified programming method for the dynamic gate driving pattern. The optimal gate drive pattern can be defined by simply adjusting one external bias resistor. The proposed method eliminates the complex trial and error digital control, and can potentially promoting the wider acceptance of dynamic gate driving by the industry. The timing resolution for the gate drive pattern can be varied in steps from 0.5 to 5 ns. It can also be used to drive many commercially available GaN power transistors.]]>361214119141325235<![CDATA[Predictive Torque Control of Five-Phase Induction Motor Drive Using Successive Cost Functions for CMV Elimination]]>$xy$-subspace current harmonic reduction is achieved with grouped VVs. The developed PTC algorithm has two successive cost functions: $g_{1h}$ for stator flux and electromagnetic torque regulation and $g_{2h}$ for $xy$-subspace current harmonic reduction. The purpose of these two successive cost functions is to reduce the complexity in determining the independent weighting factors. This algorithm retains the torque and flux responses similar to that of conventional PTC. The minimization in switching frequency is obtained in the presented PTC algorithm with the selected set of VVs. For evaluating and ascertaining the capabilities for CMV elimination and $xy$-subspace harmonic current reduction, the proposed algorithm is compared with the conventional PTC algorithm having a different set of VVs. Experimental outcomes show the significance of the discussed algorithm in the steady state and retain the transient operating conditions.]]>361214133141414716<![CDATA[Dual-Vector Located Model Predictive Control With Single DC-Link Current Sensor for Permanent-Magnet Linear Motor Drives]]>361214142141548263<![CDATA[Unified Models for Coupled Inductors Applied to Multiphase PWM Converters]]>361214155141749153<![CDATA[A Two-Stage Automotive LED Driver With Multiple Outputs]]>$N = 1$$-$ 18 LEDs. The measured system efficiency is greater than 88% over wide input (8$-$18 V) and output (3–50 V) voltage ranges, with a peak efficiency of 93%.]]>361214175141866743<![CDATA[LED Current Balancing Scheme Using Current-Fed Quasi-Z-Source Converter]]>361214187141942927<![CDATA[Miller Capacitance Cancellation to Improve SiC MOSFET's Performance in a Phase-Leg Configuration]]>MOSFETs leads to the Miller effect during switching transients. The Miller capacitance in a phase-leg configuration causes the crosstalk, the interaction between the two complementary switches, and the Miller plateau during the switching transient. The Miller effect reduces the switching speed, reduces reliability, and increases electromagnetic interference. In this article, by injecting a mirror cancellation current, the effects of Miller capacitance are canceled. The proposed technique includes a two-stage sensing and injection network to compensate for the nonlinearity of the Miller capacitance. The proposed technique can suppress both positive and negative gate voltage spikes induced by the crosstalk and reduce the switching power loss with the increased switching speed. Because no external control signals are required in the proposed technique, it can work with almost all commercial gate drivers. The detailed design for this proposed technique is presented in this article. The proposed technique was validated with both simulations and experiments.]]>361214195142065052<![CDATA[Overvoltage and Oscillation Suppression Circuit With Switching Losses Optimization and Clamping Energy Feedback for SiC MOSFET]]>off overvoltage and oscillation caused by the fast switching characteristics of SiC MOSFET. However, the turn-on switching losses will significantly increase as the snubber decouples the power loop parasitic inductance during the switching process. In this article, the effect of the power loop parasitic inductance on the switch performance of SiC MOSFETs and the quasi-zero voltage switching (QZVS) turn-on condition are studied. On this basis, an SiC MOSFET overvoltage and oscillation suppression circuit (OVSC) with not only the switching losses optimization feature but also the clamping energy feedback characteristic is proposed. The overvoltage and oscillation can be effectively suppressed by clamping capacitors, and those capacitors do not participate in the switching process until the overvoltage occurs, which is of benefit to the switching losses reduction compared with the other normal snubber circuits. Besides, the turn-off overvoltage and oscillation energy stored in the clamping capacitors can be feedback to dc and load side through a passive branch composed of an energy feedback inductor and a diode. The experimental studies and comprehensive comparison studies are carried out to verify the validity of the proposed OVSC. The experimental results show that OVSC has excellent overvoltage and oscillation suppression performance and can significantly reduce the switching losses.]]>361214207142196586<![CDATA[Capacitors Voltage Ripple Complementary Control on Three-Level Boost Fed Single-Phase VSI With Enhanced Power Decoupling Capability]]>ω) frequency ripple caused by the instantaneous power unbalance between dc- and ac-side. The existing solutions either apply a large capacitor or employ a small power converter to compensate it, which inevitably increases the system cost and control complexity. To overcome these drawbacks, this article performs the transient modeling analysis and it reveals that 2ω frequency power component in the converter achieves minimum value when the inductor current ripple is minimized. A novel capacitors’ voltage ripple complementary control algorithm based on three-level boost fed single-phase VSI is proposed. By mitigating the 2ω power component from the inductor and redistributing the stored energy between two intermediate series-connected capacitors, the oscillating power is absorbed with notably eliminated input current ripple and significantly reduced dc-link voltage ripple. Thus, the good power quality of both dc- and ac-side is guaranteed. Furthermore, the total capacitance requirement is minimized under the given dc-link ripple tolerance without any more electric stress increment and lifetime reduction. Simulation and experiment results verify the theoretical analysis and proposed control method. It is promising in applications, where both input current ripple is strictly limited and ac output voltage quality is highly required with small dc-link capacitance.]]>361214220142365832<![CDATA[Flux Linkage-Based Direct Model Predictive Current Control for Synchronous Machines]]>361214237142566363<![CDATA[Identification of IPMSM Flux-Linkage Map for High-Accuracy Simulation of IPMSM Drives]]>361214257142665620<![CDATA[Variable DC-Link Voltage Regulation of Single-Phase MMC Battery Energy-Storage System for Reducing Additional Charge Throughput]]>361214267142818331<![CDATA[An Ignored Culprit of Harmonic Oscillation in <italic>LCL</italic>-Type Grid-Connected Inverter: Resonant Pole Cancelation]]>LCL-type grid-connected inverter. However, its potential impact on the system stability has not been adequately assessed. This article provides a comprehensive investigation on three typical control schemes that utilize resonant pole cancelation. An important finding is drawn that the resonant pole cancelation violates the so-called internal stability, which can give rise to the undesired harmonic oscillation in grid current. From the physical insights, it is revealed that the resonant pole cancelation does not essentially eliminate the LCL resonance but merely “hide” it in the system, which can still be triggered and, thereby, turns into the culprit of the harmonic oscillation. The theoretical expectation is validated by the simulation and experimental results.]]>361214282142944750<![CDATA[Robust Predictive Control for Modular Solid-State Transformer With Reduced DC Link and Parameter Mismatch]]>3612142951431110149<![CDATA[Constrained Control of Low-Capacitance Delta Cascaded H-Bridge StatComs: A Model Predictive Control Approach]]>361214312143284603<![CDATA[Enhanced Force Estimation for Electromechanical Brake Actuators in Transportation Vehicles]]>361214329143393522<![CDATA[Global Optimal Cooperative Control of Multiple DC–DC Converter Systems for Dynamic Consensus]]>361214340143525104<![CDATA[Discontinuous Space Vector Modulation for Three-Phase Five-Levels Packed-U-Cell Converter]]>abc coordinates. Moreover, the switching sequence is defined online in order to reduce the converter phase voltage transitions while ensuring half-wave symmetry. In addition, a cost function is proposed to optimize the number of commutations and maintain the capacitor voltages balanced. The proposed algorithm presents advantages when compared to other strategies, such as low computational effort, reduced switching losses, and smaller capacitors. Simulation results demonstrate the good performance and effectiveness of the proposed modulation compared to works previously published in the literature. Finally, experimental results from 2-kVA three-phase five-levels packed-U-cell converter are given to support the theoretical developments.]]>361214353143654637<![CDATA[A Class of Linear–Nonlinear Switching Active Disturbance Rejection Speed and Current Controllers for PMSM]]>$b_{02}$ is not estimated accurately.]]>361214366143826284<![CDATA[Hybrid Control Strategy for an Integrated DAB–LLC–DCX DC–DC Converter to Achieve Full-Power-Range Zero-Voltage Switching]]>3612143831439711772<![CDATA[Robust Continuous Model Predictive Speed and Current Control for PMSM With Adaptive Integral Sliding-Mode Approach]]>361214398144084372<![CDATA[Multimode Smooth Transition Technique for Three-Level Cascaded Noninverting Buck–Boost DC–DC Converter]]>361214409144193704<![CDATA[Impedance Adaptive Dual-Mode Control of Grid-Connected Inverters With Large Fluctuation of SCR and Its Stability Analysis Based on D-Partition Method]]>361214420144356965<![CDATA[Review and Comparison of Control Strategies in Active Power Decoupling]]>361214436144557870<![CDATA[A Dual Modulation Waveform PWM Combined With Phase-Shifted Carriers in Stacked Multicell Converter]]>361214456144656393<![CDATA[A Multiple-Reference Complex-Based Controller for Power Converters]]>361214466144773817<![CDATA[Novel Three-Layer Discontinuous PWM Method for Mitigating Resonant Current and Zero-Crossing Distortion in Vienna Rectifier With an <italic>LCL</italic> Filter]]>LCL filter has the challenge of resonant current mitigation, current zero-crossing distortion elimination, neutral point (NP) voltage balance and switching loss reduction. Moreover, these problems are mutually coupled. To overcome these issues, the causes of resonant current with the conventional discontinuous pulsewidth modulation (PWM) (DPWM) method is analyzed, which reveals that the abrupt change of reference voltage has a wide range harmonics band and easily induces the resonant current at resonant frequency. Then, based on the analysis, a novel three-layer DPWM method with three offset voltages injection is proposed. In the first layer, the NP voltage balance is realized by injecting the first offset voltage. In the second layer, the second offset voltage, which makes the discontinuous reference voltages smooth is presented to reduce the losses and suppress the resonant current. In the third layer, the third offset voltage is elaborated to eliminate current zero-crossing distortion caused by different power factor and the LCL filter. Based on the proposed method, resonant current mitigation, current zero-crossing distortion elimination, NP voltage balance are realized simultaneously with reduced switching losses. The effectiveness and performance of the proposed method are verified by simulation and experiment.]]>361214478144908976<![CDATA[Modulation Restraint Analysis of Space Vector PWM for Dual Three-Phase Machines Under Vector Space Decomposition]]>αβ and xy subspaces, respectively. However, the modulation of voltage references in the two subspaces using the space vector pulsewidth modulation (SVPWM) is not independent but coupled. In that, voltage references of two subspaces cannot be modulated simultaneously beyond the modulation restraints, thereby distorting the voltage regulation and causing harmonics or even system misbehavior. Meanwhile, the fundamental voltage in αβ subspace responsible for electromagnetic torque generation should be prioritized and secured. Thus, this article proposes a systematic analysis of modulation restraints of three representative SVPWM techniques, i.e., the linear modulation range of xy subspace under an assured modulation index of the fundamental voltage. Voltage references of xy subspace within this range can be modulated successfully without affecting the assured modulation index and the margin left for harmonic control in xy subspace is then acknowledged. This can be used to limit the output of current controllers not to exceed the voltage modulation restraint, thereby avoiding the modulation failure. Finally, the experimental results validate the linear modulation range and demonstrate the modulation behaviors within and out of the linear modulation range.]]>3612144911450714278<![CDATA[Robustness Investigation of Multi-Inverter Paralleled Grid-Connected System With <italic>LCL</italic>-Filter Based on the Grid-Impedance Allocation Mechanism]]>LCL-type inverters. By establishing the multi-input multi-output matrix of the multi-inverter system, the system stability is divided into two parts, i.e., the self-stability and the interactive-stability. Then, based on elaborate deduction for the interactive-stability, the equivalent allocation mechanism of grid impedance is raised and a stability criterion for multimodule inverters system is proposed. In addition, on the basis of exploring the effect of the digital-control delay on the stability of the multi-inverter system in the weak grid, the phase-lead compensator combining with the optimal capacitor-current-feedback coefficient is adopted to improve the system robustness against grid impedance variation. Finally, the effectiveness of the theoretical analysis is verified by experimental results.]]>361214508145246242<![CDATA[Robust Active Damping Strategy for DFIG Wind Turbines]]>LCL filter are widely used for wind power generation. In these energy conversion systems, there is an interaction between the grid-side converter (GSC) and the rotor-side converter (RSC) control loops, the generator and the LCL filter that must be properly modeled. Such interaction between the GSC and the RSC proves to have a significant influence on the stability. Several active damping (AD) methods for grid-connected converters with an LCL filter have been proposed, nevertheless, the application of these techniques to a DFIG wind turbine is not straightforward, as revealed in this article. To achieve a robust damping irrespective of the grid inductance, this article proposes an AD strategy based on the capacitor current feedback and the adjustment of the control delays to emulate a virtual impedance, in parallel with the filter capacitor, with a dominant resistive component in the range of possible resonance frequencies. This work also proves that, by applying the AD strategy in both converters simultaneously, the damping of the system resonant poles is maximized when a specific value of the grid inductance is considered. Experimental results show the interaction between the GSC and the RSC and validate the proposed AD strategy.]]>361214525145386573<![CDATA[A Fast-Decoupled Space Vector Modulation Scheme for Flying Capacitor-Based Multilevel Converters]]>361214539145496506<![CDATA[Simplified Modeling and Control of a GaN Switched-Capacitor Converters With Phase Shift Modulation]]>361214550145669562<![CDATA[Design and Implementation of Two Hybrid High Frequency DPWMs Using Delay Blocks on FPGAs]]>361214567145784618<![CDATA[Linear Active Disturbance Rejection Controllers for PMSM Speed Regulation System Considering the Speed Filter]]>361214579145926879<![CDATA[IEEE Power Electronics Society]]>3612C3C334<![CDATA[Administrative Committee]]>3612C4C427