<![CDATA[ IEEE Transactions on Power Electronics - new TOC ]]>
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TOC Alert for Publication# 63 2020August 06<![CDATA[Table of Contents]]>3512C112584121<![CDATA[IEEE Power Electronics Society]]>3512C2C2148<![CDATA[<inline-formula><tex-math notation="LaTeX">$C_{text{oss}}$</tex-math></inline-formula> Loss Tangent of Field-Effect Transistors: Generalizing High-Frequency Soft-Switching Losses]]>$E_{text{diss}}$) related to the resonant charging–discharging of a transistor output capacitance becomes a dominant loss factor for power converters operating in the MHz range. A recent letter has introduced a small-signal measurement method to quantify $E_{text{diss}}$ with a frequency-dependent small-signal resistance, $R_{text{s}}$, and an effective small-signal output capacitance, $C_{text{oss}}^{text{eff}}$. This letter provides further insights on the effect of $R_{text{s}}$ and $C_{text{oss}}$ upon the device losses in a broader sense. In particular, the $C_{text{oss}}$ loss tangent, tan ($delta$), is introduced as a normalized $E_{text{diss}}$ to combine the roles of $R_{text{s}}$ and $C_{text{oss}}$ together with the operating frequency into a single loss parameter. By evaluating commercial device families, it is demonstrated that tan ($delta$) is constant for a given family, independent of device on-state resistance, $R_{text{DS(on)}}$. It is shown-
that a minimum $E_{text{diss}}$ is achieved by having the lowest tan ($delta$) for a given stored energy ($E_{text{oss}}$) in $C_{text{oss}}$. With accompanying guidelines, this letter identifies tan ($delta$) as a powerful figure of merit to classify field-effect transistors (FETs) for soft-switching applications, regardless of $R_{text{DS(on)}}$ variations in devices within a family. The proposed concept provides a comprehensive method to characterize and benchmark field-effect transistors for efficient operation in high and very-high-frequency (VHF) applications.]]>351212585125891051<![CDATA[A Digital Interconnected Bus Providing Voltage Synchronization for the Modular Series-Connected Inverters]]>351212590125942753<![CDATA[Comparison of Wide-Band-Gap Technologies for Soft-Switching Losses at High Frequencies]]>on-state resistance (${R}_{text{DS(ON)}}$) degradation, also charging/discharging of input capacitance (${C}_{text{ISS}}$) and output capacitance (${C}_{text{OSS}}$). As datasheets lack such important information, we present measurement techniques and evaluation methods for soft-switching losses in WBG transistors which enable a detailed loss-breakdown analysis. We estimate the gate loss under soft-switching conditions using a simple small-signal measurement. Next, we use Sawyer–Tower and nonlinear resonance (NR) methods to measure large-signal ${C}_{text{OSS}}$ energy losses up to 40 MHz. Finally, we investigate the dependence of dynamic ${R}_{text{DS(ON)}}$ degradation on off-state voltage using pulsed-IV measurements. We demonstrate an insightful comparison of soft-switching losses for various normally off gallium nitride (GaN) and silicon carbide (SiC) devices. A p-GaN-gated device exhibits the most severe ${R}_{text{DS(ON)}}$ degradation and the lowest gate loss. Cascode arrangement increases threshold voltage for GaN devices and reduces gate losses in SiC transistors; however, it leads to higher ${C}_{text{OSS}}$ losses. The study facilitates the evaluation of system losses and selection of efficient WBG devices based on the trade-offs between various sources of losses at high frequencies.]]>351212595126002804<![CDATA[Resilient Operation of Heterogeneous Sources in Cooperative DC Microgrids]]>heterogeneity between each source based on factors, such as capacity, reliability, and generation cost. This letter proposes a novel resilient methodology, which involves detection using adaptive discord element and immediate mitigation via an event-driven approach. The proposed approach successfully mitigates cyber attacks under experimental conditions.]]>351212601126052405<![CDATA[A Reconstructed S-LCC Topology With Dual-Type Outputs for Inductive Power Transfer Systems]]>351212606126112405<![CDATA[Fast Simulation of Litz Wire Using Multilevel PEEC Method]]>351212612126161046<![CDATA[Harmonic Reduction for 12-Pulse Rectifier Using Two Auxiliary Single-Phase Full-Wave Rectifiers]]>351212617126221807<![CDATA[A SiC MOSFET and Si IGBT Hybrid Modular Multilevel Converter With Specialized Modulation Scheme]]>351212623126282671<![CDATA[A Simple Equation for the Energy Stored by Voltage-Dependent Capacitances]]>CV^{2} should be replaced by a new term γ, which depends on the device structure. By applying our proposed method to several commercial diodes and transistors, we show that it matches the measured data much better than using the effective capacitances. The proposed equation will enable better power circuit design by improving the accuracy of stored energy calculations.]]>35121262912632605<![CDATA[DC-DC Converter Synthesis: An Inverse Problem]]>35121263312638884<![CDATA[A Quasi-Three-Level PWM Scheme to Combat Motor Overvoltage in SiC-Based Single-Phase Drives]]>$(dv/dt)$ of switching transients brought significant challenges that can hamper the wide adoption of WBG devices in motor drive applications. Specifically, the aggravated motor overvoltage oscillation, due to reflected voltage phenomenon under high $dv/dt$, is one of the most considerable challenges that degrade the motor lifetime. With filter networks acting as the mainstream mitigation method, the advantages of WBG-based motor drives are compromised due to additional size and power loss of the filters. This letter proposes a novel quasi-three-level pulsewidth modulation scheme as a software solution to eliminate motor overvoltage oscillations in cable-fed drives. The proposed scheme adopts a brief zero-voltage state, with a predetermined time, in the midway of each pole-to-pole voltage transition. This allows the voltage reflections along the cable to significantly discontinue after two propagation cycles, securing the motor operation at prescribed voltage levels. The proposed scheme is applicable to two-level voltage-source inverters (VSIs). In this letter, the scheme is presented on a single-phase two-level VSI motor drive, supported with theoretical and experimental proof of concept.]]>351212639126452161<![CDATA[Reducing Migration of Sintered Ag for Power Devices Operating at High Temperature]]>351212646126501238<![CDATA[Inter Harmonic THD Amplification of Voltage Source Converter: Concept and Case Study]]>351212651126561522<![CDATA[Modulation of Bidirectional AC/DC Converters Based on Half-Bridge Direct-Matrix Structure]]>3.]]>351212657126622048<![CDATA[A Unified Power Control Method for Standalone and Grid-Connected DFIG-DC System]]>351212663126672011<![CDATA[A Novel Converter-Breaker Integrated Voltage Source Converter Based on High-Surge IGCT and Fault Self-Clearing Strategy for DC Grid]]>off solid-state switch against fault. Their independent operations are complex and unreliable by two separate control systems. In this letter, a novel converter-breaker integrated voltage source converter (IVSC) based on high-surge integrated gate commutated thyristor is proposed, and to integrate the converter and breaker operation, the fault self-clearing strategy is developed. IVSC can get rid of thyristors and replace DCB with small turn-off capability load switch. This converter-breaker integration can result in advantages including lower manufacturing cost and volume.]]>351212668126723057<![CDATA[Virtual-Flux-Based Passivation of Current Control for Grid-Connected VSCs]]>351212673126772039<![CDATA[Isolated Ultrafast Gate Driver with Variable Duty Cycle for Pulse and VHF Power Electronics]]>on- and off-times and preserve variable duty cycles. With the isolated ultrafast gate driver, an EPC 2038 GaN FET achieves a drain voltage slew rate of over 37 GV/s when hard-switching and improves total efficiency by 8% (including gating loss) with a careful choice of logic inverters in a symmetric 100 MHz current-mode class D (CMCD) wireless power transfer system. The ultrafast gate driver with isolation and positive feedback was implemented with a commercial radio frequency signal transformer and discrete logic inverters and validated in a hard-switching double pulse test, a narrow pulse test repeating at 165 MHz, and a 100 MHz soft-switching CMCD resonant converter.]]>351212678126853603<![CDATA[Analysis and Design of the LLC LED Driver Based on State-Space Representation Direct Time-Domain Solution]]>351212686127015588<![CDATA[A Fault-Tolerant Hybrid Cascaded H-Bridge Multilevel Inverter]]>351212702127157563<![CDATA[An Integrated Boost Active Bridge Based Secondary Inductive Power Transfer Converter]]>351212716127273973<![CDATA[Affine Nonlinear Control of a Multivariate Inductive Power Transfer System With Exact Linearization]]>$backslash$voltage (CV/CC) charging and zero voltage switching (ZVS) operating for EVs, the controllers are designed and optimized in the linear space, and then inverse mapped to the nonlinear space. This avoids designing different controllers for each operating point. Compared with a traditional PI controller, the nonlinear control scheme suggested in this article enables the system to obtain a fixed dynamic response even if the operating point of the IPT system changes. Finally, practical results obtained from a hardware prototype are included. They confirm the performances of the system and indicate that the proposed nonlinear control scheme can automatically maintain CC$backslash$CV output and ZVS operation with a constant response time of 10 ms.]]>351212728127403914<![CDATA[On Beat Frequency Oscillation of Two-Stage Wireless Power Receivers]]>351212741127513255<![CDATA[Dynamic Improvement of Inductive Power Transfer Systems With Maximum Energy Efficiency Tracking Using Model Predictive Control: Analysis and Experimental Verification]]>351212752127644007<![CDATA[Optimal Transmission Range and Charging Time for Qi-Compliant Systems]]>$Theta (1)$ time and does not require any direct information from the transmitting part neither any preparameterized data. Simulation results indicate that the proposed algorithm can mitigate the issue of re-establishing the link when the coils are loosely coupled.]]>351212765127721009<![CDATA[Design of PWM-SMC Controller Using Linearized Model for Grid-Connected Inverter With <italic>LCL</italic> Filter]]>LCL filter. However, how to design the pulsewidth modulation based SMC (PWM-SMC) controller needs to be further explored, especially upon the large variation of the parameters drift and the delay issue. In this article, the essence of two classic SMC methods used in the power converter area is first analyzed in detail. Thus, a novel design of the PWM-SMC controller using a linearized model for the three-phase GCI with an LCL filter is proposed. Based on this, a three-loop step-by-step design of the PWM-SMC controller is developed, by using the closed-loop pole locations. A robust analysis against the parameters drift is also studied. In addition, a discrete state observer is adopted to reduce the number of sensors. Furthermore, a discussion between the proposed control strategy with the existing SMC methods and the full-state feedback controller is carried out. Finally, a 3-kW lab device designed on the dSPACE is constructed to verify the feasibility of the proposed strategy and the correctness of the theoretical analysis.]]>351212773127865755<![CDATA[The Modular Multilevel DC Converter With Inherent Minimization of Arm Current Stresses]]>351212787128006439<![CDATA[DC Voltage Ripple Optimization of a Single-Stage Solid-State Transformer Based on the Modular Multilevel Matrix Converter]]>3C) is introduced and applied to a single-stage ac/dc solid-state transformer (SST), which uses only one concentrated medium-frequency transformer (MFT) for isolation. As a result, the transformer insulation design is simplified significantly and higher power density could be achieved. Meanwhile, a novel decoupling transformation based on two internal three-phase circulating systems is proposed to improve the previous method. Through this transformation, the unbalanced capacitor voltage components can be divided into four independent dimensions, which correspond to four kinds of capacitor voltage ripple frequency. And a dc-side vector model is then established to calculate the required circulating current reference for capacitor balancing. Besides, under the application of SST, the capacitor voltage ripple suppression strategy via injection of extra circulating current is proposed. The amplitude and frequency index is optimized to obtain the best effect. Therefore, the submodule capacitor volume can be reduced to achieve higher power density. Simulation and experimental results are also provided to verify the theoretical analysis.]]>351212801128158222<![CDATA[Interleaved Multilevel Boost Converter With Minimal Voltage Multiplier Components for High-Voltage Step-Up Applications]]>351212816128334782<![CDATA[Synchronization for an MMC Distributed Control System Considering Disturbances Introduced by Submodule Asynchrony]]>351212834128452731<![CDATA[Reconfigurable Hybrid Energy Storage System for an Electric Vehicle DC–AC Inverter]]>351212846128606461<![CDATA[A Novel High-Frequency Bipolar Pulsed Power Generator for Biological Applications]]>μs pulsewidths, 500 kHz within the burst, and 10 kHz within the continuation limited by the input high-voltage dc power supply. All the pulse parameters can be programmed arbitrarily.]]>351212861128704810<![CDATA[A Novel ZVS High-Step-Up Converter With Built-In Transformer Voltage Multiplier Cell]]>MOSFETs are switched with ZVS which minimizes the switching losses of the proposed converter. Besides the voltage stress across the switches is decreased and can be controlled by the built-in transformer turns ratio enabling utilization of low on-state resistance and low forward voltage drop semiconductors. Due to the interleaved structure, the input current ripple is minimized and the thermal stress is shared between the phases. Meanwhile, the charge balance of the capacitors give rise to equal current sharing performance for the two input inductors. All of these factors reduce the power losses and improves the performance of the proposed converter. Finally, in order to verify the operation of the proposed converter, a 35-V input voltage to 500-V output voltage prototype with the rated power of 1 kW is fabricated and tested in the laboratory.]]>351212871128864767<![CDATA[Design and Assessment of External Insulation for Critical Components in a Medium Voltage SiC-Based Converter via Optical Method]]>351212887128975934<![CDATA[Comprehensive Spectral Analysis of PWM Waveforms With Compensated DC-Link Oscillations]]>351212898129085517<![CDATA[Hybrid Alternate-Common Arm Converter With High Power Capability: Potential and Limitations]]>P–Q capability of the hybrid converter is presented and discussed. Finally, simulation and experimental results that confirm the theoretical analysis and the feasibility of the studied converter are presented and discussed.]]>351212909129288130<![CDATA[A Complete HSS-Based Impedance Model of MMC Considering Grid Impedance Coupling]]>351212929129488088<![CDATA[Zero-Voltage and Zero-Current Switching Dual-Transformer-Based Full-Bridge Converter With Current Doubler Rectifier]]>351212949129583112<![CDATA[Analysis, Design, and Implementation of Impulse-Injection-Based Online Grid Impedance Identification With Grid-Tied Converters]]>$boldsymbol{rho } = 0.5$ is chosen in this article for broadband measurement of grid impedance. Furthermore, a related parameter design procedure with optimal injection position and instant is also proposed to reduce system burden and eliminate overmodulation when injecting the impulse. Finally, theoretical results are validated by experiments.]]>3512129591297610956<![CDATA[Modulation and Control of Series/Parallel Module for Ripple-Current Reduction in Star-Configured Split-Battery Applications]]>2). The control methods directly mitigate the source of the ripple current—the fluctuating arm power—by exploiting the parallel interconnection across the CHB^{2} arms. In the lab setup, the proposed solution approximately halves the battery current ripple compared to the CHB counterpart. Finally, this article studies component sizing and limitations of the proposed solution.]]>351212977129875073<![CDATA[Single-Stage PV-Grid Interactive Induction Motor Drive With Improved Flux Estimation Technique for Water Pumping With Reduced Sensors]]>351212988129998160<![CDATA[Optimization Design and Control of Single-Stage Single-Phase PV Inverters for MPPT Improvement]]>f_{0}) ripple in single-stage single-phase photovoltaic grid-connected inverters, the maximum power point tracking (MPPT) will inevitably be affected. To improve the MPPT performances, a passive LC power decoupling circuit with a robust second-order sliding-mode control (SOSMC) is thus proposed in this article. With the passive LC decoupling path, the double-frequency pulsation on the dc link is effectively cancelled out. Thus, the MPPT accuracy is significantly enhanced, and the utilization of a small dc-link capacitor becomes possible. However, resonance between the LC circuit and the main dc-link capacitor may appear, which can be damped through an active damping method. Additionally, the proposed SOSMC ensures good steady-state, dynamic performance (voltage fluctuation and settling time), and the robustness of the dc-link voltage, which is also beneficial to MPPT control in terms of high accuracy and fast dynamics. The systematic design of SOSMC is presented, and a detailed parameter optimization design of LC decoupling circuit is discussed. Experimental tests are performed on a 2.5-kW single-stage single-phase grid-connected inverter, and the results validate the effectiveness of the proposed strategy.]]>351213000130168723<![CDATA[A Step-Up Nonisolated Modular Multilevel DC–DC Converter With Self-Voltage Balancing and Soft Switching]]>351213017130303415<![CDATA[Sequence Impedance Modeling and Stability Analysis for Load Converters With Inertial Support]]>351213031130414520<![CDATA[A High Performance Interleaved Discontinuous PWM Strategy for Two Paralleled Three-Phase Inverter]]>351213042130523982<![CDATA[Wide Input Voltage DC Electronic Load Architecture With SiC MOSFETs for High Efficiency Energy Recycling]]>LLC-DCX using 1200-V SiC MOSFETs as high frequency isolation pre-regulation stage, the proposed architecture can adapt to wide input voltage of 150–750 V with high efficiency. As the bus voltage is 780 V, a T-type three-level inverter is accepted as grid-connected stage for low leakage current, small grid current harmonics and high conversion efficiency. The transfer mechanism of second harmonic component of the input current ripple is analyzed and is well suppressed by proposed current program control. An overshoot-free soft-start control is proposed to minimize resonant current peak using the inverter reverse operation. The switching frequency reduction modulation control is proposed to solve the extremely low duty-cycle problem under high input voltage and low load condition. A seamless mode transition digital control of three-stage load is proposed with smoothly switched capability between the input current loop and input voltage loop to solve the duty-cycle mutation problem during mode transition. A 5-kW, 300-kHz SiC prototype with 150–750 V input was built. The peak full-load efficiency of three-stage architecture is 95% at 750 V input. The power density is 12.6 W/in^{3}.]]>351213053130677132<![CDATA[Resonance-Based Optimized Buck LED Driver Using Unequal Turn Ratio Coupled Inductance]]>mosfet switching losses. The proposed topology is designed in a way that the mosfet works at the significantly lower switching and conduction losses in compared with conventional LED drivers. It elaborates how the proposed topology also improves the overall efficiency by decreasing power losses in other main elements of the driver, including inductance and diode. In addition, a new valley switching implementation is introduced for the new converter, which decreases the cost and dimension of the LED drivers. The experimental results confirm the high efficient operation of the proposed LED driver by reaching the efficiency up to 97% at a wide range of operating voltage.]]>351213068130763806<![CDATA[Three-Port Full-Bridge Bidirectional Converter for Hybrid DC/DC/AC Systems]]>351213077130843937<![CDATA[A QR-ZCS Boost Converter With Tapped Inductor and Active Edge-Resonant Cell]]>351213085130955061<![CDATA[Average Inductor Current Measure and Control Strategy for Multimode Primary-Side Flyback Converters]]>off instant of mosfet. Thus, a compensation circuit is needed to improve the accuracy, which leads to a large area and cost of the controller. In this work, a kind of average inductor current measure and control strategy for multimode is introduced. The average inductor current measurement strategy is based on the Miller stage to recognize the state of the mosfet, which eliminates the error caused by the mosfet. The average current of primary inductor is obtained and there is no need to estimate the rising slope and the peak value of the inductor current. To verify the feasibility of the proposed method, a controller for charging application is fabricated integrated with the proposed method. Hardware experimental results show that the control system can properly operate in multimode. The accuracy of constant output current is ±1% and the line regulation of the system is 1.6% under the input line voltage ranges from 85 to 265 Vac.]]>351213096131032190<![CDATA[Single-Inductor Multi-Input Multi-Output DC–DC Converter With High Flexibility and Simple Control]]>351213104131143648<![CDATA[AC–AC Hybrid Boost Switched-Capacitor Converter]]>351213115131254520<![CDATA[Hold-Up Time Compensation Circuit of Half-Bridge LLC Resonant Converter for High Light-Load Efficiency]]>LLC resonant converter applying a simple circuit with a variable magnetizing inductance scheme for hold-up time requirement. By changing the magnetizing inductance of the main transformer, the proposed converter can satisfy the hold-up time requirement without sacrificing efficiency, featuring small conduction, and turn-off switching losses of the primary switches in the nominal status. In addition, the proposed converter can relieve the burden of the additional components by positioning them on the signal path, and the proposed circuit is self-powered by adding only one additional winding instead of the isolated power supply. Therefore, those of the size and cost of the proposed circuit can be reduced compared to the previous studies. The feasibility of the proposed method was verified with a 350 W prototype converter (56 V/6.25 A), and the improved circuit for the transient mode was also presented. The experimental results validated the theoretical analysis and showed the effectiveness of the proposed converter for high-efficiency applications, especially in light-load conditions.]]>351213126131353113<![CDATA[Charge Pump Gate Drive to Reduce Turn-ON Switching Loss of SiC MOSFETs]]>on loss is the dominant part of the switching loss for SiC MOSFETs in hard switching. Reducing turn-on loss with conventional voltage source gate drives (VSGs) is difficult because of the limited gate voltage rating and large internal gate resistance of SiC MOSFETs. A charge pump gate drive (CPG) that can reduce the turn-on loss is presented in this article. By precharging the charge-storage capacitor in the gate drive with a charge pump circuit, the gate drive output voltage is pumped up to provide higher gate current during the turn-on transient. As a result, the turn-on time and loss is decreased. Moreover, due to the charge transfer from the charge-storage capacitor to the MOSFET gate capacitance, the pumped output voltage can naturally drop back to a normal value that avoids gate overcharging. The structure of the gate drive is simple, and no additional control is needed. The operation of the proposed CPG is verified with double pulse tests based on SiC MOSFETs. The switching loss of the proposed CPG is reduced by up to 71.7% compared to the conventional VSG at full load condition.]]>351213136131474558<![CDATA[New Bridgeless Power Factor Correction Converter With Simple Gate Driving Circuit and High Efficiency for Server Power Applications]]>351213148131562972<![CDATA[Tapped-Inductor-Based Single-Magnetic Bidirectional PWM Converter Integrating Cell Voltage Equalizer for Series-Connected Supercapacitors]]>351213157131715390<![CDATA[Ultrahigh-Voltage Switch for Bidirectional DC–DC Converter Driving Dielectric Elastomer Actuator]]>MOSFET and, therefore, push the limits from 4.5 to 16 kV. At these high-voltage levels, the structure reveals a drastic voltage unbalance related to the transformer interwinding parasitic capacitance. The compensation method proposed to achieve voltage balance only adds few passive components and reduces significantly the additional parallel capacitance of the switch compared to common load side voltage balancing methods. Finally, and as proof of concept, a half-bridge bidirectional converter was designed from this switch technology and drove an actual DEA at 16 kV.]]>351213172131811911<![CDATA[A Review of Switching Oscillations of Wide Bandgap Semiconductor Devices]]>351213182131994004<![CDATA[An Ultrahigh Step-Up Quadratic Boost Converter Based on Coupled-Inductor]]>. Meanwhile, high efficiency is possible as the energy of the leakage inductor is recycled and transferred to the load. The operating principle and steady-state analysis are provided, and a 280-W prototype is designed to verify the validity of the proposed converter.]]>351213200132093967<![CDATA[Multicell Reconfigurable Multi-Input Multi-Output Energy Router Architecture]]>351213210132248928<![CDATA[Novel High-Efficiency Frequency-Variable Buck–Boost AC–AC Converter With Safe-Commutation and Continuous Current]]>on and off in each switching period, Therefore, the proposed converter has less power loss and features high efficiency. With simple and flexible control strategy, the converter is immune of commutation problem and thus no additional safe-commutation strategy or snubber circuit is needed. Power density of proposed converter is high considering the volume metric of the energy storage components. Moreover, the input current of proposed ac–ac converter is continuous. Therefore bulky input filter required by other existing works is totally removed, which further improve the power density. Operation principles and circuit analysis is provided. To verify the performance, a 200-W laboratory prototype is constructed and experiments are conducted in operation of buck and boost mode at step-changed output frequency of 30, 60, and 120 Hz.]]>351213225132388247<![CDATA[General Method for Synthesizing High Gain Step-Up DC–DC Converters Based on Differential Connections]]>351213239132545745<![CDATA[Selective Torque Harmonic Elimination for Dual Three-Phase PMSMs Based on PWM Carrier Phase Shift]]>351213255132695110<![CDATA[Magnetization State Selection Method for Uncontrolled Generator Fault Prevention on Variable Flux Memory Machines]]>d-axis current excitation. Finally, the developed control strategy is verified by experimental measurements on a VFMM prototype.]]>351213270132804575<![CDATA[An Online Data-Driven Method for Simultaneous Diagnosis of IGBT and Current Sensor Fault of Three-Phase PWM Inverter in Induction Motor Drives]]>351213281132948846<![CDATA[Comprehensive Analysis and Experimental Validation of 240<inline-formula><tex-math notation="LaTeX">$^circ$</tex-math></inline-formula>-Clamped Space Vector PWM Technique Eliminating Zero States for EV Traction Inverters With Dynamic DC Link]]>$^circ$-clamped PWM (240CPWM) is analyzed for three-phase converters that have a cascaded connection of a dc–dc stage and a dc–ac stage. A direct application of the proposed concept is electric vehicle (EV) traction inverters that employ a dc–dc stage to interface a relatively low-voltage battery to a high-voltage motor. The 240CPWM method has the major advantages of clamping a phase to the positive or negative rail for 240$^circ$ in a fundamental period, clamping of two phases simultaneously at any given instant, and use of only active states, completely eliminating the use of zero states. These characteristics lead to more than seven times reduction in switching losses of the inverter at unity power factor compared to CSVPWM, comparable or better total harmonic distortion (THD) performance, significant reduction in common-mode voltage and high efficiency. The THD of the line current is analyzed using the notion of stator flux ripple and compared with conventional and discontinuous PWM methods. The switching loss characteristics under different power factor conditions are discussed. Experimental results from a 10-kW hardware prototype are presented. The full load efficiency with the proposed 240CPWM for the dc–ac stage exceeds 99% even with Si insulated-gate bipolar transistors (IGBTs).]]>351213295133076818<![CDATA[Design and Analysis of Electrical Braking Torque Limit Trajectory for Regenerative Braking in Electric Vehicles With PMSM Drive Systems]]>351213308133216563<![CDATA[CMOS Active Gate Driver for Closed-Loop d<italic>v</italic>/d<italic>t</italic> Control of GaN Transistors]]>v/dt of GaN transistors for both 48 and 400 V applications. To mitigate negative effects in the high-frequency spectrum emission, an original technique is proposed to reduce the dv/dt with lower switching losses compared to classical solutions. The AGD technique is based on a subnanosecond delay feedback loop, which reduces the gate current only during the dv/dt sequence of the switching transients. Hence, the dv/dt and di/dt can be actively controlled separately, and the tradeoff between the dv/dt and E_{ON} switching energy is optimized. Since GaN transistors have typical voltage switching times on the order of a few nanoseconds, introducing a feedback loop from the high voltage drain to the gate terminal is quite challenging. In this article, we successfully demonstrate the active gate driving of GaN transistors for both 48 and 400 V applications, with initial open-loop voltage switching times of 3 ns, due to a full CMOS integration. Other methods for dv/dt active control are further discussed. The limits of these methods are explained based on both experimental and simulation results. The AGD showed a clear reduction in the peak dv/dt from –175 to –120 V/ns for the 400 V application.]]>351213322133323653<![CDATA[Low-Noise Initial Position Detection Method for Sensorless Permanent Magnet Synchronous Motor Drives]]>d-axis randomly. As the magnetic pole position is detected, the magnetic polarity can be identified at the same time, based on the accumulation of the induced random HF current peak pairs without any extra signal. In addition, a saturated peak current delay compensation strategy is proposed to reduce the digital delay effects on the magnetic polarity detection. The proposed method makes the entire detection process simpler and faster. Furthermore, power spectral density (PSD) analysis of random HF currents is adopted to provide the theoretical support for noise reduction. Finally, the proposed method is verified by experiments on a 2.2-kW interior PMSM drive platform.]]>351213333133444600<![CDATA[Minimization of Additional High-Frequency Torque Ripple for Square-Wave Voltage Injection IPMSM Sensorless Drives]]>351213345133556489<![CDATA[Analysis and Design of a Low-Cost Well-Performance and Easy-to-Design Current Sensing Circuit Suitable for SiC <sc>mosfet</sc>s]]>mosfets) with high di/dt, even a tiny parasitic inductance in CSRs bring a significant impact on its sensing performance. This article proposes a low-cost well-performance and easy-to-design current sensing circuit that uses the CSRs and an LR compensation network (LRCN) to compensate for the effect of parasitic inductance on transient current sensing. In order to support the parameter selection of the LR network, the effects of parameters such as parasitic capacitance, parasitic inductance, and loads on the performance of the proposed current sensing circuit are analyzed in detail. Meanwhile, a parasitic inductance measurement method that only needs passive probes is proposed to measure and calculate the parasitic inductance of CSRs. This circuit can not only sense the transient current on the printed circuit board level but also observe the transient current on the oscilloscope through a coaxial cable connection. Finally, experimental studies under an inductive load double pulse test setup with SiC mosfets are carried out to verify the validity and feasibility of the proposed transient current sensing circuit. Only a high self-resonant frequency inductor and a surface mounted device resistor are needed to form the LR network to fully compensate the effect of parasitic inductance on CSRs.]]>351213356133666023<![CDATA[Novel iGSE-C Loss Modeling of X7R Ceramic Capacitors]]>magnetic components in power electronics to propose a Steinmetz parameter-based loss modeling approach for X7R CCs, named the Improved Generalized Steinmetz Equation for CCs, or iGSE-C. This model is verified using the Sawyer–Tower circuit to measure losses in a commercially available X7R capacitor across excitation magnitude, dc bias, temperature, excitation frequency, and harmonic injection. Losses are shown to scale according to a power law with charge, with the resulting Steinmetz coefficients valid across dc bias and slightly varying as the temperature is increased. The iGSE-C accurately predicts losses for typical nonsinusoidal phase voltage waveforms with an error under 8%. Finally, the loss modeling technique is demonstrated for the sine-wave output filter of a bridge-leg arrangement with both low- and high-frequency excitations, with total capacitor losses predicted within 12% accuracy.]]>351213367133835200<![CDATA[Comparative Temperature Dependent Evaluation and Analysis of 1.2-kV SiC Power Diodes for Extreme Temperature Applications]]>C_{j}) characteristics. Second, the reverse recovery characteristics are achieved, including peak reverse recovery current (I_{rm}), reverse recovery charge (Q_{rr}), and switching energy (E_{sw}), clarifying a clearer internal relationship between reverse recovery and junction temperature. Meanwhile, the aforementioned critical parameters are further analyzed on an electrical scale with normal atmosphere temperature, including switching speed range of 62.3–2054.8 A/μs, load current range of 6–30 A, and dc voltage range of 400–1000 V. Third, based on newly proposed power loss analysis method, the continuous operation performance of SiC diodes is quantified and analyzed in actual cryogenic converters. The excellent temperature dependence indicates that SiC diodes have great superiority for extreme applications. Importantly, SiC mosfet's body diode shows the great potential to operate as a freewheeling diode in the compact converter, especially at cryogenic temperature.]]>351213384133996185<![CDATA[Improved Methodology for Parasitic Characterization of High-Performance Power Modules]]>351213400134083192<![CDATA[Surge-Energy and Overvoltage Ruggedness of P-Gate GaN HEMTs]]>on and the inductor is discharged. The device failure occurs at the transient of peak resonant voltage and is limited by the device overvoltage capability rather than the surge energy, dV/dt, or overvoltage duration. Almost no energy is dissipated in the resonant withstand process and the device failure is dominated by an electric field rather than a thermal runaway. These results provide critical understandings on the ruggedness of GaN HEMTs and important references for their qualifications and applications.]]>351213409134194247<![CDATA[Nonlinear Compact Thermal Model of the IGBT Dedicated to SPICE]]>351213420134281119<![CDATA[Characterization of a 3.3-kV Si-SiC Hybrid Power Module in Half-Bridge Topology for Traction Inverter Application]]>on current overshooting and turn-on loss of IGBTs, negligible diode reverse recovery time and loss, as well as flexible allowance of IGBT turn-on current rising rate $boldsymbol{dI}/boldsymbol{dt}$. A parameterized study is carried out to benchmark the advantage of this new topology. Based on the experimental results, the performance of the hybrid module in a three-phase traction inverter circuit is also evaluated by means of electro-thermal simulation. The hybrid module distinguishes itself by describing much lower power loss and junction temperature than its Si-based counterpart.]]>351213429134404085<![CDATA[A BGR-Recursive Low-Dropout Regulator Achieving High PSR in the Low- to Mid-Frequency Range]]>μm 5-V CMOS devices. The PSR was measured to be –102 to –80 dB at frequencies from 100 Hz to 0.1 MHz, which is higher than that of prior LDOs with C_{OUT} ≥ 1 μF. The proposed LDO consumes only 50 μA at a load current of 300 mA, and a peak current efficiency of 99.98% was achieved. The line and load regulations were measured as 0.003%/V and 0.28%/A, respectively. This chip shows a figure-of-merit of 11 ps in the transient response.]]>351213441134543681<![CDATA[FPGA-Based Continuous Control Set Model Predictive Current Control for PMSM System Using Multistep Error Tracking Technique]]>d- and q-axes disturbances, an extended SPMSM model-based CCS-MPCC (EXM-CCSMPCC) is designed. However, the EXM-CCSMPCC has serious step response overshoot. Fifth, an extended SPMSM model-based single step error tracking CCS-MPCC is presented, whose dynamic response and steady-state performances deteriorate when the overshoot is reduced. Finally, an MSET-CCSMPCC is proposed to reduce the overshoot and improve the robustness while maintaining excellent dynamic and steady-state performances. Experiments are implemented on a field-programmable gate array based hardware system to verify the excellent performances of the proposed method.]]>351213455134643228<![CDATA[Systematic Design and Optimization Method of Multimode Hybrid Electric Vehicles Based on Equivalent Tree Graph]]>351213465134742199<![CDATA[Small Signal Modeling and Design Analysis for Boost Converter With Valley <italic>V</italic><sup>2</sup> Control]]>V^{2} control can be applied to boost converters. However, the actual transient performance and design methodology are not clear due to insufficient knowledge about its small signal model. In this article, a small signal model of valley V^{2} controlled boost converter is proposed by combining average method and sampled-data method, which is simple and accurate to half the switching frequency. Then, design guidance focused on dynamical performance and stability is provided. Moreover, compensator for the valley V^{2} controlled boost converter is discussed. The proposed small signal model and design guidelines are verified with experimental results. Results first indicate that for the valley V^{2} controlled boost converter, the inductor current information is contained in the control loop because of the discontinuous output voltage ripple, which is totally different from that in V^{2} controlled buck converter. Also, the equivalent series resistance as well as the duty ratio will affect the transient performance to some extent. Moreover, just by using the simple proportional integral compensator, the valley V^{2} controlled boost converter can be compensated, and it possesses fast transient performance. As for the stability issues, the ramp compensation is useful to eliminate the instability, improving the stability margin.]]>351213475134874445<![CDATA[A Symmetrical Control Method for Grid-Connected Converters to Suppress the Frequency Coupling Under Weak Grid Conditions]]>dq-) frame control leads to frequency coupling dynamics, which tends to bring in harmonic instability. In this article, based on the established complex signal impedance model, the influence of the grid impedance and the frequency coupling on system stability is analyzed. For the phase-locked loop (PLL) mainly affects the q-axis dynamics, it is proposed that the q-axis feedforward and the d-axis compensation control methods to decrease the asymmetric influence caused by the PLL. Similarly, for the dc-link voltage controller mainly affects the d-axis current reference, this article proposes a d-axis feedforward and q-axis compensation method to improve the asymmetry dynamics introduced by the dc-link voltage controller. When the proposed methods are adopted, the components introduced by the PLL and the dc-link voltage controller in the coupling terms are eliminated, thereby achieving the purpose of suppressing the frequency coupling phenomenon and improving the system stability. The theoretical analysis and the experimental results show that the proposed methods are effective.]]>351213488134994236<![CDATA[A Double-Modulation-Wave PWM for Dead-Time-Effect Elimination and Synchronous Rectification in SiC-Device-Based High-Switching-Frequency Converters]]>mosfets and SiC Schottky diodes, showing the merits of low voltage losses, low output harmonics, high dc-link voltage utilization, large linear modulation region, and high efficiency.]]>351213500135136403<![CDATA[Multilayer SOH Equalization Scheme for MMC Battery Energy Storage System]]>351213514135277249<![CDATA[Hybrid Modulation Technique With DC-Bus Voltage Control for Multiphase NPC Converters]]>351213528135396681<![CDATA[Analytic Spectral Analysis Technique for Converters Operating With Oscillatory DC-Link Voltage Components]]>$text{1},text{kVA}$, 3-level, $text{240},text{V}$ single-phase full-bridge inverter.]]>351213540135534855<![CDATA[An Adaptive Sensorless Control Technique for a Flyback-Type Solar Tile Microinverter]]>351213554135621978<![CDATA[Investigation of Disturbance Observers for Model Predictive Current Control in Electric Drives]]>351213563135721838<![CDATA[Design of Multifrequency Proportional–Resonant Current Controllers for Voltage-Source Converters]]>351213573135893074<![CDATA[Robust Power Sharing Control for Parallel Three-phase Inverters Against Voltage Measurement Errors]]>351213590136013469<![CDATA[Multifunction Control Strategy for Single-Phase AC/DC Power Conversion Systems With Voltage-Sensorless Power-Decoupling Function]]>3512136021362016990<![CDATA[IoT-Based DC/DC Deep Learning Power Converter Control: Real-Time Implementation]]>351213621136304562<![CDATA[Grey Wolf Optimization Algorithm Based State Feedback Control for a Bearingless Permanent Magnet Synchronous Machine]]>$K_{d}$ are obtained by employing the GWO algorithm. Finally, simulations and experiments are carried out to verify the effectiveness of the proposed method. Comparisons between the controllers with and without the penalty term are conducted. Meanwhile, the proportional-integral (PI) controllers based on the genetic algorithm and the proposed one are compared as well. The results show the superiority of the proposed method reflecting in faster response and no overshoot compared with the PI controllers.]]>351213631136404120<![CDATA[Separate-Structure UDE-Based Current Resonant Control Strategy on <inline-formula><tex-math notation="LaTeX">$LCL$</tex-math></inline-formula>-Type Grid-Tied Inverters With Weighted Average Current Method for Improved Injected Current Quality and Robustness]]>LCL filter has been widely used between inverters and the grid. However, its resonance causes system instability. The weighted-average current (WAC) strategy has been extensively studied to suppress resonance. By selecting a proper weight factor of the inductor and injected current, the order of the LCL can be reduced to first without resonance in the control loop, which can significantly simplify the controller design. Nevertheless, disturbances and uncertainties in the system will affect the control performance of the inverter. In this article, for a WAC-form LCL grid-tied inverter, a separate-structure uncertainty and disturbance estimator (SUDE) inner-loop control strategy with a zero-phase, low-pass, time-delay FIR filter is designed in the discrete domain to eliminate the influence of disturbances and parameter uncertainties on the system, and a proportional resonant controller is adopted as an outer-loop controller. By using the proposed FIR filter, the performance in the rejection of high-frequency harmonics is improved. Moreover, the stability of the proposed two-degree-of-freedom compound controller is analyzed in detail, and the superiority and effectiveness of its robustness to grid impedance and harmonic rejection are shown. Finally, the proposed strategies are validated on a 2-kW experimental platform.]]>351213641136513052<![CDATA[High Performance Model Predictive Control for PMSM by Using Stator Current Mathematical Model Self-Regulation Technique]]>351213652136624776<![CDATA[Hysteresis Voltage Prediction Control for Multilevel Converter in the Series-Form Switch-Linear Hybrid Envelope Tracking Power Supply]]>351213663136723103<![CDATA[Dual-Level Located Feedforward Control for Five-Leg Two-Mover Permanent-Magnet Linear Motor Traction Systems]]>3512136731368616234<![CDATA[Development and Verification Test of the 6.6-kV 200-kVA Transformerless SDBC-Based STATCOM Using SiC-<sc>MOSFET</sc> Modules]]>351213687136965039<![CDATA[Effective Current Limitation for Multifrequency Current Control With Distortion-Free Voltage Saturation and Antiwindup]]>351213697137136453<![CDATA[An Event-Driven Resilient Control Strategy for DC Microgrids]]>events and introduces an event-driven cyber attack resilient strategy for dc microgrids, which immediately replaces the attacked signal with a trusted event-driven signal constructed using True transmitted measurements. This mechanism not only disengages the attack element from the control system, but also replaces it with an event-triggered estimated value to encompass normal consensus operation during both steady state as well as transient conditions even in the presence of attacks. Finally, the event detection criteria and its sensitivity are theoretically verified and validated using simulation and experimental conditions in the presence of both stealth voltage and current attacks.]]>351213714137243141<![CDATA[Variable Switching Periods Based Space Vector Phase-Shifted Modulation for DAB Based Three-Phase Single-Stage Isolated AC–DC Converter]]>351213725137344467<![CDATA[Control Conflict Suppressing and Stability Improving for an MMC Distributed Control System]]>351213735137474434<![CDATA[Soft-Switching Techniques for Single-Inductor Multiple-Output LED Drivers]]>351213748137563359<![CDATA[IEEE Power Electronics Society]]>3512C3C332<![CDATA[Administrative Committee]]>3512C4C426