<![CDATA[ IEEE Transactions on Power Electronics - new TOC ]]>
http://ieeexplore.ieee.org
TOC Alert for Publication# 63 2021January 18<![CDATA[Table of Contents]]>364C13616121<![CDATA[IEEE Power Electronics Society]]>364C2C298<![CDATA[A New Active Thyristor-Based DCCB With Reliable Opening Process]]>off. As a result, the opening process is not fully controllable and reliable. In this letter, a simple active T-CB (AT-CB) topology is proposed. The proposed AT-CB can interrupt both fault current and operation current actively, and the current breaking process is fast, reliable, and fully controllable. Moreover, the proposed AT-CB can be improved to be bidirectional without increasing the conduction loss, and the topology remains simple. Parameters design principle and operation process of AT-CB are presented. Scaled-down experiment verified the effectiveness of the proposed solution.]]>364361736211206<![CDATA[A Simplified Analytical Algorithm in <italic>abc</italic> Coordinate for the Three-Level SVPWM]]>abc coordinate is proposed. The reference-voltage-vector adjustment and the calculation of modulation waves are unified based on the center-aligned SVPWM. The modulation waves can be analytically derived by only eight simple equations, without sector determination, calculation, and assignment of dwell times. Consequently, the complexity of implementing the 3L SVPWM is significantly reduced.]]>364362236272370<![CDATA[A Voltage Balancing Method for Series-Connected Power Devices in an <italic>LLC</italic> Resonant Converter]]>LLC resonant converter. Series connection of power devices can allow an LLC resonant converter to operate in high-voltage applications. One key problem of series-connected power devices is the voltage imbalance due to device parameter deviations and gate drive delays. To achieve voltage balancing, an auxiliary module (AM) is connected in parallel with each power device. Each AM consists of a capacitor and an auxiliary switch with an antiparallel diode. The AM operates as a clamping circuit and voltage among the series-connected power devices can be shared evenly if the AM capacitor voltages are well-balanced. The AM capacitors are charged during the asynchronous period of the series-connected power devices. The excess energy of AM capacitors can be released by the freewheeling current during dead time in an LLC converter. By assigning a pulsing gate signal to AMs with higher voltages in every switching cycle, the AM capacitor voltages can be balanced. The proposed method will not induce additional power loss and does not affect the normal operation of power devices. Experimental results are provided to verify the effectiveness and feasibility of the proposed method.]]>364362836322486<![CDATA[Adaptive Driving Scheme for ZVS and Minimizing Circulating Current in MHz CRM Converters]]>off time should be accurately controlled to achieve zero voltage switching (ZVS) while minimizing circulating current in pulsewidth modulation converters operating at critical conduction mode. Traditionally, the zero-crossing of the inductor current needs to be detected, and the optimal SR turn-off time is set with reference to the zero-crossing signal. However, problems such as nonlinearity and time delay need to be dealt with, and these make the tuning process very time-consuming at high frequencies. Moreover, accurate zero-current detection is also challenging at high frequencies. This letter proposes an adaptive SR turn-off time tuning method for MHz power converters. The body diode conduction of active switch is detected to adjust the SR turn-off time. With the proposed method, the SR turn-off time can be tuned under various working conditions so that ZVS is achieved while circulating current is minimized. The proposed scheme is easy to implement and not sensitive to switching noise at high frequencies. A 500-W gallium nitride based boost converter is built to verify the proposed method, and the peak efficiency reaches 99% at 1 MHz.]]>364363336373549<![CDATA[Multi-Input SECE Based on Buck Structure for Piezoelectric Energy Harvesting]]>π).]]>364363836421909<![CDATA[Double Half-Bridge Submodule-Based Modular Multilevel Converters With Reduced Voltage Sensors]]>364364336482383<![CDATA[First-Fault Detection in DC Distribution With IT Grounding Based on Sliding Discrete Fourier-Transform]]>364364936541677<![CDATA[A Novel Active Voltage Clamping Circuit Topology for Series-Connection of SiC-MOSFET<roman>s</roman>]]>364365536601745<![CDATA[A Digital Control Strategy With Simple Transfer Matrix for Three-Phase Buck Rectifier Under Unbalanced AC Input Conditions]]>364366136662031<![CDATA[Low <sc>MOSFET</sc> Count Isolated DC–AC Converter]]>364366736732455<![CDATA[A Complete Step-by-Step Optimal Design for <italic>LLC</italic> Resonant Converter]]>LLC resonant converters have been widely used in many different industrial applications. Analysis and design methodologies have great effect on the converter performance. Accordingly, a complete step-by-step optimal design methodology based on time-domain analysis has been proposed for an LLC resonant converter in this article. The proposed design methodology is implemented under the worst operation condition, and the following considerations are included to obtain the suitable design area: operation mode; voltage stress for resonant capacitor; zero voltage switching operation for primary switches; and resonant tank root-mean-square current. Then, by finding all possible design candidates and comparing them based on the power loss model, the optimized design candidate can be found. Compared with the existing design methodologies, the proposed one has the advantages of high accuracy and small computation requirement, which makes it application in industry possible. Finally, a 192-W experimental prototype was built to validate the effectiveness of the proposed design methodology. In addition, a MATLAB graphical user interference program was built based on the proposed design methodology to visualize and facilitate the design process for engineers.]]>364367436914879<![CDATA[An Overview of Condition Monitoring Techniques for Capacitors in DC-Link Applications]]>364369237167686<![CDATA[Impact of Star Connection Layouts on the Control of Multiphase Induction Motor Drives Under Open-Phase Fault]]>n-phase machine, independently of the connection of the neutral points. The latter is analytically derived and is based on the space vector representation of the machine model. In addition, it is shown that a low number of neutral points helps to reduce the winding losses in case of an open-phase fault but requires additional control regulators and computational efforts. The theory is applied to an asymmetrical quadruple-three-phase induction machine, which is configured to represent five different motor layouts. Finally, experimental results are presented to validate the control algorithm. The optimal solution that is given in this article can be employed for the control of symmetrical or asymmetrical multiphase machines with different star connection layouts and in any open-phase postfault operation.]]>364371737264256<![CDATA[An Isolated Active Balancing and Monitoring System for Lithium Ion Battery Stacks Utilizing a Single Transformer Per Cell]]>364372737341915<![CDATA[Sequential <italic>V</italic><sub>ce</sub>(<italic>T</italic>) Method for the Accurate Measurement of Junction Temperature Distribution Within Press-Pack IGBTs]]>V_{ce}(T) method with separated gate controller is proposed to measure the junction temperature distribution within press-pack insulated gate bipolar transistors (PP IGBTs), which is not possible for traditional temperature measurement methods due to the enclosed structure and external clamping force of the pressure-type package. This proposed method is integrated into a standard dc power cycling test and the steady-state junction temperature distribution is obtained to validate its applicability and effectiveness. The measured junction temperature exhibited a bathtub type distribution within PP IGBTs. The root cause is the deformation of the copper plate, which was also discussed by the finite-element simulation in previous literature. Furthermore, the influence of static characteristic dispersion is excluded by the chip transposition and the thermomechanical coupling effect is confirmed to be the dominant factor of this junction temperature distribution. Finally, the influence of heating current and heating time on junction temperature distribution is also investigated by the proposed method.]]>364373537436704<![CDATA[Frequency-Domain Identification Based on Pseudorandom Sequences in Analysis and Control of DC Power Distribution Systems: A Review]]>364374437562554<![CDATA[Online Junction Temperature Measurement for SiC MOSFET Based on Dynamic Threshold Voltage Extraction]]>MOSFETs based on the dynamic threshold voltage. The proposed method is independent of load current variation, which eliminates the complicated calibration procedure with load current. First, the physical mechanism and the temperature dependence of the dynamic threshold voltage are analyzed. An analytical model for the dynamic threshold voltage is built to investigate the effects of gate loop parameters on the temperature sensitivity and measurement accuracy. Then, the principle of the dynamic threshold voltage measurement circuit is introduced. Finally, the proposed dynamic threshold voltage measurement circuit is experimentally evaluated through the double-pulse tests. The experimental results show that the dynamic threshold voltage of SiC MOSFET has a good linear relationship with junction temperature. The temperature sensitivity of the dynamic threshold voltage of two SiC MOSFETs is approximately 5.2 mV/°C and 19.6 mV/°C, respectively.]]>364375737685210<![CDATA[A Fault Diagnosis and Postfault Reconfiguration Scheme for Interleaved Boost Converter in PV-Based System]]>364376937806797<![CDATA[A Controllable Thyristor-Based Commutation Failure Inhibitor for LCC-HVDC Transmission Systems]]>364378137922284<![CDATA[Multiphysical Time- and Frequency-Domain Fault Detection and Isolation Technique for Power-Electronic Converters in DFIG Wind Turbines]]>364379338025099<![CDATA[Hurst-Exponent-Based Detection of High-Impedance DC Arc Events for 48-V Systems in Vehicles]]>364380338136970<![CDATA[A 15-W Quadruple-Mode Reconfigurable Bidirectional Wireless Power Transceiver With 95% System Efficiency for Wireless Charging Applications]]>364381438276691<![CDATA[LCCL-LC Resonant Converter and Its Soft Switching Realization for Omnidirectional Wireless Power Transfer Systems]]>364382838393501<![CDATA[Analysis and Utilization of the Frequency Splitting Phenomenon in Wireless Power Transfer Systems]]>364384038513544<![CDATA[A Field Enhancement Integration Design Featuring Misalignment Tolerance for Wireless EV Charging Using <italic>LCL</italic> Topology]]>364385238675937<![CDATA[Flexible Combination and Switching Control for Robust Wireless Power Transfer System With Hexagonal Array Coil]]>364386838826379<![CDATA[Receiver Current-Stress Mitigation for a Dynamic Wireless Charging System Employing Constant Resistance Control]]>364388338935532<![CDATA[Design and Optimization of an Electric Vehicle Wireless Charging System Using Interleaved Boost Converter and Flat Solenoid Coupler]]>364389439086489<![CDATA[A Harmonic Phasor Domain Cosimulation Method and New Insight for Harmonic Analysis of Large-Scale VSC-MMC Based AC/DC Grids]]>3643909392411754<![CDATA[Opportunities, Challenges, and Potential Solutions in the Application of Fast-Switching SiC Power Devices and Converters]]>dv/dt of SiC devices can cause increased electromagnetic interference, current overshoot, cross-talk effect, and have a negative impact on loads such as motors. This article presents several potential solutions to tackle the application challenges and to fully exploit the superior characteristics of SiC devices and converters while attenuating their negative side effects. This article provides an overview of recent SiC device research and development activities based on academic literature, work carried out by the authors and collaborators as well as input from industry. It aims to provide benchmark results and a timely and useful reference to accelerate the adoption and deployment of SiC devices and converters.]]>364392539459357<![CDATA[An Automated Semi–symbolic State Equation Generation Method for Simulation of Power Electronic Systems]]>364394639563333<![CDATA[Multilevel CSC System Based on Series–Parallel Connected Three-Phase Modules With Optimized Carrier-Shift SPWM]]>364395739668405<![CDATA[Three Levels Are Not Enough: Scaling Laws for Multilevel Converters in AC/DC Applications]]>$_{text{rms}}$ applications, with a dc-side voltage of 400 V, achieve ultrahigh efficiency with a simple two-level topology. These single-phase designs typically utilize a line-frequency unfolder stage, which has very low losses and essentially doubles the peak-to-peak voltage that can be generated on the ac side for a given dc-link voltage. For certain applications, however, such as higher power grid-connected photovoltaic inverters, electric vehicle chargers, and machine drives, three-phase converters are needed. Because of the three-phase characteristic of the system, unfolders cannot be similarly used, leading to a higher minimum dc-link voltage of the three-phase line-to-line voltage amplitude, which is typically set to 800 V for 230 V$_{text{rms}}$ phase voltage systems. Previous demonstrations indicate that significantly more levels—and the associated higher cost and complexity—are required for ultrahigh-efficiency three-phase converters relative to their single-phase counterparts. In this article, we seek to determine the fundamental reason for the performance difference between three-phase 800 V dc-link converters and single-phase 400 V converters. First, we build a 2.2 kW dc/ac hardware demonstrator to confirm the necessity of higher complexity converters, showing a simultaneous reduction in efficiency and power density between a two-level 400 V benchmark (99.2% peak efficiency at 18.0 kW/L) and a three-level 800 V inverter phase-leg (98.8%, 9.1 kW/L). With the motivation confirmed, we derive general scaling laws for bridge-leg losses across the number of levels and dc-link voltage, finding the efficiency-optimal chip a-
ea and the minimum semiconductor losses. With commercially available Si or GaN power semiconductors, the scaling laws indicate that six or more levels would be required for an 800 V three-phase ac/dc converter to meet or exceed the bridge-leg efficiency of a two-level 400 V GaN benchmark for a fixed output filter. With a complete Pareto optimization, we find that at least seven levels are necessary to recover the efficiency of the two-level 400 V benchmark, and we validate this theory with a seven-level 800 V 2.2 kW hardware prototype with a power density of 15.8 kW/L and a peak efficiency of 99.03%. Finally, two practical solutions that make use of the benefits of unfolder bridges familiar in single-phase systems are identified for three-phase systems.]]>364396739864628<![CDATA[Discontinuous Space Vector Modulation Schemes for Modular Multilevel Converters]]>364398739944458<![CDATA[Modeling of Interconnected Voltage and Current Controlled Converters With Coupled <italic>LC</italic>–<italic>LCL</italic> Filters]]>LC filter and current control mode with L/LCL filter are interconnected, forming a more complicated impedance network and resulting in coupled control behaviors. This type of interconnected converter system can be commonly seen in a stand-alone microgrid and some advanced testing benches for power electronics converters. In this article, a system consisting of a voltage-controlled converter with LC filter and a current-controlled converter with LCL filter have been studied. A detailed mathematical model is proposed to describe the stability and coupling characteristics of such system. It is found that the stability problem in this type of configuration may arise in an uncommon way, which is different from the typical resonance in a grid-connected converter system and can be triggered in higher frequency band. Meanwhile, the voltage and current behaviors of interconnected converters are strongly coupled through the complicated filter impedances and control loops in low-frequency band and mid-frequency band.]]>364399540054049<![CDATA[FPGA-Based Deep Convolutional Neural Network of Process Adaptive VMD Data With Online Sequential RVFLN for Power Quality Events Recognition]]>364400640155263<![CDATA[Design of Passivity-Based Damping Controller for Suppressing Power Oscillations in DC Microgrids]]>364401640287073<![CDATA[Topology Modeling and Design of a Novel Magnetic Coupling Fault Current Limiter for VSC DC Grids]]>364402940415329<![CDATA[Mitigation of Double-Line-Frequency Current Ripple in Switched Capacitor Based UPS System]]>LC filter size, and less total harmonic distortion with better output waveforms. Because of the high-temperature operability and the faster switching speed of GaN semiconductor based power devices, cooling system size will further decrease, and with less reverse recovery, no snubber circuits are required. A small size dc-link capacitor can be achieved through coordination control of rectifier and inverter to cancel the second-order oscillation power. Maximum available phase difference between rectifier's and inverter's modulation references is investigated and high modulation indices are proved to be feasible for second-order power cancellation in the dc link. Theoretical analysis, simulation, and experimental results are provided to validate the effectiveness of the topology and control of the proposed converter.]]>364404240515235<![CDATA[An Improved Bipolar-Type AC–AC Converter Topology Based on Nondifferential Dual-Buck PWM AC Choppers]]>on, and therefore, the PWM dead time is not needed leading to improve the utilization of the duty cycles. Only half of the switches in the proposed converter is switched at high frequency during a switching period at most, which significantly reduces the total switching loss. In particularly, the converter has two greatest advantages that it retains the common sharing ground of the input and output and has the same buck/boost operation process for noninverting and inverting modes. In order to fully testify the performance of the proposed converter, a 500-W experimental prototype is built and tested at different conditions.]]>364405240659173<![CDATA[Analysis of the Influence of Measurement Circuit Asymmetries on Three-Phase CM/DM Conducted EMI Separation]]>${50},$dB at ${30},$MHz. However, a very high-performance CM/DM noise separator is not sufficient. It is theoretically analyzed and experimentally proven that asymmetries in the EMI test setup result in an unwanted conversion between CM and DM EMI noise, and therefore significantly influence the CM/DM EMI separation. In particular, three main influences are identified: the line impedance stabilization network (LISN), the connection cables between LISN and the equipment under test (EUT), and the converter EMI filter. The unwanted noise conversion is pronounced for frequencies in the MHz range, where parasitic resonances occur. Experimental results show a CM-to-DM conversion of up to ${-30},$dB at ${30},$MHz (a degradation by ${20},$dB or a factor of 10 compared to a high-performance separator alone) considering a connection cable length mismatch of roughly ${5},$cm. Values as high as ${-21,}$dB result when standard commercial LISNs are used for the measuremen-
. The impact of asymmetries in the EMI filter is most severe, and clearly limits the EMI noise splitting at high frequencies. A high-performance noise separator can, however, be used to investigate such filter asymmetries (component tolerances and/or layout), and therefore helps to improve the filter design process and facilitates the modeling of EMI noise sources. [COMP: Change bullet list to numbered]]]>364406640806474<![CDATA[A New Gate Drive Power Supply Configuration for Common Mode Conducted EMI Reduction in Phase-Shifted Full-Bridge Converter]]>$dV/dt$ sources generated at different floating points associated to the parasitic capacitances of the isolated barriers of the gate drivers (power supplies, and control signal isolation units), which can increase the conducted electromagnetic interference perturbations. This article is focused on the analysis of a new gate drive power supply configuration, which reduces the CM currents that circulate in the control part of the switching cells. This improvement is achieved by modifying the impedance network of CM current pathways. Experimental results are provided to prove the effectiveness of the new gate drive power supply configuration on a PSFB converter based on SiC-MOSFET devices.]]>364408140903011<![CDATA[Analytical Characterization of CM and DM Performance of Three-Phase Voltage-Source Inverters Under Various PWM Patterns]]>3644091410412710<![CDATA[Low Common-Mode Noise Full-Bridge <italic>LLC</italic> Resonant Converter With Balanced Resonant Tank]]>LLC resonant converter with two balanced resonant tanks. In the proposed converter, each resonant inductor and capacitor is divided into two components with the same value. The CM current flowing through parasitic capacitors of the transformer is reduced due to the balanced resonant tank. Moreover, the CM noise can be significantly reduced by adjacently locating the primary and secondary layers with the same dv/dt characteristic. Therefore, the proposed converter decreases the CM noise generated from the planar transformer (PT) by the balanced resonant tank and proposed layer arrangement of PT and achieves a high power density with a decreased size of the electromagnetic interference filter. The validity of the proposed converter is verified by a 1.5-kW prototype with 400-V input and 270–420-V output.]]>364410541155888<![CDATA[Electromagnetic Disturbance Characteristics and Influence Factors of PETT Oscillation in High-Voltage IGBT Devices]]>off, whose frequency can reach hundreds of MHz. This high-frequency oscillation can induce electromagnetic interference problems and may exceed relevant IEC limits for electromagnetic emission. As one of the electromagnetic disturbance sources from internal IGBT, the PETT oscillation has not attracted much attention in the electromagnetic compatibility (EMC) problems of application and development of high-voltage IGBT devices yet. In this article, the detailed characteristics of PETT oscillation, i.e., oscillation frequency, duration time, and oscillation peak, in high-voltage IGBT devices are systematically investigated by experiments. From the results, oscillation frequency increases with the increase of reverse voltage, whereas decreases with the increase of the temperature. Then, more complex dependencies of the PETT oscillation characteristics on IGBT's commutation conditions are presented. It is shown that its characteristics vary greatly under different reverse voltage, forward current, and temperature. The hazard of PETT oscillation to electronic components is discussed as well. PETT oscillation occurs during the turn-on process, which is first reported. Based on the experiment results, the EMC test related to PETT oscillation is suggested to be performed under different commutation conditions.]]>364411641243375<![CDATA[Novel Reclosing Strategy Based on Transient Operating Voltage in Pseudobipolar DC System With Mechanical DCCB]]>364412541332890<![CDATA[Quantitative Comparison and Analysis of Different Power Routing Methods for Single-Phase Cascaded H-Bridge Photovoltaic Grid-Connected Inverter]]>364413441525843<![CDATA[A Comparative Study on Photovoltaic MPPT Algorithms Under EN50530 Dynamic Test Procedure]]>$text{24.2}%$ and $text{18.8}%$, respectively.]]>3644153416810461<![CDATA[DFIG Active Damping Control Strategy Based on Remodeling of Multiple Energy Branches]]>364416941865013<![CDATA[An MPTD-Specialized MPPT Algorithm Used for a Novel Medium-Power Thermoelectric System]]>$X$ is multiplied with the voltage at time $t$, helping the operation point to relocate near the MPP quickly. The new algorithm structure can be applied with most existing thermoelectric maximum power point tracking (MPPT) algorithms, increasing the tracking efficiency. Furthermore, this article proposes an MPTD-specialized MPPT algorithm based on the new structure. The new algorithm uses the derivative of the power with respect to voltage and current to multiply the reference step $S$. When the temperature difference is 38 $^circ$C, the highest power of 0.7469 V and 70.0667 mW, respectively, can be achieved through the MPTD-specialized method. The tracking efficiency is 42.51% higher compared with the classic perturb & observe (P&O) algorithm.]]>364418741973548<![CDATA[Harmonic Linearization and Investigation of Three-Phase Parallel-Structured Signal Decomposition Algorithms in Grid-Connected Applications]]>364419842133908<![CDATA[Performance Improvement by Mitigating the Effects of Moving Cloud Conditions]]>P–V characteristic curves. Physical relocation of panels can be used as a practical solution to prevent such problems by altering the location of panels but not its electrical circuit. In this article, a reconfiguration technique for all conventional configurations like, series-parallel, bridge-link, honey comb, and total cross tied connections are proposed to reduce current difference between the rows and to improve the irradiance equalization by dispersing the shade. This article proposes a mathematical Tom-Tom puzzle pattern for $5times 5$ array to enhance the output parameters. The performance of all configurations is evaluated with artificially generated shading to resemble moving clouds which are incremented progressively in row-wise and diagonal manner. From the extensive analysis of results, it has been found that the proposed reconfigurations show better performance than its respective static configurations. The proposed configuration is also tested in terms of income generated and a comparison with the existing state-of-art methods to show the supremacy of the proposed approach.]]>364421442232988<![CDATA[System-Level Large-Signal Stability Analysis of Droop-Controlled DC Microgrids]]>364422442365485<![CDATA[Linear Time-Periodic Modeling, Examination, and Performance Enhancement of Grid Synchronization Systems With DC Component Rejection/Estimation Capability]]>364423742534835<![CDATA[Fault Detection in a Hybrid Dickson DC–DC Converter for 48-V Automotive Applications]]>Cadence simulation environment. Besides, a quantitative reliability assessment of the single-phase and multiphase configurations is presented. This has led to the selection of the hybrid Dickson topology, which has the best electrical performance and comparable cost and reliability among all for high-conversion-ratio fault-tolerant 48-V automotive application. Moreover, this article presents a fast and robust short-circuit and open-circuit fault detection scheme for power switches and flying capacitors in a hybrid Dickson dc–dc converter. The detection method only observes the low-voltage switching node, which eliminates the challenges associated with high-voltage high-bandwidth sensing. The performance of the design has been verified using a multiphase 48-V-to-3.3-V 4-to-1 Dickson converter prototype. The measured results demonstrate that the short-circuit faults are detected within two switching cycles of 250 kHz, which is less than the 10-μs short-circuit immunity of commercial silicon devices.]]>364425442686243<![CDATA[Differential Power Processing for Ultra-Efficient Data Storage]]>$^3$ power density was built to support a 450-W HDD storage system with ten series-stacked voltage domains. The prototype was tested on a 50-HDD server testbench, and the overall system loss is below 1 W (99.77% system efficiency). The server was able to maintain high-speed reading and writing operation of all 50 HDDs against the worst hot-swapping scenarios. A variety of hardware/software configurations and many cloud storage techniques were tested on the fully functioning server. Experimental results show that the energy efficiency of large-scale information systems (CPU/GPU clusters, memory banks, HDD arrays, etc.) can be greatly improved by software, hardware, and power codesign.]]>3644269428611528<![CDATA[Research on Losses of PCB Parasitic Capacitance for GaN-Based Full Bridge Converters]]>364428742995675<![CDATA[High-Efficiency Single-Phase Matrix Converter With Diverse Symmetric Bipolar Buck and Boost Operations]]>364430043157841<![CDATA[Power Loss Reduction in Buck Converter Based Active Power Decoupling Circuit]]>364431643253668<![CDATA[A Fully Integrated FVF LDO With Enhanced Full-Spectrum Power Supply Rejection]]>I_{Q}) varying from 27 to 82 μA for a load current I_{LOAD} between 5 μA and 20 mA. The circuit achieves a low frequency PSR of –58 dB with the worst full-spectrum PSR of –9 dB in 20 mA I_{LOAD} with a 300 pF on-chip output capacitor. Further, with an UGB over 400 MHz, the proposed FVF LDO reaches 0.9 ns response time when I_{LOAD} changes between 100 μA and 20 mA with edge times less than 0.8 ns.]]>364432643378554<![CDATA[A 1-A 6-MHz Digitally Assisted Buck–Boost Converter With Seamless Mode Transitions and Fast Dynamic Performance for Mobile Devices]]>364433843515877<![CDATA[A Novel High Step-Up Switched-Capacitor Multilevel Inverter With Self-Voltage Balancing]]>364435243592830<![CDATA[A Hybrid, Fully-Integrated, Dual-Output DC–DC Converter for Portable Electronics]]>$pi$-filter to attenuate the switching ripple to an acceptable value. The filter also helps to isolate the internal ground from the noisy power ground connected to boost converter power stage. By the virtue of time-interleaved switching pattern, switching noise induced in its supply rails by the S-C stage is significantly less, which makes the S-C stage an equivalent quiescent load to the boost stage. A prototype of the proposed hybrid converter has been designed, and implemented in 0.18-$mu$m CMOS process. It consumes 0.82 mm$^{2}$ area, and provides $-$1.45 V, and 3.2 V from an input voltage varying from 1.2 V to 2.7 V at an efficiency $>$ 52% (maximum 77%) for all load conditions.]]>364436043704094<![CDATA[A Reconfigurable Totem-Pole PFC Rectifier With Light Load Optimization Control Strategy and Soft-Switching Capability]]>MOSFET in the continuous conduction mode control. As a result, the proposed converter can achieve high efficiency over the entire load condition. The effectiveness of the proposed converter is verified by a prototype with ac 230V_{rms} input and 750 W output.]]>364437143826287<![CDATA[Comparison of DAB and <italic>LLC</italic> DC–DC Converters in High-Step-Down Fixed-Conversion-Ratio (DCX) Applications]]>LLC converter topologies when utilized in a high-step-down fixed-conversion-ratio application, such as the dc–dc stage in laptop and LED TV adapters. Multiple candidate topologies for this application are compared, motivating the selection of the DAB and the LLC for further investigation. The two converters are first compared using first-order insights, and then using a detailed analytical design methodology focused on zero-voltage switching. Fundamental tradeoffs between conduction and switching losses are analyzed, predicting that the DAB converter should achieve higher efficiency at heavy loads due to lower conduction losses, while the LLC converter should achieve higher efficiency at lighter loads due to lower switching losses. To validate these predictions, design examples are developed for a 1-MHz 400–20 V 330-W application, and experimental prototypes for both converters are built based on these designs. Measured results match well with the predictions. The DAB prototype achieves a peak efficiency of 94.9% at full load, corresponding to a 27% reduction in losses compared to the LLC prototype.]]>364438343984089<![CDATA[Evaluation of Three Improved Space-Vector-Modulation Strategies for the High-Speed Permanent Magnet Motor Fed by a SiC/Si Hybrid Inverter]]>364439944095460<![CDATA[Analytical Calculation of Performance of Line-Start Permanent-Magnet Synchronous Motors Based on Multidamping-Circuit Model]]>364441044194763<![CDATA[Real-Time Acoustic Emission Monitoring of Wear-Out Failure in SiC Power Electronic Devices During Power Cycling Tests]]>on–off switch and the ambient noise via a noise filtering process, AE signals were successfully collected for the SiC devices during a power cycling test. Furthermore, AE monitoring was compared to the traditional failure monitoring method using forward voltage. Physics-of-failure analysis was performed, and fatigue cracks, and lift-off in Al ribbons were confirmed as the dominant failure modes for the discrete devices. Specifically, AE counts that correspond to one of the time-domain parameters of AE signals increased with power cycling, thereby corresponding to the observed fatigue cracks in Al ribbons leading to lift-off failure. Additionally, the AE count rate was highly correlated with the crack growth rate. Based on the relationship between an AE count rate and fatigue crack growth rate, the results indicate that AE monitoring can be used to understand the fatigue propagation in Al ribbons (i.e., failure mechanism) and also as an early warning before catastrophic lift-off fracture for power electronic devices.]]>364442044284011<![CDATA[Modeling and Analysis of Bridge-Leg Crosstalk of GaN HEMT Considering Nonlinear Junction Capacitances]]>on. To suppress the crosstalk phenomenon, this article proposes an analytical model about the crosstalk voltage, with consideration of nonlinearities in capacitance–voltage (C–V) of GaN HEMT. By utilizing the equivalent circuit of control transistor and synchronous freewheeling transistor, the number of analytical model parameters to be extracted can be reduced significantly. Besides, the nonlinear characteristic of junction capacitances is taken into account in the model, and the accuracy is verified by the current–voltage (I–V) curve of capacitances. Based on the model, an exhaustive investigation into the impact of device and circuit parameters on the crosstalk phenomenon is conducted. Further, for the purpose of evaluating the oscillation of crosstalk voltage, the damping ratio and oscillation frequency are acquired. The proposed model can be applied to guiding GaN device selection and printed circuit board (PCB) circuit design. The effectiveness and superiority of the proposed model are verified with simulations and experiments on a double pulse test platform.]]>364442944396674<![CDATA[Improved Direct Torque Control for Open-Winding PMSM System Considering Zero-Sequence Current Suppression With Low Switching Frequency]]>364444044514213<![CDATA[Generalized PWM Method for Series-End Winding Motor Drive]]>364445244626819<![CDATA[Cyber-Physical Security of Electric Vehicles With Four Motor Drives]]>364446344774313<![CDATA[Order-Domain-Based Harmonic Injection Method for Multiple Speed Harmonics Suppression of PMSM]]>364447844873583<![CDATA[Computation-Efficient Solution to Open-Phase Fault Tolerant Control of Dual Three-Phase Interior PMSMs With Maximized Torque and Minimized Ripple]]>364448844993242<![CDATA[High-Precision Position Error Correction Method for the PMSM Based on Low-Order Harmonic Suppression]]>364450045123726<![CDATA[Synthesis of a Cauer Equivalent Circuit for Electric Devices From Computed and Measured Data]]>364451345212843<![CDATA[High-Bandwidth Low-Inductance Current Shunt for Wide-Bandgap Devices Dynamic Characterization]]>364452245312618<![CDATA[Over 40-W Electric Power and Optical Data Transmission Using an Optical Fiber]]>364453245391548<![CDATA[Single-Phase LED Driver With Reduced Power Processing and Power Decoupling]]>364454045484331<![CDATA[Overmodulation Methods for Modulated Model Predictive Control and Space Vector Modulation]]>364454945593226<![CDATA[One Improved Sliding Mode DTC for Linear Induction Machines Based on Linear Metro]]>364456045718906<![CDATA[Optimal Asymmetric Duty Modulation to Minimize Inductor Peak-to-Peak Current for Dual Active Bridge DC–DC Converter]]>364457245844554<![CDATA[Coordination Control of Modulation Index and Phase Shift Angle for Current Stress Reduction in Isolated AC–DC Matrix Converter]]>364458545967320<![CDATA[Second Harmonic Current Reduction for Two-Stage Inverter With DCX-<italic>LLC</italic> Resonant Converter in Front-End DC–DC Converter: Modeling and Control]]>f_{o}), generating the second harmonic current (SHC), which will propagate into the front-end dc–dc converter. This article aims for suppressing the SHC in the front-end dc–dc converter with dc transformer (DCX)-LLC resonant converter. The small-signal model of the DCX-LLC resonant converter is proposed, and based on which, the unified small-signal model of the preregulator+LLC converter is built. Then, the basic ideas for reducing the SHC are proposed, including the determination of the filter capacitors in the preregulator+LLC converter and the control approach. After that, from a perspective of output impedance, the control schemes for reducing the SHC in the front-end preregulator+LLC converter are proposed. By inserting a notch filter in the voltage loop and/or introducing a virtual impedance in series with the output rectifier of the LLC resonant converter, the output impedance of the preregulator+LLC converter at 2f_{o} is increased and, thus, the SHC can be reduced. Finally, a 6-kVA two-stage three-phase inverter with boost+LLC converter as the front-end dc–dc converter was fabricated and tested. The experimental results are provided to verify the proposed control schemes.]]>364459746095903<![CDATA[Digital Implementation of Deadbeat-Direct Torque and Flux Control for Permanent Magnet Synchronous Machines in the <italic>M</italic>–<italic>T</italic> Reference Frame]]>M–T reference frame (DB-DTFC-MT) scheme, the stator flux is calculated with the current model, and one-step delay in the digital system is neglected, which results in poor robustness to parameter variations and a serious oscillation in both the stator flux and torque, especially in the low-speed range. In this article, the digital implementation of DB-DTFC-MT is studied. First, the DB-DTFC-MT scheme considering the one-step delay in the digital system is deduced. Second, digital stator flux observer and current observer are developed to predict the stator flux and current in the next sampling instant. By using the predicted stator flux and torque, the oscillation caused by the one-step delay is eliminated and real deadbeat control is realized. Moreover, the robustness of the system to parameter variations is qualitatively evaluated. Although the system shows some sensitivity to the permanent magnet flux, it has strong robustness to the stator resistance and inductances, especially the d-axis inductance. Hence, a larger estimated d-axis inductance can be used in the system for reducing the pulsation in the d-axis current when tracking sinusoidal torque. All the proposed control designs are validated on a real-time control platform based on dSPACE DS1103.]]>364461046217689<![CDATA[An Improved Deadbeat Predictive Current Control Scheme for Open-Winding Permanent Magnet Synchronous Motors Drives With Disturbance Observer]]>d-axis, q-axis, and zero-sequence loop (ZSL) is proposed. First, the parameter mismatches are analyzed. Second, an extended state observer (ESO), which can predict the current in the next instant and the disturbance caused by parameter mismatch, is established. By combining the ESO and the deadbeat predictive current control (DPCC) in the d-axis and q-axis, replacing the sampled current in the DPCC with the predictive current in the ESO, and considering predictive disturbance as a voltage reference feedforward compensation, one-step delay and the disturbance caused by parameter mismatch are addressed. Then, in the ZSL, the predicted zero-sequence disturbance is considered as a compensation for the reference zero-sequence voltage (ZSV). The ZSV is obtained using the zero-voltage vector redistribution strategy in alternate subhexagonal center pulsewidth modulation strategy. The proposed method enhances the robustness of OW-PMSM, against parameter mismatch in the d-axis, q-axis, or ZSL. To verify the effectiveness of the proposed method, simulation and experimental results obtained using the traditional DPCC method and the ESO+DPCC method are presented herein.]]>364462246324489<![CDATA[An Overview of Artificial Intelligence Applications for Power Electronics]]>364463346584756<![CDATA[A Parameter-Independent Optimal Field-Weakening Control Strategy of IPMSM for Electric Vehicles Over Full Speed Range]]>364465946713286<![CDATA[An Improved Direct Power Control for Doubly Fed Induction Generator]]>$alpha beta$). The proposed method uses a simple feed-forward and feedback structure without a phase-locked loop and the Park transformation. Therefore, it can be easily implemented in the BTB converter. Another essential advantage of the proposed VM-DPC is that it can transform the closed-loop DFIG system into a linear-time-invariant one, which can be analyzed and designed through multiple linear control techniques. The proposed method guarantees exponential stability in the stiff grid as well as in weak-grid integration, which is proved based on eigenvalue analysis. Simulation results demonstrate that the proposed VM-DPC has a faster transient response than conventional vector-oriented control (VOC). Also, it maintains a satisfactory steady-state performance at the same level as the VOC. The robustness of proposed VM-DPC against distorted voltage conditions and parameter mismatch is also tested. Finally, the proposed VM-DPC control strategy is validated in an experimental hardware prototype of a 7.5-kW DFIG system operating in real time.]]>364467246857587<![CDATA[An Improved Multimode Synchronized Space Vector Modulation Strategy for High-Power Medium-Voltage Three-Level Inverter]]>364468646966621<![CDATA[Digital Predictive Current-Mode Control of Three-Level Flying Capacitor Buck Converters]]>peak, average, and valley current-mode controllers are studied when operated in single- and multisampled modes. A variant of the multisampled DPCMC obtained through a fast-update of the duty cycle command is also disclosed and analyzed. Results indicate that single-sampled DPCMC is always stable, and that fast-update approaches can strongly improve the converter dynamic response. Multisampled controllers are also shown to be inherently more robust than single-sampled ones against timing mismatches in the control signals, resulting in a smaller FC voltage imbalance. The analysis is validated in simulation and experimentally on a 500 kHz, 12–1.5 V, 500 mA 3LFC buck case study.]]>364469747104955<![CDATA[A Novel Trapezoidal Wave Control Method for a Single-Phase Grid-Tied T-Type Inverter]]>364471147225430<![CDATA[Universal Full-Speed Sensorless Control Scheme for Interior Permanent Magnet Synchronous Motors]]>364472347376030<![CDATA[Hybrid Duty Modulation for Dual Active Bridge Converter to Minimize RMS Current and Extend Soft-Switching Range Using the Frequency Domain Analysis]]>2SDM) scheme are established to minimize the inductor rms current by considering its fundamental component. Third, the characteristics of SSDM, A_{2}SDM, and the traditional phase shift modulation schemes are compared from several aspects, mainly including the inductor rms current and the soft-switching performance. Furthermore, the loss breakdown analysis results for the three modulation schemes are presented and compared. According to these results, the HDM scheme is proposed to improve the overall efficiency of the DAB converter. Finally, an experimental prototype was built with a peak efficiency of 97%, which validates the effectiveness of the proposed modulation scheme.]]>364473847515226<![CDATA[Improved Operation and Control of Single-Phase Integrated On-Board Charger System]]>364475247658835<![CDATA[Novel Level-Shifted PWM Technique for Equal Power Sharing Among Quasi-Z-Source Modules in Cascaded Multilevel Inverter]]>364476647775255<![CDATA[Device-Level Loss Balancing Control for Modular Multilevel Converters]]>364477847904022<![CDATA[Variable Rounding Level Control Method for Modular Multilevel Converters]]>364479148015047<![CDATA[Robustness Improvement of Model-Based Sensorless SPMSM Drivers Based on an Adaptive Extended State Observer and an Enhanced Quadrature PLL]]>αβ-axis back electromotive forces (EMFs). An adaptive bandwidth tuning scheme is proposed to online tune the parameters of the ESOs, with which the desired estimation performance of back EMFs can be achieved in wide-speed operation range. Additionally, the dynamic mechanical behavior of the sensorless control system during large load torque transient is investigated by using small-signal analysis, and then a corresponding speed estimation compensation scheme for the conventional quadrature phase-locked loop (QPLL) is developed, with which the capability of QPLL in tracking the rapidly changing speed can be significantly enhanced. Experiments on an SPMSM demonstrate the superior robustness of the proposed method to that of the conventional method in transient-state operation.]]>364480248144931<![CDATA[Regulated Resonant Switched-Capacitor Point-of-Load Converter Architecture and Modeling]]>$mu$F capacitor in a 0805 package, achieving high power density. The converter efficiency is demonstrated to be similar to that of an integrated buck converter designed for the same application, whereas the inductor size is reduced by a factor of eight.]]>364481548274324<![CDATA[Communication-Free Power Management Strategy for the Multiple DAB-Based Energy Storage System in Islanded DC Microgrid]]>364482848385581<![CDATA[Simplified Two-Stage Model Predictive Control for a Hybrid Multilevel Converter With Floating H-Bridge]]>364483948506998<![CDATA[Robust Control of Interconnected Power Electronic Converters to Enhance Performance in DC Distribution Systems: A Case of Study]]>364485148633768<![CDATA[The Current Sharing Strategy of Three-Phase Series Capacitor Boost Converter Based on Charge-Balance Method]]>364486448764741<![CDATA[A Variable-Frequency Current-Dependent Switching Strategy to Improve Tradeoff Between Efficiency and SiC MOSFET Overcurrent Stress in Si/SiC-Hybrid-Switch-Based Inverters]]>MOSFET that turns on earlier, and off later. Such issue is attributable to the overcurrent stress under the heavy load operating condition, which adversely affects the SiC MOSFET during the gate delay time. To solve this problem without increasing the extra power loss, a novel variable-frequency current-dependent switching strategy combining the variable switching pattern strategy, and the variable pulsewidth modulation (PWM) frequency strategy is proposed. Variable switching pattern strategy can avoid the overcurrent stress of the SiC MOSFET at the heavy load operating condition, and the designed optimal delay time in different switching patterns can achieve the compromise between the excellent reliability, and the power loss of Si/SiC hybrid switch. Variable PWM frequency strategy can effectively reduce the switching loss of the Si/SiC hybrid switch by decreasing the switching frequency around the peak current region. An Si/SiC-hybrid-switch-based single-phase inverter platform is constructed and tested. Test results show that the power loss of the single-phase inverter adopting such switching strategy outperforms the current-dependent switching strategy with 9.4% reduction of power loss, and overcurrent stress of SiC MOSFET is avoided.]]>364487748863711<![CDATA[Novel Multirate Modulator for High-Bandwidth Multicell Converters]]>n-cell converter may change its average output voltage over each of these intervals, while standard converters can only control the voltage over half the switching period. In this article, a general multirate modulation strategy taking advantage of this property, while avoiding an overswitching, and compatible with any n-cell converter is proposed and validated by simulation and experimental results.]]>364488749005993<![CDATA[IEEE Power Electronics Society]]>364C3C353<![CDATA[Administrative Committee]]>364C4C445