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TOC Alert for Publication# 4 2019April 18<![CDATA[Table of contents]]>544C1C4221<![CDATA[IEEE JOURNAL OF SOLID-STATE CIRCUITS]]>544C2C281<![CDATA[Table of contents]]>544909910214<![CDATA[Introduction to the Special Issue on the 2018 Symposium on VLSI Circuits]]>5449119131562<![CDATA[Chip-Scale Molecular Clock]]>16O^{12}C^{32}S) also enable miniaturization of the gas cell. All these result in an “atomic-clock-grade” frequency reference with small size, power, and cost. This paper provides the architectural and chip-design details of the first proof-of-concept molecular clock using a 65-nm CMOS bulk technology. Using a 231.061-GHz phase-locked loop (PLL) with frequency-shift keying (FSK) modulation and a sub-THz FET detector with integrated lock-in function, the chip probes the accurate transition frequency of carbonyl sulfide (OCS) gas inside a single-mode waveguide, and accordingly adjusts the 80-MHz output of a crystal oscillator. The clock consumes only 66 mW of dc power and has a measured Allan deviation of 3.8 × 10^{-10} at an averaging time of τ = 1000 s.]]>5449149265127<![CDATA[An Ultra-Low-Jitter 22.8-GHz Ring-<italic>LC</italic>-Hybrid Injection-Locked Clock Multiplier With a Multiplication Factor of 114]]>2. The total power consumption was 7.4 mW, but the DPFC consumed only 400 μW.]]>5449279364377<![CDATA[A 12-Bit 31.1-<inline-formula> <tex-math notation="LaTeX">$mu$ </tex-math></inline-formula>W 1-MS/s SAR ADC With On-Chip Input-Signal-Independent Calibration Achieving 100.4-dB SFDR Using 256-fF Sampling Capacitance]]>5449379472478<![CDATA[A 1-mW Class-AB Amplifier With −101 dB THD+N for High-Fidelity 16 <inline-formula> <tex-math notation="LaTeX">$Omega$ </tex-math></inline-formula> Headphones in 65-nm CMOS]]>2 in a standard 65-nm CMOS.]]>5449489586208<![CDATA[A Hybrid Structure Dual-Path Step-Down Converter With 96.2% Peak Efficiency Using 250-m<inline-formula> <tex-math notation="LaTeX">$Omega$ </tex-math></inline-formula> Large-DCR Inductor]]>DCR). Therefore, DPDC achieves a high power efficiency and thus also reduces the heating problem, which is another critical issue in the mobile set. Moreover, DPDC can shrink the volume of the PMIC set with a low manufacturing cost by alleviating an RDCR specification of the inductor. In this paper, although a 250 mQ of large R_{DCR} inductor is used for our measurements, a 96.2% of peak efficiency was achieved and the power loss of total parasitic resistances can be reduced to up to 30% of that of CBC. Moreover, according to our measurement plots, it is verified that DPDC achieves the efficiency notably higher not only in a wide load current (I_{LOAD}) range but also in a wide conversion ratio (V_{OUT}/V_{IN}) range, compared to CBC.]]>5449599672802<![CDATA[A 0.5–1.1-V Adaptive Bypassing SAR ADC Utilizing the Oscillation-Cycle Information of a VCO-Based Comparator]]>5449689772528<![CDATA[A Time-Resolved NIR Lock-In Pixel CMOS Image Sensor With Background Cancelling Capability for Remote Heart Rate Detection]]>-/lux · s, and an ultralow temporal random noise of 1.13 e_{rms}^{-} at analog gain of 64. A maximum charge modulation ratio of 90.1% is obtained for realizing lock-in operation by means of in-pixel lateral electric field charge modulator (LEFM). The remote HR detection is achieved by capturing the heart-beat-induced temporal variation of the oxy-hemoglobin (HbO_{2}) concentration by the developed TR CIS with NIR lock-in technique, and larger than 98% detection accuracies are attained under both non-visible-light condition and fluctuant brightness ambient-light environments. This remarkable feature demonstrates the superiority of the proposed method for driver monitoring applications in particular.]]>5449789916519<![CDATA[A 4096-Neuron 1M-Synapse 3.8-pJ/SOP Spiking Neural Network With On-Chip STDP Learning and Sparse Weights in 10-nm FinFET CMOS]]>54499210024939<![CDATA[Simultaneous Transmission of Up To 94-mW Self-Regulated Wireless Power and Up To 5-Mb/s Reverse Data Over a Single Pair of Coils]]>544100310163463<![CDATA[A Subharmonic Switching Digital Power Amplifier for Power Back-Off Efficiency Enhancement]]>544101710285373<![CDATA[Logic Process Compatible 40-nm 16-Mb, Embedded Perpendicular-MRAM With Hybrid-Resistance Reference, Sub-<inline-formula> <tex-math notation="LaTeX">$mu$ </tex-math></inline-formula> A Sensing Resolution, and 17.5-nS Read Access Time]]>544102910383453<![CDATA[Design of Single-Topology Continuously Scalable-Conversion-Ratio Switched- Capacitor DC–DC Converters]]>544103910474726<![CDATA[A 1920 <inline-formula> <tex-math notation="LaTeX">$times$ </tex-math></inline-formula> 1080 25-Frames/s 2.4-TOPS/W Low-Power 6-D Vision Processor for Unified Optical Flow and Stereo Depth With Semi-Global Matching]]>544104810585559<![CDATA[A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With −41.3-dB EVM at 1024 QAM in 28-nm CMOS]]>-1) digital power amplifier (DPA) for amplitude modulation (AM). The DPA is, unlike in a typical polar transmitter (TX), placed within the PLL and the phase-error detection happens directly at the DPA output. The subsampling polar TX thus becomes sensitive not only to phase errors but also to modulation amplitude. That feature enables AM-AM and PM-PM distortion to be detected and cancelled digitally in the background, while the transmitter operates normally. Moreover, the AM-PM cross distortion is filtered by the loop itself. The chip operates from a 0.9-V supply at 5.5 GHz with 2.5 MHz BW (1024 QAM) with average 1.1-dBm output power and total power consumption of 50 mW.]]>544105910736551<![CDATA[An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS]]>2 facilitates seamless integration in area constrained system-on-chips while achieving: 1) 25% area savings over conventional separate PUF and TRNG implementations; 2) cryptographic quality TRNG stream that passes all NIST randomness tests with 0.38 average p-value; 3) 1.6 × higher extractor performance at 9× lower area with 750-gate hierarchical VN circuit over conventional light-weight entropy extractors; 4) 0.9996/0.99997 static/dynamic Shannon entropy indicating unbiased PUF/TRNG streams; 5) ultra-low energy consumption of 2.5 and 0.46 pJ/bit measured at 650 mV, 70 °C in TRNG and PUF modes; 6) 40% higher TRNG throughput with three-way self-calibration featuring coarse-grain column swap, fine-grain incremental ES su-
stitution, and residual entropy recycling; 7) resistance to power injection attacks as measured by 64% higher performance over un-calibrated design in the presence 200-mV supply noise; 8) 2.8% PUF biterror measured at 0.55-0.75 V, 25 °C-110 °C with 15-way TMV and soft dark-bit masking over a window of 100 cycles; 9) 14.8× inter and intra-PUF hamming distance separation; and 10) 56% reduction in discarded ES cells with selective stress hardening to opportunistically reinforce/nullify pre-existing bias in PUF/TRNG candidate cells. To our knowledge, this is the first reported unified PUF-TRNG implementation enabling simultaneous generation of high-entropy chip-ID and encryption keys in real time.]]>544107410855015<![CDATA[A 12.8-Gb/s Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth, Large-Capacity Storage Systems]]>-12 with power consumption of 252.1 mW for the transmitter and 375.7 mW for all four receivers together.]]>544108610954441<![CDATA[A 5500-frames/s 85-GOPS/W 3-D Stacked BSI Vision Chip Based on Parallel In-Focal-Plane Acquisition and Processing]]>544109611053845<![CDATA[Navion: A 2-mW Fully Integrated Real-Time Visual-Inertial Odometry Accelerator for Autonomous Navigation of Nano Drones]]>544110611197540<![CDATA[An Energy-Efficient Reconfigurable Processor for Binary-and Ternary-Weight Neural Networks With Flexible Data Bit Width]]>544112011365595<![CDATA[A 30-frames/s, <inline-formula> <tex-math notation="LaTeX">$252times144$ </tex-math></inline-formula> SPAD Flash LiDAR With 1728 Dual-Clock 48.8-ps TDCs, and Pixel-Wise Integrated Histogramming]]>544113711513412<![CDATA[A 290-mV, 7-nm Ultra-Low-Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell]]>544115211602822<![CDATA[A 550-<inline-formula> <tex-math notation="LaTeX">$mu$ </tex-math></inline-formula>W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental <inline-formula> <tex-math notation="LaTeX">$SigmaDelta$ </tex-math></inline-formula> ADC With 256 Clock Cycles in 65-nm CMOS]]>2, resulting in Walden/Schreier FoMW/FoMS of 153 fJ/176.4 dB, respectively. The differential and integral nonlinearities are +0.27 LSB/-0.27 LSB and +0.84 LSB/-0.81 LSB, respectively.]]>544116111723945<![CDATA[A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains]]>dd) guardbands to account for supply droop events and temperature variation. These guardbands degrade processor energy efficiency, especially in low-voltage sensor and IoT applications due to increased delay sensitivity to temperature and V_{dd} variation. In this paper, we present an all-digital unified clock and power (UniCaP-SC) architecture that combines switched-capacitor (SC)-based voltage control and clock frequency regulation into a single loop to significantly reduce required Vdd guard-bands. A UniCaP-SC test chip consisting of a nearthreshold voltage (NTV) ARM Cortex-M0 processor was fabricated in 65-nm CMOS. The fully integrated system enables all-digital construction, aggressive V_{dd} margin reduction, and continuous V_{dd} scalability using SC-based voltage converters while no additional decoupling capacitance (decap). Test-chip measurements demonstrate a 16% Vdd reduction corresponding to a 94% V_{dd} margin recovery or an equivalent 3.2× increase in the operating clock frequency ( f_{clk}).]]>544117311844636<![CDATA[A 0.8-V 82.9-<inline-formula> <tex-math notation="LaTeX">$mu$ </tex-math></inline-formula>W In-Ear BCI Controller IC With 8.8 PEF EEG Instrumentation Amplifier and Wireless BAN Transceiver]]>2 chip is fabricated using 65-nm CMOS and contains three key features: 1) current reusing low-noise amplifier (CRLNA) for low power; 2) bootstrapping dc servo loop (BDSL) enabling low-noise measurement even on 350-mV electrode dc offset (EDO); and 3) dual-mode programmable gain amplifier (DMPGA) that reduces TRX power consumption by activating only when the intentional blink is present. EEG instrumentation amplifier (IA) shows the state-of-the-art 8.8 power efficiency factor (PEF) performance, and the entire integrated circuit (IC) consumes 82.9 μW . From the measurement, with nine subjects, the proposed BCI system accomplished 84% average accuracy for the binary selection task.]]>544118511954092<![CDATA[2019 RFIC Symposium]]>544119611961007<![CDATA[Information For Authors]]>544C3C3154