<![CDATA[ IEEE Transactions on Circuits and Systems I: Regular Papers - Popular ]]>
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Popular Articles Alert for this Publication# 8919 2019May <![CDATA[The flipped voltage follower: a useful cell for low-voltage low-power circuit design]]>527127612911168<![CDATA[Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures]]>556144114541188<![CDATA[Full On-Chip CMOS Low-Dropout Voltage Regulator]]>549187918901617<![CDATA[Consensus of Multiagent Systems and Synchronization of Complex Networks: A Unified Viewpoint]]>5712132241045<![CDATA[Understanding Phase Error and Jitter: Definitions, Implications, Simulations, and Measurement]]>6611191696<![CDATA[Tunable Quasi-Circulator Based on a Compact Fully-Reconfigurable 180° Hybrid for Full-Duplex Transceivers]]>668294929624919<![CDATA[Efficient Hardware Architectures for Deep Convolutional Neural Network]]>656194119531975<![CDATA[Switched-Capacitor/Switched-Inductor Structures for Getting Transformerless Hybrid DC–DC PWM Converters]]>5526876961294<![CDATA[Compact Extended Industrial Range CMOS Current References]]>666199820062617<![CDATA[Digital Mismatch Correction for Bandpass Sampling Four-Channel Time-Interleaved ADCs in Direct-RF Sampling Receivers]]>666200720162877<![CDATA[Benefits of Using VCO-OTAs to Construct TIAs in Wideband Current-Mode Receivers Over Inverter-Based OTAs]]>665168116913411<![CDATA[Approximate Multipliers Based on New Approximate Compressors]]>6512416941824744<![CDATA[A Study of Phase Noise and Frequency Error of a Fractional-N PLL in the Course of FMCW Chirp Generation]]>665167016802864<![CDATA[Signal Encoding and Processing in Continuous Time Using a Cascade of Digital Delays]]>663101710302202<![CDATA[Matching Properties of Femtofarad and Sub-Femtofarad MOM Capacitors]]>6367637721936<![CDATA[A frequency compensation scheme for LDO voltage regulators]]>51610411050576<![CDATA[A Novel Digital-Intensive Hybrid Polar-I/Q RF Transmitter Architecture]]>6512439044033773<![CDATA[A Low-Power Deep Neural Network Online Learning Processor for Real-Time Object Tracking Application]]>2 DNN online learning processor shows 126 mW power consumption and the processor achieves 30.4 frames-per-second throughput in the object tracking application.]]>665179418042929<![CDATA[Analysis and Design of Regenerative Comparators for Low Offset and Noise]]>668281728303124<![CDATA[Theory and applications of incremental ΔΣ converters]]>514678690416<![CDATA[Consensus Tracking of Multi-Agent Systems With Lipschitz-Type Node Dynamics and Switching Topologies]]>6124995113732<![CDATA[Implications of Passive Mixer Transparency for Impedance Matching and Noise Figure in Passive Mixer-First Receivers]]>571230923103559<![CDATA[TEAM: ThrEshold Adaptive Memristor Model]]>6012112212472<![CDATA[The Circuit Theory Behind Coupled-Mode Magnetic Resonance-Based Wireless Power Transmission]]>Q) and large coupling distance. It simplifies the analysis by reducing the order of the differential equations by half compared to the circuit theory.]]>599206520742999<![CDATA[A 10-Bit 200-kS/s 1.76-<inline-formula> <tex-math notation="LaTeX">$mu$ </tex-math></inline-formula>W SAR ADC With Hybrid CAP-MOS DAC for Energy-Limited Applications]]>2.]]>665171617273096<![CDATA[Noise Filtering and Linearization of Single-Ended Sampled-Data Circuits]]>664133113413317<![CDATA[Analysis and Design of Passive Polyphase Filters]]>RC polyphase filters (PPFs) are analyzed in detail in this paper. First, a method to calculate the output signals of an n-stage PPF is presented. As a result, all relevant properties of PPFs, such as amplitude and phase imbalance and loss, are calculated. The rules for optimal pole frequency planning to maximize the image-reject ratio provided by a PPF are given. The loss of PPF is divided into two factors, namely the intrinsic loss caused by the PPF itself and the loss caused by termination impedances. Termination impedances known apriori can be used to derive such component values, which minimize the overall loss. The effect of parasitic capacitance and component value deviation are analyzed and discussed. The method of feeding the input signal to the first PPF stage affects the mechanisms of the whole PPF. As a result, two slightly different PPF topologies can be distinguished, and they are separately analyzed and compared throughout this paper. A design example is given to demonstrate the developed design procedure.]]>5510302330371191<![CDATA[Design Methodology for Phase-Locked Loops Using Binary (Bang-Bang) Phase Detectors]]>647163716503613<![CDATA[A Fully-Integrated Low-Dropout Regulator With Full-Spectrum Power Supply Rejection]]>2, including 140 pF of stacked on-chip capacitors.]]>6237077162674<![CDATA[A Self-Powered and Optimal SSHI Circuit Integrated With an Active Rectifier for Piezoelectric Energy Harvesting]]>2. Measured results indicate that the proposed circuit increases the amount of power harvested from a piezoelectric cantilever by 2.1 times when compared with a full bridge (FB) rectifier and achieves a power conversion efficiency of 85%. The proposed circuit dissipates about 24 μW while the controller alone only 1.5 μW.]]>6435375492585<![CDATA[X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories]]>+T Differential cell. In addition, we also present a novel `read-compute-store' scheme, wherein the computed Boolean function can be directly stored in the memory without the need of latching the data and carrying out a subsequent write operation. The feasibility of the proposed schemes has been verified using the predictive transistor models and detailed Monte-Carlo variation analysis. As an illustration, we also present the efficacy of the proposed in-memory computations by implementing advanced encryption standard algorithm on a non-standard von-Neumann machine wherein the conventional SRAM is replaced by X-SRAM. Our simulations indicated that up to 75% of memory accesses can be saved using the prop-
sed techniques.]]>6512421942323431<![CDATA[A 53–67 GHz Low-Noise Mixer-First Receiver Front-End in 65-nm CMOS]]>2 of silicon area.]]>666205120634001<![CDATA[Bias-Compensated Least Squares Identification of Distributed Thermal Models for Many-Core Systems-on-Chip]]>619266326762344<![CDATA[Linearization Techniques for CMOS Low Noise Amplifiers: A Tutorial]]>58122361569<![CDATA[Error-Feedback Mismatch Error Shaping for High-Resolution Data Converters]]>664134213542862<![CDATA[A 1-MHz Relaxation Oscillator Core Employing a Self-Compensating Chopped Comparator Pair]]>2 and consuming around 160 μW while running at 1 MHz. Employing a self-compensating chopped comparator structure, the designed oscillator exhibits a significant improvement in the frequency stability and control linearity, at the same time retaining a fast start-up and having a minimal overhead in the power consumption and area. Measured on 8 test chips, the frequency variation against temperature is ±0.26% in the temperature range from -40 to 125 °C, and the line sensitivity is ±0.08 %/V with the supply voltage changing from 3.0 to 4.5 V. The typical distortion parameters of the control characteristic are HD_{2} = -61.7 dB and HD_{3} = -93.2 dB at △f_{osc} = 500 kHz. The measured jitter and phase noise at 10 kHz carrier offset are 235 ppm and -92 dBc/Hz, respectively, while the Allan deviation floor is 15 ppm.]]>665172817363173<![CDATA[Second-Order Trajectory Sensitivity Analysis of Hybrid Systems]]>665192219341332<![CDATA[An Architecture to Accelerate Convolution in Deep Neural Networks]]>2.]]>654134913623035<![CDATA[Kron Reduction of Graphs With Applications to Electrical Networks]]>6011501633757<![CDATA[Low-Power/Low-Voltage Integrated CMOS Sense Resistor-Free Analog Power/Current Sensor Compatible With High-Voltage Switching DC–DC Converter]]>2, and consumes a power of 0.748 mW.]]>666220822183166<![CDATA[Development of Single-Transistor-Control LDO Based on Flipped Voltage Follower for SoC]]>555139214012180<![CDATA[Analysis and Optimization of Direct-Conversion Receivers With 25% Duty-Cycle Current-Driven Passive Mixers]]>579235323662929<![CDATA[Memristor-Based Circuit Design for Multilayer Neural Networks]]>6526776862210<![CDATA[Analysis and Design of Voltage-Controlled Oscillator Based Analog-to-Digital Converter]]>2.]]>57118301424<![CDATA[High-Efficiency Wireless Power Transfer for Biomedical Implants by Optimal Resonant Load Transformation]]>6048678741382<![CDATA[Low-Pass Filtering SC-DAC for Reduced Jitter and Slewing Requirements on CTSDMs]]>664136913812633<![CDATA[Event-Triggered Control for Consensus Problem in Multi-Agent Systems With Quantized Relative State Measurements and External Disturbance]]>657223222423683<![CDATA[Variability-Aware Design Method for a Constant Inversion Level Bias Current Generator]]>2 and produces 11.4 nA on average, while all eight measured devices were inside ±2.1% of the average.]]>666202720362570<![CDATA[A 25–35 GHz Neutralized Continuous Class-F CMOS Power Amplifier for 5G Mobile Communications Achieving 26% Modulation PAE at 1.5 Gb/s and 46.4% Peak PAE]]>6628348473598<![CDATA[Design-oriented estimation of thermal noise in switched-capacitor circuits]]>521123582368672