<![CDATA[ IEEE Transactions on Circuits and Systems I: Regular Papers - Popular ]]>
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Popular Articles Alert for this Publication# 8919 2019April <![CDATA[The flipped voltage follower: a useful cell for low-voltage low-power circuit design]]>527127612911168<![CDATA[Understanding Phase Error and Jitter: Definitions, Implications, Simulations, and Measurement]]>6611191696<![CDATA[Consensus of Multiagent Systems and Synchronization of Complex Networks: A Unified Viewpoint]]>5712132241045<![CDATA[Efficient Hardware Architectures for Deep Convolutional Neural Network]]>656194119531975<![CDATA[Full On-Chip CMOS Low-Dropout Voltage Regulator]]>549187918901617<![CDATA[Noise Filtering and Linearization of Single-Ended Sampled-Data Circuits]]>664133113413317<![CDATA[Approximate Multipliers Based on New Approximate Compressors]]>6512416941824744<![CDATA[Switched-Capacitor/Switched-Inductor Structures for Getting Transformerless Hybrid DC–DC PWM Converters]]>5526876961294<![CDATA[Matching Properties of Femtofarad and Sub-Femtofarad MOM Capacitors]]>6367637721936<![CDATA[Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures]]>556144114541188<![CDATA[Second-Order Trajectory Sensitivity Analysis of Hybrid Systems]]>665192219341332<![CDATA[Consensus Tracking of Multi-Agent Systems With Lipschitz-Type Node Dynamics and Switching Topologies]]>6124995113732<![CDATA[A 10-Bit 200-kS/s 1.76-<inline-formula> <tex-math notation="LaTeX">$mu$ </tex-math></inline-formula>W SAR ADC With Hybrid CAP-MOS DAC for Energy-Limited Applications]]>2.]]>665171617273096<![CDATA[Wide-Bandwidth, High-Linearity, 2.8-GS/s, 10-bit Accurate Sample and Hold Amplifier in 130-nm SiGe BiCMOS]]>2 and consumes an average power of 1.26 W. The SHA is a pseudo-differential open-loop design that includes two cascaded track-and-hold amplifiers, a high-speed clock driver, and externally adjustable current mirror biases. The high-speed clock drivers and buffers add 170 mW to the total power consumption. The measurements of the fabricated SHA show a 10-bit effective resolution across the 1-GHz IF bandwidth and <; -61-dBc HD_{2} and HD_{3}.]]>665175817684788<![CDATA[A Study of Phase Noise and Frequency Error of a Fractional-N PLL in the Course of FMCW Chirp Generation]]>665167016802864<![CDATA[Implications of Passive Mixer Transparency for Impedance Matching and Noise Figure in Passive Mixer-First Receivers]]>571230923103559<![CDATA[Exploiting Machine Learning Against On-Chip Power Analysis Attacks: Tradeoffs and Design Considerations]]>6627697814010<![CDATA[Benefits of Using VCO-OTAs to Construct TIAs in Wideband Current-Mode Receivers Over Inverter-Based OTAs]]>665168116913411<![CDATA[Event-Triggered Control for Consensus Problem in Multi-Agent Systems With Quantized Relative State Measurements and External Disturbance]]>657223222423683<![CDATA[X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories]]>+T Differential cell. In addition, we also present a novel `read-compute-store' scheme, wherein the computed Boolean function can be directly stored in the memory without the need of latching the data and carrying out a subsequent write operation. The feasibility of the proposed schemes has been verified using the predictive transistor models and detailed Monte-Carlo variation analysis. As an illustration, we also present the efficacy of the proposed in-memory computations by implementing advanced encryption standard algorithm on a non-standard von-Neumann machine wherein the conventional SRAM is replaced by X-SRAM. Our simulations indicated that up to 75% of memory accesses can be saved using the prop-
sed techniques.]]>6512421942323431<![CDATA[Error-Feedback Mismatch Error Shaping for High-Resolution Data Converters]]>664134213542862<![CDATA[A 25–35 GHz Neutralized Continuous Class-F CMOS Power Amplifier for 5G Mobile Communications Achieving 26% Modulation PAE at 1.5 Gb/s and 46.4% Peak PAE]]>6628348473598<![CDATA[A frequency compensation scheme for LDO voltage regulators]]>51610411050576<![CDATA[A 1-MHz Relaxation Oscillator Core Employing a Self-Compensating Chopped Comparator Pair]]>2 and consuming around 160 μW while running at 1 MHz. Employing a self-compensating chopped comparator structure, the designed oscillator exhibits a significant improvement in the frequency stability and control linearity, at the same time retaining a fast start-up and having a minimal overhead in the power consumption and area. Measured on 8 test chips, the frequency variation against temperature is ±0.26% in the temperature range from -40 to 125 °C, and the line sensitivity is ±0.08 %/V with the supply voltage changing from 3.0 to 4.5 V. The typical distortion parameters of the control characteristic are HD_{2} = -61.7 dB and HD_{3} = -93.2 dB at △f_{osc} = 500 kHz. The measured jitter and phase noise at 10 kHz carrier offset are 235 ppm and -92 dBc/Hz, respectively, while the Allan deviation floor is 15 ppm.]]>665172817363173<![CDATA[Development of Single-Transistor-Control LDO Based on Flipped Voltage Follower for SoC]]>555139214012180<![CDATA[A CMOS V-Band PLL With a Harmonic Positive Feedback VCO Leveraging Operation in Triode Region for Phase-Noise Improvement]]>665181818304376<![CDATA[A Low-Power Deep Neural Network Online Learning Processor for Real-Time Object Tracking Application]]>2 DNN online learning processor shows 126 mW power consumption and the processor achieves 30.4 frames-per-second throughput in the object tracking application.]]>665179418042929<![CDATA[A Second-Order Bandpass <inline-formula> <tex-math notation="LaTeX">$DeltaSigma$ </tex-math></inline-formula> Time-to-Digital Converter With Negative Time-Mode Feedback]]>2.]]>664135513684929<![CDATA[Analysis and Design of Voltage-Controlled Oscillator Based Analog-to-Digital Converter]]>2.]]>57118301424<![CDATA[World’s Fastest FFT Architectures: Breaking the Barrier of 100 GS/s]]>664150715163399<![CDATA[Improving Receiver Close-In Blocker Tolerance by Baseband <inline-formula> <tex-math notation="LaTeX">$G_m-C$ </tex-math></inline-formula> Notch Filtering]]>6638858963427<![CDATA[Efficient FPGA Implementations of Pair and Triplet-Based STDP for Neuromorphic Architectures]]>664155815703404<![CDATA[A Two-Stage Fully Differential Inverter-Based Self-Biased CMOS Amplifier With High Efficiency]]>587159116031735<![CDATA[Design Methodology for Phase-Locked Loops Using Binary (Bang-Bang) Phase Detectors]]>647163716503613<![CDATA[Learning in Memristive Neural Network Architectures Using Analog Backpropagation Circuits]]>6627197324455<![CDATA[A Fully-Integrated Low-Dropout Regulator With Full-Spectrum Power Supply Rejection]]>2, including 140 pF of stacked on-chip capacitors.]]>6237077162674<![CDATA[A Novel Digital-Intensive Hybrid Polar-I/Q RF Transmitter Architecture]]>6512439044033773<![CDATA[New Mixed-Mode Design Methodology for High-Efficiency Outphasing Chireix Amplifiers]]>min and R_{max} and input RF gate drives yielding the best combination of efficiencies and output powers without needing to perform a load pull simulation or measurement. New analytic equations expressed only in terms of R_{min} and R_{max} are given for designing the Chireix combiner at the current source reference planes. Nonlinear embedding is then used to predict the incident power and multi-harmonic source and load impedances required at the package reference planes to physically implement the power amplifier (PA). An analytic formula solely expressed in terms of Rmin and Rmax is reported for the peak and backoff outphasing angles required at the PA input reference planes. A Chireix outphasing PA is designed using two 15-W GaN HEMTs. A Chireix outphasing PA exhibits a peak efficiency of 72.58% with peak power of 43.97 dBm and a 8-dB backoff efficiency of 75.22% at 1.9 GHz. Measurements with 10-MHz LTE signals with 9.6-dB PAPR yield 59.4% average drain efficiency at 1.9 GHz while satisfying the 3GPP linearity requirements.]]>664159416075351<![CDATA[A 0.9-/spl mu/A Quiescent Current Output-Capacitorless LDO Regulator With Adaptive Power Transistors in 65-nm CMOS]]>2 . The measured results have shown that the proposed circuit consumes a quiescent current of 0.9 μA at no load, regulating the output at 1 V from a voltage supply of 1.2 V. It achieves full range stability from 0 to 100 mA load current at a maximum 100 pF parasitic capacitance load. The measured transient output voltage is 68.8 mV when load current is stepped from 0 to 100 mA in 300 ns with C_{L} = 100 pF. The recovery time is about 6 μs. Compared to previously reported counterparts, the proposed OCL-LDO regulator shows a significant improvement in term of OCL-LDO transient figure-of-merit (FOM) as well as balanced performance parameters in terms of PSR, line regulation and load regulation.]]>604107210812451<![CDATA[Analysis and Design Considerations of Integrated 3-Level Buck Converters]]>6356716822000<![CDATA[A Novel Convolution Computing Paradigm Based on NOR Flash Array With High Computing Speed and Energy Efficiency]]>665169217035586<![CDATA[Kron Reduction of Graphs With Applications to Electrical Networks]]>6011501633757<![CDATA[The Circuit Theory Behind Coupled-Mode Magnetic Resonance-Based Wireless Power Transmission]]>Q) and large coupling distance. It simplifies the analysis by reducing the order of the differential equations by half compared to the circuit theory.]]>599206520742999<![CDATA[Analysis and Optimization of Direct-Conversion Receivers With 25% Duty-Cycle Current-Driven Passive Mixers]]>579235323662929<![CDATA[Design of Sparse FIR Filters With Reduced Effective Length]]>0-norm minimization problem. This original design problem is re-formulated by encoding the filter coefficients using a binary encoding vector, which represents the locations of the zero and non-zero filter coefficients. An iterative 0-1 exchange process with proper direction control is proposed to propel the minimax approximation error toward the specified upper bound of error for sparsity maximization. The effective length is optimized with a lower priority than sparsity in the proposed algorithm. Simulation results show that the proposed algorithm is superior to the existing algorithms in terms of both sparsity and/or effective length in most cases.]]>664149615061910<![CDATA[The Theory of Special Noise Invariants]]>Nmin and N, may be expressed in terms of such eigenvalues. In addition, we provide a complete characterization of the four noise parameters of two-port passive dissipative networks in terms of their gain parameters and derive the condition under which the invariant 4NT_{0}/T_{Nmin} of passive nonreciprocal networks is lower than two. We also extend the theory of special noise invariants to LNAs with lossy input matching network. Overall, the impact of the findings emerging from the theory is highlighted through theorems, remarks, circuit examples, and studies on widespread design methodologies.]]>664130513181193<![CDATA[Computing Timing Jitter From Phase Noise Spectra for Oscillators and Phase-Locked Loops With White and<tex>$1/f$</tex>Noise]]>53918691884773<![CDATA[Low-Pass Filtering SC-DAC for Reduced Jitter and Slewing Requirements on CTSDMs]]>664136913812633<![CDATA[Linearization Techniques for CMOS Low Noise Amplifiers: A Tutorial]]>58122361569<![CDATA[A Reconfigurable Streaming Deep Convolutional Neural Network Accelerator for Internet of Things]]>2. The accelerator can support major CNNs and achieve 152GOPS peak throughput and 434GOPS/W energy efficiency at 350 mW, making it a promising hardware accelerator for intelligent IoT devices.]]>6511982082922