<![CDATA[ IEEE Transactions on Circuits and Systems I: Regular Papers - Popular ]]>
http://ieeexplore.ieee.org
Popular Articles Alert for this Publication# 8919 2020April <![CDATA[Approximate Multipliers Based on New Approximate Compressors]]>6512416941824744<![CDATA[The flipped voltage follower: a useful cell for low-voltage low-power circuit design]]>527127612911168<![CDATA[Needle-Type Imager Sensor With Band-Pass Composite Emission Filter and Parallel Fiber-Coupled Laser Excitation]]>674108210912200<![CDATA[Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures]]>556144114541188<![CDATA[Full On-Chip CMOS Low-Dropout Voltage Regulator]]>549187918901617<![CDATA[Switched-Capacitor/Switched-Inductor Structures for Getting Transformerless Hybrid DC–DC PWM Converters]]>5526876961294<![CDATA[Analysis and Design of Regenerative Comparators for Low Offset and Noise]]>668281728303124<![CDATA[A Fully-Integrated Low-Dropout Regulator With Full-Spectrum Power Supply Rejection]]>2, including 140 pF of stacked on-chip capacitors.]]>6237077162674<![CDATA[Matching Properties of Femtofarad and Sub-Femtofarad MOM Capacitors]]>6367637721936<![CDATA[Implications of Passive Mixer Transparency for Impedance Matching and Noise Figure in Passive Mixer-First Receivers]]>571230923103559<![CDATA[A Low Voltage and Low Power 10-bit Non-Binary 2b/Cycle Time and Voltage Based SAR ADC]]>674113611485552<![CDATA[Optimized Design of N-Phase Passive Mixer-First Receivers in Wideband Operation]]>6211275927702893<![CDATA[Analysis and Optimization of Direct-Conversion Receivers With 25% Duty-Cycle Current-Driven Passive Mixers]]>579235323662929<![CDATA[Consensus of Multiagent Systems and Synchronization of Complex Networks: A Unified Viewpoint]]>5712132241045<![CDATA[On-Chip Solar Energy Harvester and PMU With Cold Start-Up and Regulated Output Voltage for Biomedical Applications]]>2 as energy transducer and a Power Management Unit (PMU) on the same silicon substrate, and an output voltage regulator. Both chips are implemented in standard 0.18 μm CMOS technology with total layout areas of 1.575 mm^{2} and 0.0126 mm^{2}, respectively. The system also contains an off-the-shelf 3.2 mm × 2.5 mm × 0.9 mm supercapacitor working as an off-chip battery or energy reservoir between the PMU and the voltage regulator. Experimental results show that the fast energy recovery of the on-chip solar cell and PMU permits the system to replenish the supercapacitor with enough charge as to sustain Bluetooth Low Energy (BLE) communications even with input light powers of 510 nW. The whole system is able to self-start-up without external mechanisms at 340 nW. This work is the first step towards a self-supplied sensor node with processing and communication capabilities. The small form factor and ultra-low power consumption of the system components is in compliance with biomedical applications requirements.]]>674110311143278<![CDATA[Linearization Techniques for CMOS Low Noise Amplifiers: A Tutorial]]>58122361569<![CDATA[A Power-Efficient CNN Accelerator With Similar Feature Skipping for Face Recognition in Mobile Devices]]>674118111934747<![CDATA[Jitter Minimization in Digital PLLs with Mid-Rise TDCs]]>b-bit midrise TDC case, the quantization noise can be further reduced at the cost of higher complexity and finer time resolution. The choice of N_{b} = 2 seems to be the best compromise between jitter reduction and complexity increase. Time-domain simulations assess the theoretical framework and demonstrate the validity of the assumptions made throughout the paper.]]>6737437523524<![CDATA[Noise Analysis for Comparator-Based Circuits]]>563541553854<![CDATA[Development of Single-Transistor-Control LDO Based on Flipped Voltage Follower for SoC]]>555139214012180<![CDATA[Low-Power All-Digital Multiphase DLL Design Using a Scalable Phase-to-Digital Converter]]>2 of active area and consumes 2.25mW at 2.5GHz input frequency with a 622.6MHz sample clock. The RMS jitter of the circuit is 1.2ps and 1.4ps for the DLL loop and the phase shifter loop, respectively. The RMS jitter is significantly reduced with the CS! based DLL to 0.86ps and the power consumption of 2.64mW at 4GHz input frequency with a 996.1MHz sample clock provides an improved power efficiency compared to the SC! based DLL. As a trade-off, the area is increased to 0.0085mm^{2} due to the use of a ΔΣ modulator and an analog low pass filter.]]>674115811682942<![CDATA[A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors]]>6611417241854557<![CDATA[Optimizing Weight Mapping and Data Flow for Convolutional Neural Networks on Processing-in-Memory Architectures]]>674133313436360<![CDATA[X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories]]>+T Differential cell. In addition, we also present a novel `read-compute-store' scheme, wherein the computed Boolean function can be directly stored in the memory without the need of latching the data and carrying out a subsequent write operation. The feasibility of the proposed schemes has been verified using the predictive transistor models and detailed Monte-Carlo variation analysis. As an illustration, we also present the efficacy of the proposed in-memory computations by implementing advanced encryption standard algorithm on a non-standard von-Neumann machine wherein the conventional SRAM is replaced by X-SRAM. Our simulations indicated that up to 75% of memory accesses can be saved using the prop-
sed techniques.]]>6512421942323431<![CDATA[Low 1/f<sup>3</sup> Noise Corner LC-VCO Design Using Flicker Noise Filtering Technique in 22nm FD-SOI]]>3 corner below 18 kHz and a figure-of-merit (FOM) at 1 MHz offset frequency of 188~190 dBc/Hz over the tuning range. Thanks to the flicker noise filtering technique, flicker noise upconversion can be suppressed significantly without degrading the phase noise (PN) in the 1/f^{2} region. The difference in connection of the switched-capacitor bank (SCB) over the VCO tuning range is taken into account in our analysis of flicker noise filtering. The VCO uses differential source degeneration with a self-coupled inductor that is used for layout compactness and common-mode (CM) resonance manipulation. To obtain a low 1/f^{3} corner over the tuning range, a common centroid layout technique is used for the SCB. The post-layout simulation shows that the 1/f^{3} corner is well below 50 kHz over the tuning range in different process corners. The PN@1 MHz and PN@100 kHz are −110.2 dBc/Hz and −89.9 dBc/Hz, respectively, at the center of the tuning range with a power consumption of 8.8 mW.]]>675146914804351<![CDATA[A Wide Dynamic Range Laser Radar Receiver Based on Input Pulse-Shaping Techniques]]>PP991127205<![CDATA[A High Efficiency Multi-Mode Outphasing RF Power Amplifier With 31.6 dBm Peak Output Power in 45nm CMOS]]>6738158284908<![CDATA[A 60-m Range 6.16-mW Laser-Power Linear-Mode LiDAR System With Multiplex ADC/TDC in 65-nm CMOS]]>6737537644715<![CDATA[A Full Ka-Band Power Amplifier With 32.9% PAE and 15.3-dBm Power in 65-nm CMOS]]>sat), and 12.9-dBm output 1-dB compression point (P1 dB). The fractional bandwidth of the PA is 63.3% from 21.6 to 41.6 GHz, which covers the full Ka-band (26.5 to 40 GHz).]]>659265726683024<![CDATA[Design of D-Band Transformer-Based Gain-Boosting Class-AB Power Amplifiers in Silicon Technologies]]>$G_{max}$ , saturation power $P_{sat}$ , drain efficiency DE and power-added efficiency PAE) is studied for different silicon technologies after properly sizing the PA transistors to reach an optimum load resistance $R_{opt}$ . The inductive gain-boosting PA is explored and compared with the capacitive gain-boosting one in SiGe BiCMOS to achieve an even higher $P_{sat}$ while maintaining a high $G_{max}$ . Finally, A D-band 4-stage capacitive gain-boosting PA is fabricated in a 28 nm bulk CMOS process as a reference to verify the design methodology and simulation results, and its detailed design considerations are described. This prototyped D-band PA achieved the state-of-the-art results: a 22.5 dB $G_{p}$ , 6.6 % PAE, 8 dBm $P_{sat}$ an-
81.1 FoM with only 0.0265 mm^{2} core area.]]>675144714588558<![CDATA[Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial]]>5913291561<![CDATA[Bio-Inspired Imprecise Computational Blocks for Efficient VLSI Implementation of Soft-Computing Applications]]>5748508624056<![CDATA[Computing Timing Jitter From Phase Noise Spectra for Oscillators and Phase-Locked Loops With White and<tex>$1/f$</tex>Noise]]>53918691884773<![CDATA[A frequency compensation scheme for LDO voltage regulators]]>51610411050576<![CDATA[A Novel Digital-Intensive Hybrid Polar-I/Q RF Transmitter Architecture]]>6512439044033773<![CDATA[Statistical BER Analysis of Wireline Links With Non-Binary Linear Block Codes Subject to DFE Error Propagation]]>-15 reasonable. Error bounds associated with each method are found. The efficiency of the proposed model allows it to handle a larger state space, more DFE taps, and more sophisticated linear block codes than prior work. A 4-PAM 60 Gb/s wireline transceiver fabricated in a 7 nm FinFET technology is used as a test vehicle to validate this model. Measured data with two different channels reveals that the statistical model can properly predict the post-FEC error floor with standard FEC codes. While this paper demonstrates the method for capturing DFE error propagation, the method is general and can be applied to model other communication systems having memory effects. Moreover, our proposed model can be easily extended to higher-level PAM schemes and other advanced equalizer architectures to assist in making architectural choices for wireline transceivers.]]>6712842972872<![CDATA[The Circuit Theory Behind Coupled-Mode Magnetic Resonance-Based Wireless Power Transmission]]>Q) and large coupling distance. It simplifies the analysis by reducing the order of the differential equations by half compared to the circuit theory.]]>599206520742999<![CDATA[A Universal Method of Linear Approximation With Controllable Error for the Efficient Implementation of Transcendental Functions]]>6711771882254<![CDATA[Analysis of Wandering Spur Patterns in a Fractional-<inline-formula> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> Frequency Synthesizer With a MASH-Based Divider Controller]]>6737297428884<![CDATA[An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with −55 dBc Fractional and −91 dBc Reference Spurs]]>2.]]>6511375637684910<![CDATA[A 77-GHz Mixed-Mode FMCW Generator Based on a Vernier TDC With Dual Rising-Edge Fractional-Phase Detector]]>67160734470<![CDATA[A 12-Bit 100-MS/s Pipelined-SAR ADC With PVT-Insensitive and Gain-Folding Dynamic Amplifier]]>PP991102626<![CDATA[CORDIC-Based Architecture for Computing Nth Root and Its Implementation]]>-7 for the relative error. The design is modeled using Verilog HDL and synthesized under the TSMC 40-nm CMOS technology. The report shows a maximum frequency of 2.083 GHz with 197421.00 μm^{2} area. The area decreases to 169689.98 μm^{2} when the frequency lowers to 1.00 GHz.]]>6512418341952623<![CDATA[Analysis of Phase Noise in Phase/Frequency Detectors]]>6035295392481<![CDATA[Nano-Ampere Low-Dropout Regulator Designs for IoT Devices]]>6511401740265307<![CDATA[Sigma-Delta Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey]]>5811211691<![CDATA[A New Design Technique for Sub-Nanosecond Delay and 200 V/ns Power Supply Slew-Tolerant Floating Voltage Level Shifters for GaN SMPS]]>663128012902841<![CDATA[Utilization of Multi-Resonant Defected Ground Structure Resonators in the Oscillator Feedback for Phase Noise Reduction of K-Band VCOs in 0.18-<inline-formula> <tex-math notation="LaTeX">$mu$ </tex-math></inline-formula>m CMOS Technology]]>674111511253502<![CDATA[A 40-Gb/s PAM-4 Transmitter Using a 0.16-pJ/bit SST-CML-Hybrid (SCH) Output Driver and a Hybrid-Path 3-Tap FFE Scheme in 28-nm CMOS]]>2. Operating at 40 Gb/s and at a 0.9-V supply, the TX dissipates 19.5 mW, of which 6.4 mW is due to the SCH driver. The corresponding energy efficiencies are 0.16 and 0.5 pJ/bit for the SCH driver and TX, respectively; both compare favorably with the prior art.]]>6612485048612823<![CDATA[Wideband Inductorless Low-Power LNAs with G<sub><italic>m</italic></sub> Enhancement and Noise-Cancellation]]>2.]]>65126383641