<![CDATA[ IEEE Transactions on Circuits and Systems - Popular ]]>
http://ieeexplore.ieee.org
Popular Articles Alert for this Publication# 31 2019April <![CDATA[Cellular neural networks: theory]]>>]]>3510125712721201<![CDATA[Idealized operation of the class E tuned power amplifier]]>Qassumption. These equations are then used to determine component values for optimum operation at an efficiency of 100 percent. Other combinations of component values and duty cycles which result in 100-percent efficiency are also determined. The harmonic structure of the collector voltage waveform is analyzed and related amplifier configurations are discussed. While this analysis is directed toward the design of high-efficiency power amplifiers, it also provides insight into the operation of modern solid-state VHF-UHF tuned power amplifiers.]]>24127257351037<![CDATA[Cellular neural networks: applications]]>3510127312902924<![CDATA[Power supply rejection ratio in operational transconductance
amplifiers]]>37910771084708<![CDATA[The modified nodal approach to network analysis]]>226504509760<![CDATA[Transformation between Foster and Cauer equivalent networks]]>T-matrices transforming Foster-lI to equivalent Cauer structures are derived. The results are given in a recursive form column-by-column, starting from the first.]]>254238239191<![CDATA[<e1>z</e1>-domain model for discrete-time PLL's]]>s-domain model for continuous-time
phase-locked loops (PLLs) is a fundamental tool for the linearized
analysis of these systems. For PLLs with digital inputs and outputs,
however, a discrete-time z-domain model more accurately
describes loop behavior. In this study, a methodology is described for
obtaining an accurate z-domain description of a discrete-time
PLL. The modeling technique transforms portions of the s-domain
PLL model directly into the z-domain, requiring only
straightforward algebraic manipulations even for complex loop filters.
This methodology is demonstrated for a simple loop filter, and
measurements from the digital signaling interface integrated circuit are
used to compare s-domain, z-domain, and time-step
analysis results for a more complicated loop filter. The
z-domain model, although only incrementally more complicated
than the s-domain model, is shown to be more accurate,
especially at higher jitter frequencies]]>351113931400568<![CDATA[Simple 'neural' optimization networks: An A/D converter, signal decision circuit, and a linear programming circuit]]>3355335411064<![CDATA[Neural networks for nonlinear programming]]>355554562680<![CDATA[Exact analysis of class E tuned power amplifier at any Q and switch duty cycle]]>Qor the minimum possible value ofQ. This paper presents an exact analysis of the Class E amplifier at anyQand any switch duty cycleD, along with experimental results. The basic equations governing the amplifier operation are derived analytically using Laplace-transform techniques and assuming a constant current through the dc-fed choke. The following performance parameters are determined for optimum operation: the current and voltage waveforms, the peak collector current and collector-emitter voltage, the output power, the power-output capability, the load-network component values, and the spectrum of the output voltage. It is shown that all parameters of the amplifier are functions ofQ. Therefore, the high-Qassumption used in previous analyses leads to considerable errors. For example, forQ < 7atD = 0.5, some errors are up to 60 percent. The results can be used for designing Class E stages at anyQand switch duty cycleD. The measured performance shows excellent agreement with the design calculations. The collector efficiency was over 96 percent at 2 MHz for all tested values ofQfrom 0.1 to 10.]]>342149159934<![CDATA[Kronecker products and matrix calculus in system theory]]>2597727811024<![CDATA[A new algorithm in spectral analysis and band-limited extrapolation]]>f (t)is given, then its Fourier spectrumF(omega)is estimated either as the transform of the product off(t)with a time-limited windoww(t), or by certain techniques based on various a priori assumptions. In the following, a new algorithm is proposed for computing the transform of a band-limited function. The algorithm is a simple iteration involving only the fast Fourier transform (FFT). The effect of noise and the error due to aliasing are determined and it is shown that they can be controlled by early termination of the iteration. The proposed method can also be used to extrapolate bandlimited functions.]]>229735742680<![CDATA[Fading memory and the problem of approximating nonlinear operators with Volterra series]]>3211115011611352<![CDATA[An efficient method for computer aided noise analysis of linear amplifier networks]]>234235238512<![CDATA[Narrow-band multiple-coupled cavity synthesis]]>215649655680<![CDATA[Design of linear CMOS transconductance elements]]>3110891894488<![CDATA[Noise analysis of switched capacitor networks]]>z-transform transfer function. These results are applied to the SC integrator and excellent concordance to the measurements made on a laboratory model is established.]]>3013743799<![CDATA[The double scroll]]>3287978182960<![CDATA[A higher order topology for interpolative modulators for
oversampling A/D converters]]>373309318800<![CDATA[CMOS voltage to current transducers]]>321110971104824<![CDATA[An adaptive filter for noise cancelling]]>351012011209660<![CDATA[Matrix representations for sorting and the fast Fourier transform]]>T_{N}. The Kronecker product notation and the ideal shuffle baserpermutation operator form the basis for a unifying theory through which the various versions of the FFT can be viewed. The properties of the ideal shuffle baserpermutation operator are used to arrive at FFT versions with such desirable properties as in-place computation or identical geometry from stage to stage. The FFT versions previously described in the literature are derived here. At the same time, algorithms for the sorting of FFT data in digit-reversed order are generated. These are explored and new sorting versions amenable to hardware implementation with sequential memory are presented. As an example of how the unifying theory is used, a number of FFT versions with identical geometry from stage to stage are derived. The hardware necessary for these algorithms is described for the base 4 case withN = 1024data points.]]>211109116910<![CDATA[The double scroll family]]>R^3. Using this approach, we were able to prove that the chaotic dynamics of the double scroll is quite common, and is robust because the associated horseshoes predicted from Shilnikov's theorem are structurally stable. In fact, it is exhibited by a large family (in fact, infinitely many linearlyequivalent circuits) of vector fields whose associated piecewise-linear differential equations bear no resemblance to each other. It is therefore remarkabl-
that the normalized eigenvalues, which is a local concept, completely determine the system's global qualitative behavior.]]>3311107211185074<![CDATA[Frequency-response masking approach for the synthesis of sharp linear phase digital filters]]>Mdelay elements, an(M + 1)-band filter is produced. The transition-width of this(M + 1)-band filter is1/Mthat of the prototype low-pass filter. A complementary filter can be obtained by subtracting the output of the(M + 1)-band filter from a suitably delayed version of the input. The complementary filter is an(M + 1)-band filter whose passbands and stopbands are the stopbands and passbands, respectively, of the original(M + 1)-band filter. If the frequency responses of the original( M + 1)-band filter and its complementary filter are properly masked and recombined, narrow transition-band filter can be obtained. This technique can be used to design sharp low-pass, high-pass, bandpass, and bandstop filters with arbitrary passband bandwidth.]]>334357364811<![CDATA[Analysis of periodically switched linear circuits]]>hat{H}(f, t)and the impulse responseh(t,tau)are derived. These results are most suitable for computer aided design. Applications to switched filters and modulators are given.]]>24105315411050<![CDATA[Improved circuits for the realization of switched-capacitor filters]]>274237244752<![CDATA[Considerations for fast settling operational amplifiers]]>373326334708<![CDATA[An improved Wien bridge oscillator]]>RC-active Wien-bridge oscillator is proposed
whose oscillation frequency is independent of the time constants of the
op amps used in the design and is determined only by passive components.
Other important effects such as the influence of parasitic poles and
nonlinearities in the stability of the system are also analyzed.
Experimental results are given, showing close agreement with theoretical
predictions]]>374543546304<![CDATA[A piecewise harmonic balance technique for determination of periodic response of nonlinear systems]]>2328591720<![CDATA[Indeterminacy and identifiability of blind identification]]>385499509896<![CDATA[Start-up time of CMOS oscillators]]>3432592681016<![CDATA[An improved correlated double sampling circuit for low noise charge
coupled devices]]>371215591565504<![CDATA[Device modeling via nonlinear circuit elements]]>2711101410443792<![CDATA[Subharmonics and chaos in a controlled switched-mode power
converter]]>35810591061300<![CDATA[An adaptive weighted median filter for speckle suppression in medical ultrasonic images]]>>]]>361129135836<![CDATA[The Hopf bifurcation theorem and its applications to nonlinear oscillations in circuits and systems]]>2642352542376<![CDATA[Solid-state power conversion: A Fourier analysis approach to generalized transformer synthesis]]>2843193301184<![CDATA[Fast algorithm and implementation of 2-D discrete cosine transform
]]>N×N DCT, where N=2^{m}, can be
computed using only N 1-D DCTs and additions, instead of using
2N 1-D DCTs as in the conventional row-column approach. Hence
the total number of multiplications for the proposed algorithm is only
half of that required for the row-column approach and is also less than
that of most of other fast algorithms, whereas the number of additions
is almost comparable to that of others. It is also shown that only N
/2 1-D DCT module are required for hardware parallel implementation
of the proposed algorithm. Thus the number of actual multipliers being
used is only a quarter of that required for the conventional approach
]]>383297305716<![CDATA[Design of computationally efficient interpolated FIR filters]]>H(Z)=F(z^{L})G(
z) is studied. Both single-stage and multistage implementations
of G(z) are considered. Optimal decompositions
requiring fewest number if multipliers are given for some representative
low-pass cases. An efficient algorithm for designing these filters is
described. It is based on iteratively designing F(z^{L}) and G(z) using the Remez
multiple-exchange algorithm until the difference between the successive
stages is within the given tolerance limits. A novel implementation for
G(z) based on the use of recursive running sums is
given. The design of this class of filters is converted into another
design problem to which the Remez algorithm is directly applicable. The
results show that the proposed methods result in significant
improvements over conventional multiplier efficient implementations of
FIR digital filters]]>35170881536<![CDATA[Generalized Image Restoration by the Method of Alternating Orthogonal Projections]]>fis a vector known a priori to belong to a linear subspace{cal P}_bof a parent Hilbert space{cal H}(, but all that is available to the observer is its imageP_{a} f, the projection offonto a known linear subspace{cal P}_a(also incal H). 1) Find necessary and sufficient conditions under whichfis uniquely determined byP_{a} fand 2) find necessary and sufficient conditions for the stable linear reconstruction offfromP_{a} fin the face of noise. (In the later case, the reconstruction problem is said to be completely posed.) The answers torn out to be remarkably simple. a)fis uniquely determined by{cal P}_{a}iff{cal P}_{b}and the orthogonal complement of{ cal P}_{a}have only the zero vector in common. b) The reconstruction problem is completely posed iff the angle between{cal P}_{b}and the orthogonal complement of{cal P}_{a}, is greater than zero. (All angles lie in the first quadrant.) c) In the absence of noise, there exists in both cases a) and b) an effective recursive algorithm for the recovery offemploying only the operations of projection onto{cal P}_{b}and projection onto the orthogonal complement of{cal P}_{a}These operations define the necessary instrumentation.]]>259694702994<![CDATA[Adaptive algorithms with an automatic gain control feature]]>351122127496<![CDATA[Class-E zero-voltage-switching and zero-current-switching
rectifiers]]>dv/dt),
zero-current-switching (low di/dt), and mixed-mode
rectifiers are introduced and verified experimentally. The rectifiers
are derived from conventional rectifiers by adding reactive components.
New conventional rectifiers are also introduced and presented in a
systematic manner. The principle of class-E rectifier operation is
explained using current and voltage waveforms. The class-E rectifiers
offer a means of rectification suitable for high-frequency applications,
e.g. in resonant DC/DC power converters. A general approach to the
synthesis of resonant DC/DC converters is presented]]>373436444796<![CDATA[Topological generation and analysis of voltage multiplier circuits]]>upsilon_i(t)= E sin omega tinto a dc output voltageV_{out} = nE, wheren geq 2. This paper investigates the topological properties of voltage multiplier circuits and presents a unified approach for generating new voltage-multiplier circuit structures. In particular, an algorithm is presented for generatingn-fold voltage multipliers withncapacitors andndiodes. A theorem is presented for finding the dc capacitor voltages by inspection when no load current is drawn. For the case with load, explicit formulas for the output de voltage and the output resistance are given. Using the algorithm developed in this paper, three new voltage quadrupler circuits are generated and shown to have an output resistance only one-half of the conventional ladder quadrupler circuit.]]>24105175301535<![CDATA[On charge injection in analog MOS switches and dummy switch
compensation techniques]]>RC model of the conductive channel has
been used and verified in different switch configurations, including
variable input voltages. Special emphasis is laid on the feasibility and
limits of charge cancellation techniques using dummy switch
designs]]>372256264704<![CDATA[A parasitic-insensitive area-efficient approach to realizing very
large time constants in switched-capacitor circuits]]>36912101216556<![CDATA[A sigma-delta modulator as an A/D converter]]>257510514568<![CDATA[Nonlinear circuits]]>31169872632<![CDATA[A calculus for computing Filippov's differential inclusion with application to the variable structure control of robot manipulators]]>34173821024<![CDATA[A structure preserving energy function for power system transient stability analysis]]>PQbus. Flux decay of the generator field winding is included. The original network topology is maintained explicitly. An energy function is proposed which differs from the traditional one in that it includes additional terms corresponding to the energy stored in the loads and field winding. A characterization of the stability region is derived based on this energy function.]]>321010411049879<![CDATA[Center weighted median filters and their applications to image
enhancement]]>389984993888