Lowest variability SOI FinFETs having multiple Vt by back-biasing

FinFETs with an amorphous metal gate (MG) are fabricated on silicon-on-thin-buried-oxide (SOTB) wafers for realizing both low variability and tunable threshold voltage (V
_t
) necessary for multiple V
_t
solution. The FinFETs with an amorphous TaSiN MG record the lowest on-state drain current (I
_on
) variability (0.37 %μm) in comparison to bulk and SOI planar MOSFETs thanks to the suppressed variability of V
_t
(A
_Vt
=1.32 mVμm), drain induced barrier lowering (DIBL) and trans-conductance (G
_m
). Back-biasing through the SOTB provides excellent V
_t
controllability keeping the low V
_t
variability in contrast to V
_t
tuning by fin channel doping.