Low-Noise Power-Amplifier MMICs for the WR4.3 and WR3.4 Bands in a 35-nm Gate-Length InGaAs mHEMT Technology

This letter presents two distributed low-noise power-amplifier (LNPA) monolithic microwave integrated circuits (MMICs). The two amplifiers (DA1 and DA2) target the WR4.3 (170–260 GHz) and WR3.4 bands (220–330 GHz) as a minimum operating bandwidth (BW). The MMICs are realized in the Fraunhofer IAF 35-nm InGaAs mHEMT technology. Both amplifiers yield a small-signal gain of more than 20 dB from 110 GHz up to the corresponding upper band edges (265 and 335 GHz) and an average noise figure (NF) of 4.5 dB (110–216 GHz). Furthermore, DA1 delivers a saturated output power (<inline-formula> <tex-math notation="LaTeX">${P}_{\mathrm{ sat}}$ </tex-math></inline-formula>) of 12.4–15.2 dBm with a power-added efficiency (PAE) of 3.4%–6.2% (160–255 GHz). DA2 exhibits a <inline-formula> <tex-math notation="LaTeX">${P}_{\mathrm{ sat}}$ </tex-math></inline-formula> of 10–14.5 dBm (210–335 GHz). To the best of the authors’ knowledge, DA1 and DA2 present the best NF and <inline-formula> <tex-math notation="LaTeX">${P}_{\mathrm{ sat}}$ </tex-math></inline-formula> over the full WR4.3 and WR3.4 bands, respectively.


I. INTRODUCTION
A S DESCRIBED by the Bode-Fano criterion, reactively matched low-noise amplifiers (LNAs) as well as power amplifiers (PAs) face a similar trade-off between bandwidth (BW) and noise figure (NF) or output power (P out ).Nevertheless, several applications in radio astronomy, radar, wireless communication, or measurement and sensing equipment require cutting-edge performance over entire waveguide (WG) bands.Applications, such as the generation of complex modulated signals, where a combination of a low NF and a high P out is requested, are even more challenging and tend to describe a contradiction.Distributed amplifiers (DAs) are not limited by the Bode-Fano criterion.Though, DAs are commonly not known for a good NF or P out .However, recent work has shown [1], [2] that especially in the upper millimeter-wave (mmW) and sub-mmW frequency range, DAs can compete with the performance of dedicated LNAs or PAs, while instantaneously providing large BWs.Moreover, recent results insinuate that DAs can achieve equally good NF and P out performance on a single monolithic microwave integrated circuit (MMIC).However, this has been rarely demonstrated.[3] demonstrate a 170-260-GHz LNA with an NF on module level in the range of 4.9-5.6 dB (160-220 GHz).However, module data are difficult to compare with MMIC level data.In the WR3.4 band, [4] reports on an LNA MMIC with an NF of 5-8 dB.In both cases, P out is not reported.A PA covering a full WG band is reported in [1] with 10-14.9dBm from 75 to 305-GHz.Hamada et al. [5] demonstrate a P out of 3.5-6.3dBm over the WR3.4 band.The NF is in both cases not reported.
This work presents two low-noise power-amplifier (LNPA) MMICs targeting a minimum operating frequency of the full WR4.3 and WR3.4 WG bands, respectively.If possible, an operating BW in excess of the official band definitions is aimed for.The main design goal is to provide, simultaneously, an optimum NF and P out and to demonstrate state-of-theart performance for both parameters.Section II summarizes the used 35-nm InGaAs metamorphic high-electron-mobility transistor (mHEMT) technology and describes the MMIC design.Section III presents the on-wafer measurement results.

II. DISTRIBUTED LNPA MMICS
The presented MMICs [Fig.1(a) and (b)] are fabricated in our in-house 35-nm gate-length InGaAs mHEMT technology.The front-end-of-line (FEOL) and back-end-of-line (BEOL) processes are described in detail in [6] and [7], respectively.The high-electron-mobility transistors (HEMTs) exhibit an extrinsic maximum transition frequency ( f T ) and a maximum-oscillation frequency ( f max ) of above 500 and 1000 GHz, respectively.The BEOL includes three interconnection metal layers (MET1 to MET3).Besides the more traditional grounded coplanar WG or microstrip lines with a signal guidance mainly in the GaAs substrate, the other possibilities make use of the polymer layers on top of the GaAs substrate.Thus, several thin-film microstrip lines (TFMSLs) or elevated coplanar WGs (eCPWs) are possible.
Both MMICs share the same design approach and comprise DA cores.The amplifiers consist of two different, subsequent cores and have two branches in parallel.Block diagrams of the bottom branch of the mirror-symmetric circuits are depicted as overlays in Fig. 1

(a) and (b).
The first core (Core 1 ) targets an optimum NF.Moreover, the gain and the large-signal (LS) performance should be good enough to drive the second core (Core 2 ) into saturation.The main design goal of Core 2 is to provide a maximum P out .The actual design of the cores is based on design strategies that are discussed in [2], [7] and are adopted to the individual needs of the WR4.3 (DA 1 ) and WR3.4 amplifier (DA 2 ).
Core 1 follows primarily a standards traveling-wave amplifier (TWA) architecture where the cells are dc coupled to the gate line, and each cell contains an RF cascode.The used total gate width (TGW) and the number of cells per core are the most important design parameters.It is known from [7] that the NF at the upper part of the band of a DA is better for fewer cells, as long as the gain of Core 1 is high enough to sufficiently suppress the noise contribution of the second stage.Thus, Core 1 targets a transducer gain (G t ) of 10 dB.The gain of a DA is mainly defined by the absolute transconductance of the used transistor or cell and the number of cells.This, in combination with the assumption that a fewer number of cells results in a better high-frequency NF, means that TGW per cell should be as large as possible, so that the fewest number of cells per core enables a gain of 10 dB.Following this guideline, Core 1 of DA 1 and DA 2 uses 2 × 13 and 2 × 10 µm transistors, respectively.Here, it is primarily the required BW and the input capacitance (C in ) of the cell that limits TGW.To achieve 10 dB of gain, Core 1 of DA 1 and DA 2 uses four and six cells, respectively.The transistors in Core 1 are biased for optimum noise.Thus, the drain current (I d ) is 300 mA/mm, and the drain-source voltage (V ds ) per HEMT is 0.7 V, resulting a total supply voltage of 1.4 V.
The transmission line (TL) between the two transistors of an RF cascode and the gate-termination capacitor of the commongate (CG) transistor are designed, so that a maximum gain is achieved, while ensuring a stable operation.This part is the results of heavy EM simulations, since the description of compact models is not sufficient for the required level of complexity.The TL is realized in TFMSL1 (MET2 over MET1).Fig. 1(c) illustrates simplified schematics of Core 1 and the corresponding cells of DA 1 and DA 2 .The TLs of the gate and drain line are designed, so that matching and synchronism of the artificial TLs (ATLs) are achieved over the required BW.The drain bias is supplied with a quarter-wave (QW) stub, which is connected in the center of the drain ATL.The drain stub uses a high-impedance TL and is designed for the center of the corresponding WG band.Except the connection between common-source (CS) and CG HEMTs, all TLs of Core 1 are realized with TFMSL2 (MET3 over MET1), which provides the best trade-off between a compact layout and low losses.Core 1 of DA 1 is designed for a 50-input and output impedance.Since the impedance of an ATL decreases close to the Bragg frequency, a T-network with an open stub is used at the input and output of Core 1 to improve the match in the upper part of the intended band.For two reasons, Core 1 of DA 2 is designed for a 25-input impedance.First, it allows to design Core 1 of DA 2 up to 350 GHz.This is beneficial to ensure enough drive power for Core 2 at the upper band edge without having an early power roll-off.Second, it improves the input matching over the entire WG band.The output of Core 1 of DA 2 is designed for a 40-environment.It improves the output matching and reduces the effort in the matching between Core 1 and Core 2 of DA 2 .
Core 2 is designed for a maximum P out .Thus, the design aims for a large TGW and a maximum number of cells.For symmetry and, thus, transistor performance reasons, Core 2 uses two-finger HEMTs.TGW is chosen, so that the operating frequency range is in the maximum-stable gain (MSG) region to avoid a gain drop at the upper band edge.Thus, TGW in Core 2 of DA 1 and DA 2 is 2 × 20 and 2 × 15 µm, respectively.The corresponding C in is too large to match the resulting ATL up to the upper band edge.Thus, C in of the cells is reduced by capacitive voltage division with a 25-fF series capacitor at the gate of the CS HEMT.The number of cells is set to eight, since a further increase predicts no improvement of P out .Simplified schematics of Core 2 and the cells are depicted in Fig. 1(d).Even with the capacitive voltage division at the input of the cells, the input and output impedance of Core 2 is reduced to 25 to achieve the BW.The bias of Core 2 is I d = 300 mA/mm and V ds = 1 V per HEMT.Thus, the total supply voltage is 2 V. Except the drain bias stub, all TLs of Core 2 are realized in TFMSL2.The drain stub uses an eCPW (MET3: signal and MET1: GND), since the The last design part is dedicated to the 1:2 power splitter/combiner at the input and output of the MMICs and the intercore connections.These networks serve two needs; first, an impedance transformation and, second, the signal routing simply from a layout point of view.For the impedance transformation, Table II summarizes the input and output impedance of the core circuits.The impedance at the common node of the splitter/combiner is 100 for each branch.Thus, the combiners at the output of DA 1 and DA 2 and the input of DA 2 appear to be the most demanding (4-to-1) impedance transformation step.For DA 1 , the networks before and after each core are realized as QW transformers (QWTs).The length is also needed to connect the individual parts.The dissipated loss of TLs at these high frequencies does not make, e.g., multisection transformers beneficial.The impedance of the TLs is a result of the corresponding impedance at the input and output of the QWTs.Fig. 1(a) shows the impedance and the center frequency of the QWTs.The network between Core 1 and Core 2 is as well a QWT.The length is needed to route the dc lines from the center of the MMIC to the top side where the dc pads are located.The dc lines of all cores are wired to the center (symmetry plane) to achieve a fully symmetric MMIC layout, including RF and dc networks.This is done to prevent any possible odd-mode stability issues due to a slightly different layout of the top and bottom branch.The input and output combiners utilize TFMSL2.The QWT between Core 1 and Core 2 is designed in TFMSL3, using MET2 as ground plane, so that the dc line can be routed in MET1, shielded from the RF circuitry.The networks of DA 2 are realized in a very similar way.A major difference is the input and output combiner, which requires, for layout reasons, a longer TL than λ/4.Thus, two-section non-QWTs are used.The design parameters are indicated in Fig. 1(b).In addition, Fig. 1(e) exemplifies the schematic of an entire MMIC-here, DA 2 .

III. MEASUREMENT RESULTS
For all on-wafer measurements, the MMICs are biased with-Core 1 : V d1 = 1.4 V, I d1,q = 300 mA/mm and Core 2 : V d2 = 2 V, I d2,q = 300 mA/mm.Consequently, the quiescent dc power of DA 1 and DA 2 is 471 and 389 mW, respectively.The S-parameters are measured from 0.01 to 220 GHz by an Anritsu vector network analyzer (VNA) setup and, from 200 to 335 GHz, by a Keysight PNA-X setup using VDI WR3.4 WG extenders.The S-parameters of DA 1 and DA 2 are shown in Fig. 2 over the entire measured frequency range and in Fig. 3 zoomed into the corresponding WG band.Both amplifiers achieve an S 21 of more than 20 dB beginning at the D-band (110-170 GHz) frequencies up to the intended WG band.In the WR4.3 and WR3.4 bands, DA 1 and DA 2 exhibit an S 21 of 20.6-23.6 and 20-24.4dB, respectively.
The NF is measured from 67 to 216 GHz in the W-, D-, and WR5.1 bands using ELVA-1 and VDI (WR5.1 band) WG noise sources.For higher frequencies, no commercial WG noise source is available.At the output of the DUT, the test signal is converted to an IF of 53 MHz by commercial mixer   modules and measured by a Keysight NF analyzer.The NFs are shown together with the S-parameters in Figs. 2 and 3.The NF of DA 1 and DA 2 over the entire measured band is within 3.8-5.7 and 3.6-6 dB, respectively.Above 110 GHz, the average NF is 4.5 dB for both amplifiers.At the upper band edges, the predicted NFs of DA 1 and DA 2 are still below 6.5 and 7.5 dB.
The CW LS performance is measured using a Keysight PNA-X and WR4.3 and WR3.4 VDI WG extenders as signal sources.P out is measured by a VDI Erickson PM5B power meter.For the measurements, diced MMICs are glued on a metal carrier with silver-filled epoxy.The LS performance of DA 1 is shown in Fig. 4 and exhibits a saturated P out (P sat ) of 12.4-15.2dBm.The power-added efficiency (PAE) is 3.4%-6.2%.In the WR3.4 band, the test port power is not sufficient to drive DA 2 into saturation.Thus, a second DA 2 MMIC is placed in front of the DUT DA 2 and connected with wire bonds.DA 2 yields a P sat of 10-14.5 dBm in (Fig. 5).IV.CONCLUSION This letter presents two distributed LNPA MMICs, fabricated in a 35-nm InGaAs mHEMT technology.DA 1 and DA 2 obtain an S 21 in excess of 20 dB starting at 110 GHz up to the band edges at 265 and 335 GHz, respectively.The measured average NF is 4.5 dB (110-216 GHz) for both MMICs.DA 1 exhibits a P sat of 12.4-15.2dBm with a corresponding PAE of 3.4%-6.2%for WR4.3 frequencies.DA 2 yields a P sat of 10-14.5 dBm from 210 to 335 GHz.Thus, both MMICs demonstrate state-of-the-art results and set a new milestone for full waveguide band performance in the WR4.3 and WR3.4 bands.

Fig. 1 .
Fig. 1.Chip photograph of the fabricated (a) DA 1 and (b) DA 2 MMIC with a chip size of 1.5 × 0.75 mm.The overlays illustrated block diagrams of the bottom half of the full MMICs.Simplified schematics of (c) Core 1 and (d) Core 2 and the corresponding cells of DA 1 and DA 2 .(e) Full schematic of DA 2 .

Fig. 2 .
Fig. 2. Measured and simulated S-parameters and NF of (a) DA 1 and (b) DA 2 over the full band.Closed and open symbols indicate measurements with the WG and VectorStar VNA setup, respectively.

Fig. 3 .
Fig. 3. Measured and simulated S-parameters and NF of (a) DA 1 and (b) DA 2 over the WR4.3 and WR3.4 bands, respectively.Closed and open symbols indicate measurements with the WG and VectorStar VNA setup, respectively.

TABLE I STATE
-OF-THE-ART FULL WG-BAND MMICS Reports on amplifier MMICs with an operating BW of a full WR4.3 (170-260 GHz) or WR3.4 (220-330 GHz) WG band are very limited in the open literature.Table I summarizes results for state-of-the-art LNAs and PAs.Varonen et al.

TABLE II INPUT
AND OUTPUT IMPEDANCE OF THE CORE CIRCUITSTFMSLs do not provide a 70-TL that can sustain the maximum I d .