A 7–115-GHz Distributed Amplifier With 24-dBm Output Power Using Quadruple-Stacked HBT in InP

In this letter, we present the designs and development of a wideband, high output power quadruple-stacked heterojunction bipolar transistor (HBT) distributed amplifier (DA). In particular, the stacked HBT configuration can improve gain and output power while achieving a very wide bandwidth. To validate the proposed design concept, a quadruple-stacked HBT DA is designed in an indium phosphide (InP) process. The measurement results show an average gain of 16 dB from 7–115-GHz bandwidth with a maximum of 24-dBm saturated output power ( $P_{\mathrm {sat}}$ ). To the best of the authors’ knowledge, this is the first time quadruple-stacked HBT is used in a DA to achieve the highest output power compared with other published work in the same frequency range.

In this letter, we present the design of high-power, wideband DAs in an InP technology. To achieve a high output power, a quadruple-stacked HBT DA is employed. The DA achieves a 7-115-GHz bandwidth with a 16-dB average gain. The maximum achievable saturate output power (P sat ) is 24 dBm, with the corresponding output power at 1-dB compression (P 1 dB ) of 21.6 dBm. To the best of the authors' knowledge, this is the first time a quadruple-stacked using InP HBT device is utilized in a DA configuration. In addition, the proposed quadruple-stacked DA achieves the highest output power among reported DAs with similar or larger bandwidths. of the HBT devices, the traveling input signal is gradually attenuated toward the termination resistor. As a result, there exists an optimal number of stages from which no input signal is further amplified due to the heavy attenuation. Hence, it is observed from the simulation that the gain and output power of the DA no longer increase, as the number of stages exceeds nine. At the same time, as the stacking order increases, the phase misalignment becomes more profound and causes the voltage swing not to add up in phase [1]. Moreover, the smaller base capacitance at higher stacked HBT leads to a more severe leakage current to the base that detrimentally impacts the output current phasor [27]. Therefore, stacking beyond four transistors does not indicate any output power improvement, as shown in Fig. 2(a). Fig. 2(b) demonstrates the maximum available gain of a single common emitter, a double-stacked HBT, and a quadruple-stacked HBT gain unit cell. At 110 GHz, the quadruple-stacked HBT provides ≈5 and 14 dB compared with the double-stacked and the single common-emitter topology, respectively. Therefore, in order to achieve above 22-dBm output power with the operation frequency covering up to W -band, a quadruple-stacked HBT with input capacitive coupling is employed. Furthermore, a compact on-chip wideband termination network is developed to provide wideband matching while providing an on-chip dc bias scheme.

II. CIRCUIT DESIGN AND IMPLEMENTATION
The transistor Q 1 -Q 4 is 10 µm in length with a nominal quiescent current of 12.5 mA. The base capacitors for Q 2 -Q 4 are valued at 92, 60, and 25 fF, respectively. The values of these capacitors reduce gradually, as the stacking goes up to provide a proper voltage swing at each transistor. Each transistor's base terminal is biased through a 1-k resistor. Peaking inductors are employed between each transistor to extend the bandwidth. The input line base inductance, L b , and the output collector line inductance, L c , are 60 and 90 pH, respectively, with a termination resistor of R term,b = R term,c = 60 . An impedance step-down matching is implemented with the output RF pad to achieve better matching. Both input and output inductors are realized using a high-impedance microstrip line.
The quadruple-stacked HBT DA employs a wideband on-chip biasing circuit to eliminate the use of an external bias tee. The output termination network is designed to have an effective impedance of around 60 . Fig. 3(a) shows the layout of the wideband termination network. The wideband termination with a wideband on-chip biasing network features a very compact design with a size of 200 × 150 µm. Fig. 3(b) demonstrates the simulated impedance of the termination network using ideal components and electromagnetic (EM) models. Although the frequency limitation of the EM model   is due to the nonideal spiral inductor, the impedance is kept within the −10-dB matching region from 20 to 100 up to 170 GHz. The input termination can utilize a similar network for the purpose of biasing the previous stage if necessary.
At each input of the stacked HBT gain cell, a coupling capacitor, C s = 20 fF, is used to improve bandwidth and provide a dc block at the input terminal. The coupling capacitor C s is designed using four identical metal-insulator-metal (MIM) capacitors connected in a series and parallel configuration to reduce the effects of process variation [16]. The chip photograph of the quadruple-stacked HBT DA is shown in Fig. 4. The total chip size is 1.9 × 0.92 mm, including all pads. The input and output ports of the DA are connected to 100-µm pitch ground-signal-ground (GSG) pads. The design parameters are summarized in Table I.

III. EXPERIMENTAL RESULTS
The proposed amplifier is designed and fabricated in an InP HBT process [17]. The InP process has a transition frequency f T of 290 GHz and a maximum frequency f max of 390 GHz. The nominal device collector junction current bias condition is J c = 1.3-1.6 mA/µm at an ambient temperature T a = 25 • C. The process offers high-quality factor MIM capacitors with low-loss thin-film dielectric wirings. The prototype is built on a test printed circuit board (PCB) substrate with the voltage supply pads being wire bonded onto a 500-pF single-layer capacitor. The bases of the transistors Q 1 -Q 4 are biased at 1.15, 2.1, 4.2, and 5.8 V, accordingly. Note that the   Measured and simulated P sat and P 1 dB over the frequency of the DA.
collector-emitter bias voltage of Q 1 is lower than the rest to optimize for the gain and power performance. The biasing pad at the bottom right of the chip can be used as a wideband bias tee for a previous stage if necessary. Fig. 5 illustrates the small-signal S-parameter measurements of the proposed quadruple-stacked HBT DA. The solid lines are the measured results, and the dashed lines represent the simulated ones. The amplifier achieves an average gain of 16 dB, covering a bandwidth from 7 to 115 GHz. The input return loss remains below −10 dB, and the output return loss is better than −8 dB across the operating frequency. Overall, the simulations relatively predict the measurement results of the amplifier with a slight reduction in bandwidth. One possible reason for the degradation could be severe couplings from the output transmission line to the ground planes and the adjacent dc biasing traces. Fig. 6 presents the measured stability factor K and the group delay in picosecond (ps). The DA is unconditionally stable with K > 1, and | | is verified to be less than one. From 10 to 110 GHz, the quadruple-stacked DA has a group delay variation of ±10 ps. The small-signal measurements are conducted in different frequency bands: 0-67 GHz    Fig. 7. The DA can still provide 16-dBm P sat at the 3-dB bandwidth 115 GHz. The proposed quadruple-stacked HBT DA achieves a power roll-off slope of 0.85 dB/10 GHz across the bandwidth. Fig. 8 illustrates the power sweep measurement at 25 and 75 GHz. At 75 GHz, the quadruple-stacked DA achieves a measured P sat of 20 dBm, a P 1 dB of 16.9 dBm, and a maximum power added efficiency (PAE) of 6.8%. Table II summarizes the performance of state-of-the-art wideband amplifiers in the same frequency range. Only [27] achieves up to 23.5-dBm output power using a quadruple-stacked FET in SOI technology. However, the bandwidth in [27] is limited to 104 GHz with a power roll-off slope of 3.83 dB/10 GHz, which is 2.98 dB higher than our work. To the best of our knowledge, the quadruple-stacked DA achieves the highest output power among the reported DAs with similar or higher bandwidth to date.

IV. CONCLUSION
In this letter, we demonstrate the development of a highpower and wide bandwidth quadruple-stacked HBT DA. A nine-stage DA is designed and fabricated in an InP process offering an f T / f max of 290/390 GHz. The amplifier achieves a 16-dB gain over 7-115-GHz bandwidth. The maximum P sat is 24 dBm, with a corresponding P 1 dB of 21.6 dBm.

ACKNOWLEDGMENT
The authors would like to thank the support of Keysight Technologies, Santa Rosa, CA, USA, under the Core Technology University Research Program.