A 5–10-GHz Highly Configurable IEEE 802.15.4a/4z-Compatible IR-UWB Coherent Transmitter in 28-nm CMOS

This letter presents an IEEE 802.15.4a/4z-compliant integrated impulse radio ultrawideband (IR-UWB) coherent transmitter that supports all channels in Band 2 from 6.5 to 10 GHz. A wideband phase-locked loop (PLL) with dual <inline-formula> <tex-math notation="LaTeX">$LC$ </tex-math></inline-formula> quadrature voltage-controlled oscillators (QVCOs) is implemented that covers more than 5-GHz frequency range. The PLL features a phase noise of −99.8 dBc/Hz at 1-MHz frequency offset and an rms jitter of 2.3 ps, which ensures reliable coherent operation. The quadrature clocks also make easy future <inline-formula> <tex-math notation="LaTeX">$I/Q$ </tex-math></inline-formula> receiver integration. The pulse envelope and width are digitally controlled, thanks to our flexible digital pulse-shaping configuration. Implemented in a 28-nm CMOS process with a supply voltage of 0.9 V, the chip occupies a core area of 0.21 mm2 and supports channel 5–15 with a peak pulse repetition frequency (PRF) of 499.2 MHz. The transmitter has a maximum output swing of 430 mV and the power consumption is 1.3 nJ/pulse at a PRF of 15.6 MHz.


I. INTRODUCTION
W ITH an increasing demand for accurate indoor and outdoor ranging and location, ultrawideband (UWB) technology draws much attention in the field of smartphones, intelligent vehicles, health monitoring, and the Internet of Things (IoT) due to its capability in providing centimeterlevel location accuracy under impulse-radio (IR) operation. In comparison to the legacy standard IEEE 802. 15.4a, the newly released IEEE 802. 15.4z standard improves upon the security of ranging and mandates a coherent operation mode for high-rate PHY [1]. Although free-running digitally controlled oscillators (DCOs) are preferred due to their low power consumption and short startup time, the poor clock Manuscript  quality cannot meet the stringent frequency accuracy and jitter requirements for coherent operation, even with the help of frequency tuning or calibration [2], [3], [4]. Therefore, in this work, as prior standard coherent systems do [5], [6], [7], a continuously running phase-locked loop (PLL) for clock generation is adopted that covers a wide frequency range from below 5 GHz to beyond 10 GHz. Different approaches have been explored to generate the UWB pulse that meets the spectral emission regulations as prescribed by Federal Communications Commission (FCC). Conventional IR-UWB transmitters use a digital synthesizer and a low-pass filter (LPF) [7] or direct baseband pulseshaping filters [8], [9], whose output is up-converted to RF with a mixer and amplified using a linear driver amplifier. However, high power dissipation, limited frequency range, as well as big die area in such transmitters are undesirable. As a result, digital pulse-shaping utilizing a low-supply CMOS process has become a dominant strategy because of its low power consumption and high programmability [2], [10], [11].
In this work, we present a more flexible digital pulseshaping method using a highly configurable ring counter and a parallel digital power amplifier (DPA) stages. The major contributions of our work include the following.
1) The design achieves the highest degree of pulse-shaping configurations reported in the literature. 2) A low-jitter PLL is implemented using dual LC quadrature voltage-controlled oscillators (QVCOs) for reliable coherent operation. 3) Integrated quadrature clocks improve the receiver signalto-noise ratio (SNR).
II. IR-UWB TRANSMITTER ARCHITECTURE The architecture of the proposed IR-UWB transmitter is shown in Fig. 1. Transmitter data and configuration bits are stored in on-chip registers before pulse generation through a microcontroller. The PLL is locked to an external 38.4 MHz reference and generates target carrier frequencies from 4.992 to 9.984 GHz, which are then used to drive the ring counter and pulse modulator. The output of the last stage within the ring counter serves as the clock to synchronize  Fig. 2 shows the wideband integer-N-type-II PLL architecture in this work. The PLL uses two LC QVCOs to provide continuous frequency coverage of Band 2 with a sufficient margin and overlap to accommodate the process, voltage, and temperature (PVT) variations and modeling inaccuracies. The use of QVCOs allows easy generation of quadrature clocks that are essential in improving the receiver's SNR [6], [7], [8]. A 3-bit current-controlled charge pump is implemented to tune the PLL bandwidth. The second-order loop filter is implemented off-chip to save chip area. A transmission gatebased multiplexer selects between the two QVCOs for different carrier frequencies. On the feedback path, a high-speed programmable divider is used to bring the carrier frequency down to a fixed frequency of 499.2 MHz. The divider incorporates the control logic into a conventional cascade prescaler and achieves an extended division ratio of 8-31 with four prescalers [12], [13]. The 499.2-MHz clock can be used as the chip rate clock, or fed to a frequency doubler to generate the 998.4-MHz clock for the receiver back-end [7]. The output of the divide-by-13 block and buffered 38.4-MHz temperaturecompensated crystal oscillator output are compared by the phase frequency detector. An analog lock detector [14] with a 10-bit counter depth is implemented as an indicator for PLL operation status.

A. Wideband PLL With Dual LC QVCO Cores
The quadrature clocks are generated by direct current coupling between two LC VCOs. Such structure suffers from inherent frequency uncertainty because it can support two oscillation modes as explained in [15], [16], and [17]. To avoid such uncertainty, RC phase shifters are used in this work in the coupling path as illustrated in Fig. 3 to ensure the loop gain of the desired mode is dominant. Therefore, one oscillation mode is boosted, while the other is suppressed. A combination of a capacitor bank-based coarse tuning and a varactor-based fine tuning is used for both QVCOs. Each capacitor bank consists of eight unit cells over 3-bit control. To further improve phase noise performance, high-quality factor (Q) MOM capacitors and parallel switches are used to increase the overall Q of the resonant tank. If desired, quadrature carrier frequencies in Band 1 (3.4944-4.4928 GHz) can also be obtained by dividing the corresponding frequencies by two within Band 2. Fig. 4 explains the detailed operation principle of the digital pulse-shaping method. The fully symmetric ring counter is  clocked by the PLL output and consists of 40 true singlephase-clock (TSPC) digital flip-flop (DFF) and transmissiongate-based 4:1 multiplexer unit cells. Due to its high programmability, the ring counter is able to bypass up to 30 unit cells for different pulsewidth and signal bandwidth. Bypassed DFFs are disabled to save power. As a result, if all unit cells are enabled, a maximum of 40 consecutive rectangular pulse windows as long as the clock period is created from T 1 to T 40 as shown in Fig. 4. The pulse envelope shaping function is implemented by 18 parallel DPA stages. Within each DPA stage, a logic AND operation is first performed between all T n 's and corresponding envelope configuration bits to determine whether this DPA stage should be ON or OFF during each T n . If BPM data is logic "1," an enable signal at node E is generated by performing OR function on all ON T n 's. The BPSK data selects either C L K p or C L K n to modulate the pulse. Before propagating to the dual-path tristate inverter output cells, the CLK is controlled by the enable signal at node E, which turns the inverters ON or OFF.

B. Digital Pulse Shaping Architecture
Between pulses, nodes P and N are precharged and predischarged to VDD and GND, respectively. Output current from two paths that have in-phase RF components, but out-ofphase low-frequency components are then capacitively combined at the antenna using on-chip DC block capacitors as illustrated in Fig. 4. This ensures that the DC component of the combined DPA output remains close to half-VDD independent of the modulation and helps reduce spectral content in the 960-1610-MHz frequency corner [2]. Also, the DC block capacitors and antenna serve as a high-pass filter that further reduces emission at low frequencies. Both up and down paths in each DPA stage consist of eight tri-state inverter unit cells configurable with 3 bits of output power control to meet the power spectrum density (PSD) requirement of −41.3 dBm/MHz [1] for different mean pulse repetition frequencies (mPRFs).
The proposed digital pulse shaping architecture achieves a significantly high degree of flexibility in programming the pulse envelope and width. The proposed structure is able to modulate BPM and BPSK bits with a Gaussian or other desired

III. MEASUREMENT RESULTS
The proposed IR-UWB transmitter is fabricated in a 28-nm CMOS process. Fig. 5 shows the die micrograph of the chip after wire-bonding. Anritsu MS2830A signal analyzer and Tektronix MSO72004C oscilloscope are used for frequencydomain and time-domain measurements.
The PLL is able to provide wide carrier frequencies with continuous integer multiples of 499.2 MHz from 10 to 20 as shown in Fig. 6(a). In the post-layout simulation, the corresponding I /Q mismatch of these carrier frequencies is within 1 • . The measured phase noise is −99.8 dBc/Hz at 1-MHz frequency offset and the rms jitter is 2.3 ps with a carrier frequency of 6.4896 GHz for channel 5 and channel 7 as shown in Fig. 6(b).   Fig. 7(a) shows the transmitted Gaussian envelope pulse waveform for channel 5 with a maximum peak-to-peak amplitude of 430 mV, including 2-dB loss from the wirebonds, PCB traces, SMA connectors, and cables. Fig. 7(b) shows a pulse burst transmission. The highly configurable transmitter is also capable of generating a rectangular envelope pulse as shown in Fig. 7(c), while Fig. 7(d) shows a monocycle pulse with a peak pulse repetition frequency (PRF) of 499.2 MHz, which can be used for UWB pulse radar applications due to its short pulse duration and high resolution [18], [19].
The transmitter supports all channels in Band 2. The measured PSD shows the compliance with the FCC mask for all supported channels as illustrated in Fig. 8. The performance of this work is summarized and compared with state-ofthe-art coherent IR-UWB transmitters in Table I. Our work features the highest degree of pulse-shaping configurations and is the only one capable of generating UWB monocycle pulses. Besides, only our work and [6] have implemented the quadrature clocks. However, the rms jitter and power consumption in [6] are significantly higher than our work.

IV. CONCLUSION
This letter presents an IEEE 802.15.4a/4z-compatible fully integrated IR-UWB coherent transmitter in 28-nm CMOS that supports all channels in Band 2. In addition, the transmitter can be used for UWB pulse radar applications. The wideband PLL based on dual LC QVCO cores provides high-quality I /Q clocks for coherent modulation and future I /Q receiver integration. Pulse envelope, width, and amplitude are all highly configurable to meet FCC regulations under different channels and data rates without off-chip filtering.