Neural Network Model-Predictive Control for CHB Converters With FPGA Implementation

Finite control set model-predictive control appears an interesting and effective control technique for cascaded H-bridge converters but, because of its computational complexity, becomes impractical when the number of levels of the converter increases. This article proposes a neural-network-based approach capable of overcoming the computational burden of conventional predictive control algorithms. The proposed control is, then, applied to a cascaded H-bridge static synchronous compensator using a field-programmable gate array and tested via hardware in the loop. Results and analysis demonstrate that the optimal control of multilevel converters with many levels can be obtained with low computational effort.


I. INTRODUCTION
C ASCADED H-bridge multilevel converters (CHB-MLCs) are characterized by well-known advantages, such as modularity, low dv/dt, operations at low switching frequency, and, in medium-voltage systems, the possibility of avoiding step-up or step-down transformers [1], [2], [3]. During the past few years, the model-predictive control (MPC) strategy has been attracting increasing attention from researchers and practitioners also in the field of power converters [4], [5]. The most popular declination of MPC is the so-called finite control set model-predictive control (FCS-MPC), where the control problem is formulated considering the switching combinations of the converter as a finite and countable set of inputs [6], [7]. The possibility of directly controlling the switching signals avoids the use of a modulator, provides a fast dynamic response, and limits switching frequency, thus ensuring low losses for the converter. FCS-MPC is also popular for its simplicity since it just searches for the best switching pattern driving the converter [8]. However, in MLCs, computational complexity grows exponentially with the number of levels of the converter. Therefore, calculating the optimal input for the next sampling step becomes challenging [9]. Significant efforts can be found in the literature to improve the efficiency of FCS-MPC algorithm to make it implementable in a few tenth microseconds. One possible approach is reducing the search space within a subset of all the possible inputs. However, with this approach, only a suboptimal solution can be found with the existing real-time constraints [10], [11], [12]. Nasiri et al. [13] and Ni and Narimani [14] proposed control strategies that explicitly exploit system's dynamics. However, they do not compute the control solving an optimization problem. In [15], the optimization problem is solved by employing a sphere decoding algorithm. However, it requires the determination of an initial radius and involves several iterations. An interesting case is the control of the CHB-MLC static synchronous compensator (CHB-STATCOM), which is one of the most advanced flexible alternative current transmission systems and is capable of regulating and stabilizing the grid voltage through the control of the reactive power. STATCOMs are commonly used in the stabilization of medium-voltage ac lines; hence, they take advance from multilevel topologies with a large number of levels, which makes their control with the FCS-MPC strategy challenging. Because of the high computational complexity and nonlinearity, a common solution divides the overall optimization problem into subproblems that are solved separately [16], [17], [18]. For instance, Zhang et al. [16] proposed first solving the current control problem and then ensuring voltage balancing. The resulting computational complexity is polynomial. Zhang et al. [19] proposed a branch and bound strategy to further reduce the computational complexity of the current controller, obtaining an algorithm with linear complexity. However, the number of computations is still high.
Owing to the large number of signals necessary to drive their power switches, MLCs usually employ field-programmable gate arrays (FPGA)s because they make available a large amount of input/output pins necessary for driving the signals of the CHB converter. Moreover, they are used for acquiring inputs, for the modulation algorithm, and for achieving the highest computational speed [20], [21], [22]. Zhang et al. [20] implemented the polynomial-level FCS algorithm in [19] by employing a DSP for the main calculations of the control law, accompanied by an FPGA for reading the analog input signals, for sending the gate signals to the switches, and for hardware acceleration of most expensive parts of algorithm computation. Owing to the large number of computations needed by an FCS-MPC approach, it is a good solution to implement the overall control law on the FPGA [23], [24], [25], [26].
In recent years, machine learning (ML) techniques have been widely used in many engineering fields. One popular application in the automatic control field is to approximate a control law that is too computationally expensive to be implemented in real time. With offline computations, the ML procedure computes a nonlinear function that embeds the optimization solver. This function can be used in online implementation as a replacement for the original controller. In [27], a shallow neural network (NN) is trained to learn the MPC law for a two-level inverter for different circuit parameters and loads. In [28], the same strategy is applied to reduce the computational cost of a two-level inverter when considering horizons equal to one, two, and three. In [29], horizons 1 and 2 are evaluated on a three-level neutral point clamped topology. In [30], an NN is used for a flying capacitor multilevel topology. A comparison of timings and space complexity of the algorithm is carried out, and the number of output neurons linearly depends on the number of levels. In [31], a comparison between classification and regression NNs for modular MLCs is presented, where regression turns out to be more effective than classification. Timings are compared for predictive horizons of lengths one and two. In [32], different ML techniques are compared for approximating MPC on a CHB inverter. In a previous work [33], a preliminary methodology was proposed for deriving an NN capable of learning the optimal FCS-MPC. Owing to the low computational burden and the hardware acceleration, it is not necessary to consider the step ahead delay, and the control input is actuated in the same sampling interval.
The manuscript presents: 1) a deep study of the performance of the NN-MPC compared to the FCS-MPC on both the steadystate and transient conditions; 2) the generalization of the algorithm for different numbers of levels and prediction horizons via simulative results and the analysis of the performance when weighting coefficients and number of neurons change; 3) the description at the register transfer level (RTL) of the experimental implementation of the NN-MPC on the FPGA platform; 4) the evaluation of clock cycles needed for the algorithms execution and the actual time spent in computations on a Cyclone V FPGA on DE-10 Nano board; and 5) the analysis of the impact of the computation delay on the controller performance via hardware-in-the-loop simulation by employing the FPGA and the Simulink model.
The rest of this article is organized as follows. In Section II, the FCS-MPC strategy for a CHB inverter is discussed, and the NN-MPC approach is derived. In Section III, the CHB-STATCOM mathematical model is described. In Section IV, the FCS formulation for a CHB-STATCOM is presented. In Section V, the simulation results are discussed. In Section VI, the RTL implementation of the two algorithms is described, the number of computations is derived, and the HIL comparison is presented. Finally, Section VII concludes this article.

A. Finite Control Set Model-Predictive Control
Consider a general CHB inverter composed of N H-bridges per phase as in Fig. 1. The currents are governed by Kirchhoff's laws where i a,b,c are the three-phase currents, v a,b,c are the voltages at the inverter output, v s (a,b,c) are the voltages at the load side, and R and L are the resistance and the inductance of the load, respectively. Using the Clarke transformation, the αβ reference frame currents are given by Previous equations, discretized via Euler approximation, become where T is the sampling interval and k is the generic sampling instant.
In the FCS-MPC, the state in the next sampling instant is predicted using the dynamical model of the system. The control law calculations consist of the minimization of an optimization function, which generally includes two weighing terms: one for the deviation of the state from a reference value and the other for the effort of the controller. The FCS current control aims to solve the following minimization problem: where the first term is the weighted norm of the error between the reference current and the predicted current at time k + p, while the second term weights the variation of the applied switching vector to limit the switching loss of the converter. The weighting matrices can be expressed as Q i = w i × I and Q s = w s × I, where I is the 2 × 2 identity matrix and w i and w s are scalar numbers. The prediction horizon h determines the number of future predictions to be computed, and the optimal input S α,β (k) is searched within the set of all the possible switching combinations V α,β .
With the FCS approach, the solutions are reached by computing the cost for each possible vector and, then, its minimum. The prediction is computed making an explicit use of the model in (1) The number of possible switching vectors is (12 × N 2 + 6 × N + 1) h , and the exhaustive search algorithm is quadratic with respect to the number of levels and exponential with respect to the prediction horizon.

B. Neural Network Model-Predictive Control
In MLCs, the complexity of the controller becomes challenging when the number of levels becomes relevant, as occurs in medium-voltage systems. To overcome this difficulty, a novel approach is proposed to solve the optimal current control problem via an NN approximation, which consists of two distinct steps: in the first step, the CHB is simulated and the optimal vectors S αβ (k) are computed solving (4) for all the collected con- . Further data are collected by solving the control problem for random configurations. In the second step, the overall dataset is used to train an NN to obtain optimal current control inputs. A shallow NN is employed, using the Bayesian regularization backpropagation to minimize the sum squared error. The NN has eight input and two output variables; therefore, the input and output neurons are eight and two, respectively.
It is proposed to use η hidden neurons with a hyperbolic tangent activation function and a simple linear one for the output layer. Note that the computational complexity of the NN does not depend on the number of levels and prediction horizons and is only given by the adopted architecture. For the considered simple NN, 8 × η + η × 2 sums and multiplications and η activation function computations are needed. This approach brings a closed form of the approximated solution of the optimal problem, which can be quickly calculated in real time. Since it is not possible to obtain a feasible result by simply rounding the S αβ vector, the result is transformed into a reference frame, in which the α-axis is delayed by π/3, obtaining the S Then, the feasible points are arranged on a grid with orthogonal axes. The transformation also provides a scale factor in order to make them integer values. In this way, the feasible switching vector is obtained by rounding S π/3 αβ . Hence, the inverse transformation into the abc frame leads to The NN, including the reference transformation, is shown in Fig. 2.

III. CHB-STATCOM MODEL
The proposed approach is tested using a CHB-STATCOM composed of an inverter with N H-bridges per phase, each one including a dc-link capacitor C. The converter is connected with the grid through a series inductor L, as shown in Fig. 3. Each H-bridge can output positive, negative, or zero voltage, whose rated value is V DC .
According to this, the system can be modeled considering the inputs of the system as discrete variables where v DC(a,b,c)i is the dc-link voltage of the ith cell of the corresponding phase. Since the inverter is sized to have a small ripple voltage on the dc side, usually v DC(a,b,c)i is assumed to be equal to V DC . The dynamic model of the CHB-STATCOM is where i a,b,c are the three-phase currents fed by the inverter, v s(a,b,c) are the three-phase grid voltages, and R is the equivalent resistance of the STATCOM. Using Clarke's transformation and discretizing, we have

IV. MPC FOR CHB-STATCOM
As discussed in [33], the FCS-MPC problem can be divided into three distinct subproblems: 1) current tracking, which is presented in Section II; 2) cluster voltage balancing; and 3) individual voltage balancing. Once the switching vector S αβ is computed, it is transformed into abc coordinates. The zero-sequence voltage is computed to balance the three clusters. Given the predicted average voltages of the three clusters v a,b,c (k + 1), the cluster voltage balancing problem is where C eq is the equivalent phase capacitance, equal in all the phases. The first term is a weighted norm of the deviation of the three cluster voltages from the reference value, and the second term aims to reduce the common-mode voltages. Then, the control algorithm searches among the redundant vectors in the abc coordinates, which are 4N + 1.
The third subproblem aims to find which H-bridges must supply the voltage in the proper polarity to obtain the overall desired voltage. Specifically, the individual voltage balancing problem solves the following optimization problem for each phase: where S * (a,b,c) (k) is the switching vector computed by (9). Zhang et al. [16] also proposed an efficient algorithm for solving the capacitor voltage balancing problem. The solution can only be : the optimization problem becomes a {0, 1} programming problem. Then, rather than computing the cost for every possible {0, 1} combination of the switching states, which are 2 N + 1, the cost increment in choosing 1 rather than 0 is computed for every phase cell. Once the N costs are determined, they are sorted in ascending order, and the first |S * (a,b,c) (k)| elements of the array identify the best possible s (a,b,c)i (k) that must be selected to ensure the desired phase voltage. With this procedure, the computational cost is no longer exponential and is limited to the cost of the sorting algorithm, which must sort an array of N elements.

A. Training Procedure
The power system in [34] was used as a test bench for the STATCOM. The original test bench was modified to deal with a medium-voltage grid. In particular, the voltage source was set to 10 kV, while the nominal power was set to 6 MVA. The CHB-STATCOM replaced the original two-level STATCOM. Three different case studies were considered, i.e., three STATCOM configurations with N = 5, 10, and 20 H-bridges, respectively. STATCOMs were sized to account for grid voltage variations of ±20% of the nominal voltage, providing up to ±600 kvar. The inductor was 44 mH, while the capacitors for the three cases were 2600 V-250 μF, 1300 V-500 μF, and 650 V-1000 μF [3]. The test bench simulates changes in the voltage source propagating through grid elements until they reach the node where the STATCOM is connected. Several step changes in the source voltage were simulated in the interval of [0.8, 1.2] per unit (p.u.) voltage. In this way, the STATCOM, controlled by FCS-MPC, reacted by providing reactive power in all the ranges of the rated STATCOM power (600 kvar). For each configuration of N , η, (w i , w s ), and h, the data were collected from a simulation of 8 s with 80 step changes. Since the controller sampling time was 40 μs, the overall dataset was composed of 200 000 samples. Starting from this dataset, a further dataset was created by perturbing the inputs of the optimization problem, i.e., i ref α,β (k), i α,β (k), v s(α,β) (k), and S α,β (k-1), with random noise and computing the optimum values S αβ (k) for these new points. The original dataset and the perturbed one were merged into one dataset: this procedure gives robustness to the learning procedure and improves the NN performance. Once the dataset was collected, several NNs were trained in MATLAB, changing the activation functions of hidden and output neurons, training algorithms, and performance indexes. The training dataset was 70% of the overall set, while the validation and the test datasets were 15%. For each configuration, the three sets (training, validation, and test) were collected randomly grabbing the points from the overall set. In this way, every learning procedure had a different division of the datasets and computed a slightly different NN; therefore, it was possible to select the best one. This procedure was done to reduce the effect of dataset division on the NN performance. In this article, ten NNs were trained for each parameter combination, and the best one was selected. The best NN had hyperbolic a tangent function ("tansig") in the hidden neurons and a linear activation function ("purelin") in the output neurons, while the Bayesian regularization ("trainbr") was used for the learning procedure, considering as performance index the sum squared errors ("sse"). The selected NN was the one with minimum sum squared error. A shallow NN was employed since it was the simplest architecture and was accurate enough for our scope. Each NN training, considering 1000 epochs, takes on average about 4 min to be computed on the authors' PC (on 11th Gen Intel Core i7, eight cores, 2.8 GHz, 8-GB RAM, Linux Ubuntu 20.04, MATLAB 2021b).

B. Performance Evaluation
The performance of the different approaches was compared considering the mean absolute error (MAE) between current and reference, the switching frequency, and the total harmonic distortion (THD) on steady state and evaluating the transient response. The NN-FCS approach was tested using varying number of levels, weighting parameters, number of hidden neurons, and prediction horizon.
1) Different Numbers of Levels N : In order to analyze the generalization of the NN approach for different levels, three CHB inverters were considered, with N = 5, 10, and 20 Hbridges. The weighting coefficients (w i , w s ) were fixed to (1, 0.1), and η = 8 hidden neurons are considered with a prediction horizon h = 1. Fig. 4 shows the switching frequency of the controllers for different steady-state conditions of the quadrature current reference. The frequency is not fixed due to the absence of a modulator and varies according to reference changes.      a slightly lower frequency and harmonic distortion, compatible reference errors in steady state, and a slightly slower dynamic response. Moreover, it follows the optimal controller trend, irrespective of the number of levels of the converter, making the NN a general solution and a promising alternative for real-time implementation. Table I summarizes the average performances.  Further tests were carried out to analyze the system outside the nominal conditions to evaluate the performance of the NN controller in a region outside the training dataset. In particular, a voltage 20% higher than the nominal value was applied, and a current 20% higher than the rated value was supplied. The grid voltage was 1.4 p.u., and the reference quadrature current step was 1.2 p.u. Fig. 8 shows the step response for the N = 10 inverter. A zoom of the αβ currents is shown highlighting the satisfactory dynamic response. Fig. 9 shows the switching frequencies when applying the two controllers. The NN was able to generalize the control law even on operational conditions not considered in the training dataset. This result is still valid for N = 5 and N = 20 STATCOMs, but the relative plots are omitted for space reasons.
2) Different Weighting Coefficients (w i , w s ): The weighting factors of the FCS-MPC cost function in (4) allow a tradeoff between tracking performances and switching losses. By increasing the ratio w i /w s , the controller gives higher priority to reference error minimization at the expense of the switching frequency. Once the weighting factors are suitably tuned, it is possible to train the NN that will approximate the desired controller behavior. In order to evaluate the NN performance under different tuning parameters, tests were carried out by varying the FCS-MPC weighting coefficients (w i , w s ) between (1, 0), (1, 0.1), (1, 0.5), (1,1), and (0.5, 1). Thus, different NNs were trained to learn the controllers with different tuning parameters. The following tests refer to the N = 10 case, with η = 8 and h = 1. Figs. 10-12 show the switching frequencies, the MAE, and the THD at steady state for the different control    tunings, respectively. As the ratio increases, the MAE and the THD decrease at the expense of a higher switching frequency. Conversely, as the ratio decreases, the switching frequency becomes lower but MAE and THD increase. The step response in Fig. 13 shows that a low ratio also impacts the transient state, increasing both settling time and overshoot, as evident in the case (w i , w s ) = (0.5, 1).

3) Different Hidden Neurons η:
The tradeoff between the performance and complexity of the NN is a key factor for the online implementation. In order to find the best tradeoff, tests were carried out by training NNs with a different number of hidden neurons. Starting from the data collected for the case in which     Fig. 17 presents the transient state. The tests above showed that even an NN with just two hidden neurons was enough to stabilize the system. However, its performance was poor if compared to NNs with more neurons. The performance analysis suggested that η = 4 was sufficient to guarantee satisfactory results. At the same time, η = 8 was the best option since it generated the lowest switching frequency, and its performance was compatible in terms of THD and MAE with respect to η = 4, 16, 32.

4) Different Prediction Horizons h:
By increasing the prediction horizon of the FCS-MPC, it is possible to improve the overall performance of the controller [7]. In order to test the ability of the NN approach to learn multiple horizons, FCS-MPC tests were carried out by changing the prediction horizon. Since the increase of the control horizon led to a dramatic increment in computations, horizons larger than three were not tested. It turned out that horizon h = 2 led to better performances with respect to the case in which h = 1. Choosing h = 3, the one-step prediction controller was improved, but no significant improvements were found by changing h from 2 to 3. For this reason, NN approximations were tested just for h = 1 and 2. Figs. 18-20 show the steady-state switching frequency, MAE, and THD, respectively, for the case in which N = 5, (w i , w s ) = (1, 5), approximated with η = 8 NNs for horizon h = 1, 2. The NN-MPC tended to have slightly lower switching frequency and slightly higher THD when compared with the original FCS-MPC. Fig. 21

VI. HARDWARE-IN-THE-LOOP SIMULATIONS
Hardware-in-the-loop tests were carried out for N = 5, 10, and 20 cases. The weighting parameters were fixed to (w i , w s ) = (1, 0.1). The number of hidden neurons was η = 8: the best tradeoff between accuracy and cost complexity for the discussed implementation. The prediction horizon was h = 1 to allow a fair comparison with the FCS-MPC, whose classical solution is impractical for larger horizons with a large number of levels.

A. RTL Implementation
In this section, the RTL implementation is discussed, presenting the algorithmic state machines (ASMs) that realize the sequential steps of the algorithm and giving insights into the combinatorial part. In the ASMs, the notation <= is a signal assignment, while ← means that a register is updated, implying that the value is changed in the next clock cycle. The ASM that implements the NN calculation for η = 8 is shown in  minimizes the cost is selected. In the ASM in Fig. 23, the cost is initialized to be the maximum stored value, while the optimum value is initialized to be S 0 abc . The const abc value includes the term that is constant during the operations in the same sampling interval (INIT 1 ). The minimum and maximum values between  adders and 12 multipliers multiplexed in an eight-level pipeline structure. The minimum cost and the optimal vector are iteratively updated by employing the comparator circuits in the figure.
The individual voltages balancing problem is solved for each abc phase starting from the optimal value S min abc . It proceeds as follows: the cost for each H-bridge is computed; then, the cost array is sorted in increasing order. The first |S min abc | H-bridges are selected to be 1 or −1 according to the sign of S min abc , while the others are set to 0. Fig. 24 presents the implementation of the different steps, computed concurrently for each phase.      choosing 1 rather than 0 is computed. Otherwise, if the MSB is 1, the cost difference in choosing −1 rather than 0 is evaluated.
The N costs are evaluated and stored by employing a fivelevel pipeline and utilizing four adders and four multipliers: it makes it possible to use the 12 total adders and multipliers for computing the three phases in parallel. The second ASM implements the sorting algorithm: a selection sort algorithm is chosen for simplicity. The third ASM selects the best H-bridges setting them to 1 or −1, leaving the remaining values equal to 0. These switching variables are converted into gate signals.
On the other hand, FCS-MPC implementation employs the same architecture for the clusters and voltage balancing problems but differs for the current control loop. The ASM that implements the FCS current control consists of an initialization step, the cost computation, and the evaluation of all the possible vectors (similar to cluster voltage balancing ASM) and the abc transform. The cost computation is realized using the same adders and multipliers multiplexed in an eight-level pipeline. Considering the steps needed by the exhaustive search, the pipeline, the initialization, and the transform, the total number of steps needed by the control loop is 12N 2 + 6N + 14.

B. Hardware-in-the-Loop Results
The two algorithms were implemented using a Terasic DE-10 Nano board equipped with an FPGA SoC Intel Cyclone V (5CSEBA6U23I7). Each control algorithm was tested via hardware-in-the-loop setup, in which the STATCOM model was simulated in Simulink environment, while the algorithm computations were implemented on the FPGA. The FPGA-in-the-loop app in Simulink was used to generate a Quartus project that embedded the hardware implementation. More in detail, it provided the Universal Asynchronous Receiver-Transmitter connection that permitted the communication between the Simulink model and the FPGA control. The simulation step was set according to the actual clock frequency needed to guarantee the correct execution of the algorithm. With the described implementation, with the register sized to 48 bits and the sharing of the arithmetic resources, the Quartus Time Analyzer ensured correct execution with a clock frequency of 36 MHz. The clock cycles needed for the two algorithms and the execution times for different values of N are reported in Table III.
It can be seen that the time delay of the NN is the same, independently of the number of levels. This result leads the NN-MPC to have a much shorter execution time than the classic FCS-MPC. The time spent in clusters and individual voltage balancing is the same for the two controllers since the neural network replaced just the current control. For N = 5, FCS-MPC takes 11.75 μs, while NN-MPC takes 3.03 μs. Thus, the classic control is implementable in real time, and it is possible to compute the input within the 40-μs sampling interval. By the way, NN-MPC takes an execution time nearly four times smaller. For N = 10,  The performance of the standard FCS-MPC is degraded due to the one sampling interval delay. Because of this, it is a common solution to use a delay compensation as in [9]. Using NN-MPC, the control loop is completed in 4.97 μs, which is one order of magnitude less than the conventional FCS-MPC, and it makes it possible to apply the input in the same sampling interval. Fig. 25 shows the algorithm steps simulated via ModelSim, whereas Figs. 26-29 shows the HIL simulations for N = 10. Compared with the FCS-MPC with delay compensation, NN-MPC has similar performance on the steady-state error and harmonic distortion, as seen in Figs. 27 and 28. However, in Fig. 26, the steady-state switching frequency of the NN-MPC is still slightly lower, and in Fig. 29, the dynamic performances of the proposed approach are superior since it has faster response and does not suffer from the inaccuracy of the two-step forward prediction that leads, in any case, to a deterioration of the performances.
For N = 20, the standard control is impractical unless the sampling interval is increased. The proposed one takes 10.94 μs, which is small enough to permit the real-time implementation. It is interesting to notice that the time spent for the NN with η = 8, 4, 2 hidden neurons was similar for the described implementation since 12 adders and multipliers were used in parallel (the cluster voltages balancing requires four of them for each phase). In particular η = 4 requires 27 iterations, while η = 2 requires 25 iterations, resulting in 0.75 and 0.69 μs. With the described implementation, without adding extra hardware resources, the NN with η = 16 required to solve the two loops in the ASM in Fig. 22 twice, resulting in 50 iterations. Analogously, the η = 32 NN required to solve the loops four times, and 88 iterations were needed. The execution time spent was about 1.39 and 2.44 μs for the two cases. The FCS-MPC for N = 10 and horizons h = 2 and 3 required about 89.9 and 852 us. In contrast, the time spent by the NN-MPC is always the same as Table III, regardless of the prediction horizon. Fig. 30 presents a schematic diagram flow that summarizes the whole procedure, which embeds: 1) the simulation of the FCS-MPC to control the CHB inverter for collecting data; 2) the training of the NN; 3) the selection of the best NN in the closed-loop performance; 4) the implementation on the FPGA; and, finally, 5) the HIL simulation used to analyze the effect of computation delay.

VII. CONCLUSION
In this article, an NN-MPC for a cascaded H-bridge converter was presented. A shallow NN was trained to learn the FCS-MPC solution. The control was tested on a CHB-STATCOM in simulation to analyze the performance of the proposed controller in comparison to the standard FCS-MPC. The controllers were tested for different numbers of levels, and the results suggested that the NN well follows the optimal behavior in each case. The standard FCS-MPC and the proposed algorithm were implemented on the FPGA, and the time spent by the computations of the controllers was derived. It turned out that the standard FCS-MPC is only implementable for a CHB with ten H-bridges with a delay compensation technique and becomes impractical for 20 H-bridges.
On the other hand, the time delay of the proposed approach allows the control input to be computed within the same sampling intervals, even for a CHB inverter with 20 H-bridges per phase.