Noise Analysis and Design Methodology of Chopper Amplifiers With Analog DC-Servo Loop for Biopotential Acquisition Applications

Biopotential acquisition chopper instrumentation amplifiers require a dc-servo loop (DSL) in order to filter electrode dc offsets. However, the noise performance degradation due to the addition of the DSL is often overlooked despite that it can be very detrimental at the frequencies of interest. This article presents an in-depth noise analysis of biopotential acquisition chopper instrumentation amplifiers with analog DSLs. Analytical expressions that predict the noise of different DSL implementations are found and a design flow to minimize their noise contribution is proposed. The design methodology is demonstrated with example circuits targeting biopotential recording systems. These circuits are implemented using a standard 180 nm CMOS technology, and their performance is verified through postlayout simulations. The findings of this work provide a comprehensive understanding of the noise characteristics of a DSL, its impact on noise performance, and design strategies for noise optimization.


I. INTRODUCTION
B IOPOTENTIAL signals such as those present in elec- trocardiography (ECG), electromyography (EMG), and electroencephalography (EEG) are typically weak, in the order of a few µV to mV, and mainly distributed in a low-frequency range below 1 kHz as illustrated in Fig. 1 [1], [2].Accordingly, they are vulnerable to low-frequency noise, especially the 1/ f noise present in CMOS amplifiers.A commonly used circuit design technique to cope with this problem is to employ chopper-stabilized biopotential amplifiers.This technique has been extensively adopted in biosensing analog front-ends [3], The authors are with the School of Electrical Engineering and Computer Science, KTH Royal Institute of Technology, 100 44 Stockholm, Sweden (e-mail: ykhuang@kth.se;saul@kth.se).
Color versions of one or more figures in this article are available at https://doi.org/10.1109/TVLSI.2023.3315417.
In addition to stringent 1/ f noise requirements, biopotential amplifiers face an additional challenge in the form of electrode dc offset (EDO).The EDO arises due to the difference in half-cell potentials between the electrode and the electrolyte, which can be as high as tens of millivolts for gel electrodes [9].The EDO is a crucial consideration in biopotential amplifier design, as it can saturate the amplifier chain and distort the signal.Although commonly treated as a dc offset, in reality, EDO is not constant and exhibits variations over time due to electrode displacement.To address this issue, the biopotential amplifier must have ac-coupling characteristics that eliminate the EDO.
One possible solution is to use capacitively coupled instrumentation amplifiers (CCIAs) which are implemented by placing a series dc-blocking capacitor at the input as illustrated in Fig. 2(a) [10], [11], [12].Since the amplification factor and the high-pass corner frequency are determined by the ratio between C F and C in and the time constant of R F C F , respectively, very large capacitors are commonly required in order to achieve high gain and extremely low cut-off frequencies.This is impractical in multichannel recording applications as a large silicon area would be required.Besides the area penalty, the mismatch between the capacitors makes the CCIA sensitive to large common-mode interference.To mitigate the mismatch between the capacitors, a chopper is commonly placed in front of input capacitors and another chopper is placed at the output of the amplifier as depicted in Fig. 2(b) [13], [14], [15].In this way, the common-mode interference that is converted to differential-mode due to mismatches is upconverted to a higher frequency.However, the addition of chopping has the following drawbacks.First, the presence of a switched-capacitor at the input impacts the input impedance.The input impedance of a CCIA is approximately 1/2 f chop C in , where f chop represents the chopping frequency and C in refers to the series dc-blocking capacitor [16].Second, the placement of the chopper before the input capacitors upconverts the EDO, preventing it from being blocked.Consequently, additional circuitry is required to suppress the EDO.
An alternative approach to achieve ac-coupling and filtering the EDO is through the use of active feedback, as demonstrated in Fig. 2(c).This topology, commonly known as a dc-servo loop (DSL), involves an integrator in a negative feedback loop.The integrator extracts the dc component, including the low-frequency offset, from the output signal and feeds it back to the input, where it is subtracted [17].Through this mechanism, the DSL can eliminate the EDO present in the signal, thereby providing an effective means of achieving ac-coupling characteristics.This approach can be applied to design an EDO-rejection chopper CCIA by utilizing a voltage-mode DSL (VM-DSL) through a capacitor feedback network.Alternatively, this approach can be implemented as a current-mode DSL (CM-DSL) in which the DSL generates a current output that can be subtracted at low-impedance nodes in the amplifier.This method requires fewer capacitors, making it more area-efficient and a preferred solution for integration.DSL circuits provide an efficient way to remove the EDO, however, they also have drawbacks.One of its major drawbacks is the introduction of additional electronic noise, which can easily become detrimental to low-noise biosensor applications as demonstrated in [4], [17], [18], and [19].While significant effort has been devoted to the noise analysis and optimization of chopper amplifiers [4], [16], [20], [21], a comprehensive analysis of the noise contribution of the DSL has not been widely investigated.A poorly designed DSL can become the primary source of noise in the amplifier chain, thereby reducing the signal-to-noise ratio (SNR) and compromising the amplifier's performance.Therefore, it is essential to understand its noise characteristics and how it affects the overall noise performance of an amplifier.In this study, we aim to perform a thorough theoretical analysis of the noise contribution of the DSL and propose a design methodology to minimize its impact.By characterizing the DSL's noise, we can optimize its design, mitigate its noise contribution, and improve the overall amplifier's SNR.
This article is structured as follows.Section II provides a brief explanation of the chopper instrumentation amplifier's operating principle and analog DSL circuit architectures that can be configured either in voltage-mode or current-mode.In Section III, the noise analysis of the chopper amplifier is presented, and the impact of the DSL, including its noise modeling and noise contribution, is discussed.Section IV demonstrates transistor-level circuit examples and a design methodology to enhance the noise performance.Finally, Section V presents a discussion followed by conclusions in Section VI.

A. Chopper Stabilization Technique
The basic principle of a chopper-stabilized amplifier is illustrated in Fig. 3.The input signal is upconverted by the input chopper to the chopping frequency f chop .The amplifier's input-referred offset voltage v os and the electronic noise v n , including 1/ f noise and thermal noise, are then added to the chopped-modulated signals.Thanks to the upmodulation of the signal before being amplified, 1/ f noise is not present in the frequency band of interest if the condition of f chop > f c is fulfilled, where f c is the corner frequency of the 1/ f noise.After amplification, the signal of interest is downconverted to baseband while the unwanted 1/ f noise and v os are upconverted to f chop .Likewise, common-mode interference that is converted to the differential-mode signal due to mismatches in the amplifier is also upconverted to f chop , resulting in an improvement of the low-frequency common-mode rejection ratio (CMRR).The noise located at odd harmonics of f chop and other upconverted unwanted signals can be suppressed by a low-pass filter.The chopper-stabilized amplifier offers very good noise performance within the band of interest for biopotential sensing.However, it still requires additional circuitry to filter the EDO.

B. DC-Servo Loop
The EDO can be filtered by adding a negative feedback DSL as depicted in Fig. 4. The chopper amplifier is modeled as a single-pole system with a gain of A 1 and cut-off frequency f p1 .Likewise, the DSL is modeled as a single-pole system with a gain of A 2 and a pole at f p2 .Assuming that f p1 ≫ f p2 , the overall transfer function is given by Accordingly, the cut-off frequency of the high-pass response is A 1 A 2 f p2 and the dc component is suppressed by 20 log(1/A 2 ) dB.
The noise contribution of the DSL can be analyzed by extracting the transfer function from the input-referred noise of the DSL, V n,DSL , to the output of the amplifier V out .For low frequencies, the noise transfer function is Consequently, the low-frequency noise of the DSL appears at the output without attenuation and it may become a significant noise contributor to the core amplifier.For this reason, it is essential to conduct a meticulous analysis of the noise contribution of a DSL and optimize its design to achieve the desired noise performance.

C. Architecture of Chopper Amplifier With Analog DSL
The voltage-mode DSL (VM-DSL) [7], [14], [15] and the current-mode DSL (CM-DSL) [7], [23], [24] are two distinct analog DSL implementations used for EDO cancellation as demonstrated in Fig. 5. VM-DSL is commonly employed in CCIA design.This topology comprises a core amplifier (A V 1 and A V 2 ), choppers (CH in and CH out ), and a capacitor negative feedback loop, which determines the amplification factor by the ratio between C in and C f .The VM-DSL loop integrates the output voltage of the core amplifier and directly feeds it back to the input by using the capacitors C hp .Through this mechanism, the VM-DSL can effectively remove the EDO from the input signal.The maximum EDO rejection (V EDO,max ) and the high-pass cut-off frequency ( f hp ) of this architecture are determined by where the f u,INT is the unit-gain frequency of the integrator.The VM-DSL requires only a single integrator in the feedback loop, resulting in reduced power consumption.However, this approach requires the use of several capacitors, which occupy a significant silicon area.Therefore, proper capacitor sizing is essential to minimize area overhead while also ensuring adequate performance of the amplifier.
An interesting alternative that requires fewer passive components is the CM-DSL.Two CM-DSL topologies are analyzed in this study: CM-DSL topology I [Fig.5(b)], and CM-DSL topology II [Fig.5(c)].The CM-DSL is typically associated with the current-balancing instrumentation amplifier (CBIA) [25].The CBIA consists of a transconductance amplifier (Gm) and a transimpedance amplifier (TIA).This is a popular architecture for biopotential amplifier design as it offers higher CMRR and lower power consumption compared to the traditional three-OPAMP IA structure [26].In this architecture, EDO results in a current I EDO flowing through the degeneration resistor R 1 , which is compensated by the I DSL generated by the CM-DSL.Compared to VM-DSL, CM-DSL has the advantage of eliminating the need for capacitors, thereby saving silicon area, achieving higher input impedance, and improving the CMRR due to the absence of capacitor mismatch.The maximum EDO rejection and the high-pass cutoff frequency are calculated by where I DSL,max is the dc biasing current at the output stage of Gm 2 , which is the maximum output current that can be supplied by Gm 2 .Hence, there exists a trade-off between maximum EDO rejection and power consumption in the design of this architecture.
As discussed in Section II, the input chopper upconverts the input signal, comprising of biopotentials and unwanted EDO, to f chop .Accordingly, the EDO is modulated from dc to f chop and ultimately becomes a square wave current flowing through R 1 .Therefore, the extracted dc component at the DSL requires an upconversion to f chop before the subtraction of EDO can take place.In CM-DSL, the upconversion can be done either by placing a chopper at the output of the loop or at the output of the integrator as depicted in Fig. 5(b) and (c), respectively.Therefore, there is a design choice on where the chopper should be placed.

III. NOISE ANALYSIS
Thermal noise and 1/ f noise are widely recognized as the most critical noise sources in CMOS low-noise amplifiers.In biosensing applications, the noise performance of the first amplifier in the front end plays a significant role in determining the overall system performance.As such, it is essential to accurately characterize and mitigate its noise sources.In this section, we will present a detailed theoretical analysis of noise performance in chopper-stabilized amplifiers which incorporates analog DSLs.We will investigate the effects of the DSL on the amplifier's noise performance and provide insights into design considerations for achieving optimal performance.

A. Effect of Chopping Modulation on the Amplifier's Noise
The noise model of a chopper instrumentation amplifier is depicted in Fig. 6.The noise of the amplifier is equivalently represented by the input-referred voltage source ( vn,IA ) in series and its input-referred current source ( în,IA = vn,IA ( jωC i )) in parallel to a noiseless amplifier.The total input-referred noise power spectrum density (PSD) is then calculated by Consequently, ( 7) can be rewritten as follows: where Z s is the source's impedance and C i is the input capacitance of the amplifier.At low frequencies, the first term in (7) dominates.Therefore, the input-referred noise PSD at low frequencies, where the noise contribution from the current noise i n,IA is negligible, can be rearranged to a thermal noise term S N 0 added to a low-frequency 1/ f noise term as given in (9) where f c denotes the noise corner frequency.The equivalent input noise is then amplified by the voltage gain, A 0 , and modulated with the output chopper.The output noise PSD is the summation of the replicas of the noise spectrum located at odd harmonic frequencies of f chop After chopping demodulation, the output signal spectrum is transposed to the baseband.Accordingly, the output noise at the baseband is crucial to the design.At the frequency band where f ≤ 0.5 f chop , (10) is nearly constant and can be approximated by a white-noise PSD [8] (11) where f −3 dB denotes the 3-dB bandwidth of the amplifier.From (11), it can be observed that the baseband noise level is approximately equal to the thermal noise, S N 0 , when f −3 dB is greater than the f chop .As a result, the chopper stabilization technique efficiently suppresses 1/ f noise.However, it comes with the trade-off of requiring a larger amplifier bandwidth, consequently leading to higher power consumption.modulation is ineffective in suppressing 1/ f noise from v n,INT as it is upconverted by CH DSL and downconverted again by CH out .Therefore, the derivation of output noise does not need to take the frequency modulation of choppers into account.By solving the KCL expression at the input node of the amplifier, the additional output noise resulting from v n,INT can be derived as follows:

B. Effect of DSL on Noise Contribution
where τ is the time constant of the integrator.The output noise can be referred to the input by dividing it by the voltage gain of the core amplifier, which is proportional to C in /C f .Consequently, the input signal is susceptible to the 1/ f noise generated by the integrator, and the extent of its impact depends on capacitor sizing.Fig. 7 also depicts the noise model of the CM-DSL in which the dc offset-induced current is compensated by the output current of the Gm 2 stage.As explained in Section II, the upconversion in the DSL can potentially occur at two locations as shown in Fig. 7(b) and (c), respectively.In topology I, the chopper is located at the output of the Gm 2 stage.The input-referred noise (v n,in ) of the integrator and the Gm 2 stage can be directly calculated by v n,in is then upconverted by CH DSL and downconverted by CH out , resulting in v n,in appearing at the output of the amplifier almost without attenuation at low frequencies.Consequently, 1/ f noise from both the integrator and the Gm 2 stage remains at low frequencies, resulting in a significant degradation in noise performance.Alternatively, the chopper can be placed between the integrator and the Gm 2 stage as shown in Fig. 7(c).Compared to CM-DSL topology I, the noise of the Gm 2 stage is only upconverted once by CH out in this topology.The equivalent input-referred noise of the integrator, the intermediate chopper, and the Gm 2 stage is derived by v n,in passes through the loop as described in (2), and its contribution to the output noise PSD is derived by modulating ( 14) with CH out and multiplying its NTF as follows: Similar to the chopper amplifier, CH out transposes the noise of the Gm 2 stage to the odd harmonics of f chop .As a result, the 1/ f noise is upconverted and not visible at baseband.Consequently, the noise of the Gm 2 stage at the frequencies of interest is mainly white noise.However, the integrator's noise is both upconverted and downconverted, resulting in the 1/ f noise and the dc offset of the integrator being present at baseband.The output PSD at baseband is approximated by where Z TIA is the effective transimpedance of the TIA stage.
It is worth noting that the noise below the cut-off frequency of the DSL loop, which is Gm 2 Z TIA /τ , is nearly unattenuated.Fig. 8 shows the comparison between CM-DSL topology I and II.Topology II takes advantage of the chopper for improving noise performance, especially the low-frequency noise.Nevertheless, according to the noise analyses of these two topologies, we can draw a conclusion that a CBIA cannot be fully free from 1/ f noise if a DSL is present.However, the noise can be reduced by the proper selection of circuit architecture, sizing of components, and biasing.So far, the noise contribution of the CM-DSL to the output noise PSD has been identified.For further noise optimization, we are interested in the contribution of the DSL's noise to the input-referred noise of the amplifier, especially at low frequencies where the 1/ f noise of the integrator dominates.The input-referred noise PSD is calculated as S 2 n,out (s)/H (s) 2 , where H (s) is the transfer function of the CBIA with DSL.At low frequencies where the loop gain of the DSL is much greater than 1, H (s) is inversely proportional to the gain of the DSL as we have derived in (1).Accordingly, the 1/ f noise components of the input-referred noise can then be calculated by The contribution of 1/ f noise is directly proportional to the ratio of Gm 2 /Gm 1 .Thus, it is desirable to minimize this ratio to optimize noise performance.However, Gm 2 is related to the loop gain of DSL and hence the attenuation of the EDO as given in (1).On the other hand, power consumption can be traded off for maximizing Gm 1 .It can be concluded that there are two design considerations for the design of CBIA with CM-DSL: 1) trade-off between noise and EDO attenuation and 2) trade-off between noise and power consumption.

IV. CIRCUIT DESIGN
To validate the analytical expressions and showcase the impacts of analog DSL on the noise performance of a chopper IA, the circuit architectures shown in Fig. 5 are implemented at transistor level in Cadence 1 Virtuoso 1 ADE.The circuits are implemented using a standard 180 nm CMOS process and are designed to fulfill typical specifications for biopotential acquisition systems while maintaining a low noise level.The circuit architectures and design methodology are presented to demonstrate a systematic design flow for noise optimization.Periodic steady-state (PSS) simulation and periodic noise analysis (Pnoise) are used to obtain the ac response and noise performance.All the simulation results are based on the same PSS analysis setup (shooting method with f beat = f chop and maxsideband = 20) for a fair comparison.

A. Design Specifications
Biopotential amplifiers must fulfill strict low-noise requirements and incorporate ac coupling characteristics in order to maintain the integrity of weak biopotential signals and to mitigate the EDO, which is on the order of tens of millivolt.Additionally, biopotential amplifiers need to meet certain criteria to avoid corrupting the signal.First, the amplifiers should provide sufficient voltage gain such that biopotential signals are at a measurable level.Second, biopotential signals are weak in comparison to unwanted common-mode signals such as power line interference and motion artifacts.These ones 1 Registered trademark.

TABLE I
TARGET SPECIFICATIONS can overwhelm the desired signal, and therefore, high CMRR is a critical performance metric.The amplifiers should also present high input impedance to minimize the loading effect on the electrode and skin-electrode interface.For instance, the impedance of wet Ag/AgCl electrodes can be 350 k ∥25 nF, while metal plate electrodes can have an impedance as high as 1.3 k ∥12 nF [27].From the system point of view, high input impedance helps mitigate the effect of electrode impedance imbalances ( Z e ), thereby improving the overall CMRR which is given by [28] CMRR sys ≈ −20 log Z e Z in,CM + 1 CMRR Amp (18) where Z in,CM and CMRR Amp represent the common-mode input impedance and amplifier's CMRR, respectively.Last but not least, the design requires low power consumption and small size in order to be amenable for wearable and portable applications that feature multichannel signal recording.Table I summarizes the general specifications of biopotential recording systems [29], [30], which also serve as the design target for implementing the above-mentioned circuit architectures.

B. Design Considerations
Based on the theoretical analysis conducted in Sections II and III, it has been shown that an analog DSL improves the EDO tolerance and rejects low-frequency varying offset by creating an ac-coupling characteristic.However, it requires additional hardware which takes up silicon area, consumes power, and can also become a considerable noise contributor.An analog design octagon [31] as shown in Fig. 9, which is specific for the design of the biopotential chopper IA with DSL, is used to cope with all the design trade-offs.

C. Circuit Design of a Chopper CCIA With VM-DSL
The circuit implementation of a chopper CCIA with a VM-DSL comprising a core amplifier, choppers, a capacitor negative feedback loop, and a DSL is shown in Fig. 10.Detailed device parameters and transistor dimensions are available in Table II.The core amplifier is implemented using a folded-cascode amplifier, which is followed by a common-source output stage.The design of the folded-cascode amplifier focuses on noise optimization as it provides the first-stage amplification.On the other hand, the output stage aims for handling a large voltage swing.The noise of this    10 stage is mainly coming from M P1 -M P2 , M N 1 -M N 2 , and M P4 -M P5 .The cascode transistors do not contribute to noise.The input-referred noise can be calculated by where v 2 n is the input-referred noise power spectral density of a MOSFET as given by [32]: for transistors in strong inversion, and for transistors in weak inversion, where γ ≈ 2/3 is the coefficient in strong inversion, f c is the noise corner frequency, q is the electron charge, I D is the drain current, V T is the thermal voltage (V T ≈ 26 mV at room temperature), and n ≈ 1.5 − 2 is the subthreshold slope factor.v 2 n contains a bias-dependent thermal noise and area-dependent flicker noise, resulting in design trade-offs between noise and power/area.According to (19), the input differential pair is crucial for noise optimization.In this design, input transistors M P1 and P2  operate in the weak-inversion in order to achieve low-power consumption while maximizing g m /I DS ratio.M N 1 -M N 2 and M P4 -M P5 operate in strong inversion in order to minimize g m, p4 /g m, p1 and g m,n1 /g m, p1 ratios.A detailed design strategy of noise optimization for folded-cascode OTA is out of the scope of this study and has been thoroughly discussed in [33].
The actual noise corner frequency f c of the core amplifier is obtained through a noise simulation.Fig. 11 shows that f c is around 1 kHz and the amplifiers achieve an input referred noise of 65 nV/ √ Hz while consuming only 1.6 µA from VDDA.The 1/ f noise is the primary noise contributor within the bandwidth from 1 to 100 Hz as shown in the noise breakdown.To effectively transpose the 1/ f noise to high frequencies, choppers (CH in and CH out ) are applied to the CCIA and the relationship between the simulated integrated input-referred noise and the chopping frequency is shown in Fig. 12.A chopping frequency of 5 kHz is selected as only very modest improvement is achieved for higher frequencies at the expense of much higher power consumption.The simulated noise level and the noise breakdown that corresponds to a chopper CCIA with a chopping frequency of 5 kHz are presented in Fig. 13.
As described in Section III, the noise contribution of VM-DSL is inversely proportional to the value of C in .Fig. 14 presents a circuit simulation result that demonstrates the relationship between total noise and C in .Consequently, a large C in is desirable for noise optimization.In addition, large capacitors are less prone to mismatches, resulting in a higher CMRR.However, these capacitors require considerable silicon area and also degrade the input impedance.In this design,  C in is 9 pF so that an input impedance higher than 10 M is achieved with enough margins while achieving the target noise level and CMRR.The value of feedback capacitors is then calculated as 90 fF to provide a 40 dB amplification.The selected value of C hp is 500 fF in order to provide a maximum EDO tolerance of around 100 mV.The high-pass and low-pass cutoff frequencies are determined by the unit-gain bandwidth of the integrator and the value of Miller capacitor C c , respectively.The integrator is implemented using an area-efficient pseudoresistor-based active RC integrator to achieve a very large time constant, and therefore, an extremely low high-pass cutoff frequency while allowing on-chip integration [34].Fig. 15 shows the layout implementation of the chopper CCIA with VM-DSL.Fig. 16(a) and (b) presents simulation results of ac characteristics and CMRR, respectively.This design meets the specifications by providing 40 dB amplification within the 1 Hz to 1 kHz range, while also maintaining a low noise level and achieving a CMRR of 106 dB.

D. Circuit Design of a Chopper CBIA With CM-DSL
Fig. 17 presents the circuit implementation of a chopper CBIA with CM-DSL.The core amplifier is composed of a transconductance stage and a transimpedance stage.Detailed device parameters and transistor dimensions are available in Table III.The input differential signal is sensed by the source degeneration resistor R 1 , resulting in a signal-dependent current that is translated to output voltage through the impedance R 2 ||C 1 .Therefore, the voltage gain of the core amplifier is Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.accurately defined by where K 1 is the current mirror ratio, which is 0.4 in this design to reduce the current consumption.The input-referred noise of this circuit architecture is derived by The noise level is mainly dominated by the input differential pair and the thermal noise of R 1 .To minimize the noise contributed by other devices, the trade-off can be made between current consumption and g m, p1 .From a noise performance point of view, the value of R 1 should be minimized.However, R 1 is also related to the maximum EDO tolerance as calculated in (5).Consequently, the choice of R 1 requires a compromise with power consumption.In this implementation, the value of R 1 and the biasing current for the input pair are chosen as 25 k and 2.5 µA such that they approximately have the same thermal noise contribution as calculated by The value of g m /I DS is around 21 when the pMOS is working in the weak-inversion region in this CMOS technology.
To provide a 40 dB amplification, the value of R 2 is then determined to 6.25 M .Next, a noise simulation is conducted in order to find the 1/ f corner frequency f c and select the chopping frequency.The chopping frequency is selected as 5 kHz to make the 1/ f noise negligible within the signal bandwidth.
The CM-DSL contains an integrator to extract the dc component of the output and a transconductance stage to perform the current-to-voltage conversion.The design of CM-DSL is critical to define the high-pass cutoff frequency, EDO tolerance, and also noise performance.The implementation of the integrator is the same as the one used previously in the VM-DSL.The transconductance stage is implemented using a source-degenerated differential amplifier to accurately define its equivalent G m by the choice of R 3 .Its output stage is designed to provide a maximum I DSL of 2 µA to achieve around 50 mV EDO tolerance.In this architecture, the highpass cut-off frequency is determined by Therefore, the time constant of the integrator and the value of R 3 require proper sizing in order to reach very low cut-off frequencies.
As described in Section II, there are two possible topologies that can be implemented: topology I by placing CH DSL at the output of the DSL (green chopper), or topology II by placing CH DSL at the intermediate point between the integrator and the transconductance (brown chopper) as shown in Fig. 17.To demonstrate the impact of the placement of the chopper, Fig. 18(a) shows three different Pnoise simulations that were performed on this amplifier: first the chopper was totally deactivated, then chopper was connected as in topology I, and finally the chopper was connected as in topology II.Fig. 18(b) presents the total input-referred noise within 1 to 100 Hz bandwidth of each topology and also compares the corresponding noise breakdown.The noise of the amplifier without chopping modulation is relatively high in the low-frequency range due to the 1/ f noise from both the CBIA and the CM-DSL.In this design, the noise can be reduced by around 36% when the chopping technique is applied to the CBIA and the CM-DSL is Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.configured as topology I.In this topology, the 1/ f noise of the CBIA is suppressed significantly because of the upmodulation process, but the 1/ f noise of the Gm 2 stage and the integrator within the feedback loop still remain at low frequencies.In order to further improve the noise performance, the chopper in the DSL is placed in front of the Gm 2 stage as shown in the circuit topology II.As we have derived in (16), the 1/ f noise of the Gm 2 stage is not visible at baseband by using topology II, and therefore the major 1/ f noise contributor is from the integrator.The primary noise contributor is the thermal noise, which can be further reduced by increasing biasing current.As a result, an additional 49% reduction in total integrated noise is reached under the condition that identical circuit blocks are used.According to this comparison, topology II is chosen in this design as it offers the lowest noise level.
It can be observed from the noise breakdown that the 1/ f noise of the integrator becomes a critical noise contributor in topology II.For further noise optimization, it is of great importance to understand how this noise source affects the overall noise level.As we have derived in (17), the extent of the impact of the integrator's noise on the total noise is related to the transconductance of the Gm 2 stage.Fig. 19 presents a circuit simulation result that shows the relationship between the total input-referred noise and Gm 2 by sweeping the value of R 3 .Due to the fact that Gm 2 = K 2 /R 3 , it is desired to maximize the value of R 3 for better noise performance at the expense of area.However, in this case, only marginal improvement can be obtained when the Gm 2 is less than 10 µS.Considering the area-noise design trade-off, the Gm 2 stage is designed to offer a transconductance of 10 µS for reaching a better area efficiency.Fig. 20 shows the layout implementation of a chopper CBIA with CM-DSL.Finally, Fig. 21 presents the ac response, noise performance and CMRR, respectively.It can be seen that this architecture also offers   performance metric to compare the noise performance of an amplifier.NEF is defined as [25] where V rms,in is the total input-referred noise rms value within the bandwidth, I tot is the total current consumption, V T is the thermal voltage, K is Boltzmann's constant, T is the absolute temperature, and BW is the 3 dB-bandwidth of an amplifier.This factor reflects how closely the amplifier approaches an ideal BJT, which has a NEF of 1.Compared to CM-DSL, VM-DSL implementations generally exhibit higher NEF since they do not require an additional transconductance stage for EDO subtraction.The additional transconductance adds current consumption which is proportional to the amplitude of the EDO.For this reason, the EDO tolerance is typically limited to tens of millivolt.To address this issue, a dual-branch current-feedback CBIA [35] has been proposed to offer a wider range of EDO tolerance.The major drawback of the VM-DSL is the necessity of a relatively large capacitor which is not amenable to integration in systems that require multiple recording channels.For this reason, the number of channels is commonly less than eight in system-on-chip (SoC) designs unless special multichannel multiplexing techniques such as digitally assisted time-division multiple access (TDMA) [36] and dual-channel charge recycled (DCCR) [37] are utilized to share hardware.
Although chopping helps attenuate 1/ f noise, it effectively reduces Z in owing to the switched-capacitor resistor formed by the input chopper and the large-value input capacitors.As a result, Z in is commonly less than 10 M in chopper VM-DSL architecture, which is acceptable for general biosensing applications over the skin where relatively large electrodes are used, but it may not be acceptable in deep brain recording implants [38].Consequently, additional circuit techniques that boost the input impedance may need to be applied in order to mitigate the loading effect and also achieve the required CMRR performance [3], [4], [5], [6], [13], [14], [15].
In contrast, CM-DSL can easily achieve higher CMRR and be more robust against device mismatch due to the fact that it does not depend on the matching of passive devices.Additionally, the input impedance is not severely affected by the chopper, therefore making it suitable as an interface with a broad type of electrodes without the need for an additional input impedance boosting circuitry.However, it is crucial to investigate the noise contribution from the DSL as it may have a considerable contribution to the total noise at low frequencies.Therefore, its noise modeling and mitigation strategies are important for circuit design.In particular, the exact placement of the chopper within the DSL is of paramount importance as significant noise reduction can be achieved.

VI. CONCLUSION
This article has presented a comprehensive noise analysis and modeling of two circuit architectures extensively used in biopotential acquisition front-ends: the chopper-based charge-balancing IA with current-mode DSL and the chopper-based capacitively coupled IA with voltage-mode DSL.Our investigation has specifically focused on the impact of analog DSL implementations on noise performance, and we have presented and discussed the associated design considerations and trade-offs.Furthermore, we have proposed a design methodology for noise optimization, which we have successfully applied in two example circuits designed in 180 nm CMOS.The simulation results, after parasitic extraction, show that these circuits have the potential to achieve similar or even better performance than the prior art.These results provide strong evidence that the proposed noise modeling and design methodology can be effectively employed in the development of fully integrated, low-power, low-noise biopotential amplifiers.

Manuscript received 23
March 2023; revised 4 August 2023 and 25 August 2023; accepted 11 September 2023.Date of publication 9 October 2023; date of current version 29 December 2023.This work was supported in part by the Swedish Foundation for Strategic Research (SSF) under Project ITM17-0079 and in part by the Region Stockholm under Project HMT FoUI-979040.(Corresponding author: Yu-Kai Huang.)

Fig. 7 (
Fig. 7(a) shows the noise model of the VM-DSL employed on a chopper CCIA.In this architecture, the input-referred noise of the integrator, v n,INT , is the only noise contributor from the DSL loop.It can be observed that the chopper

Fig. 9 .
Fig. 9. Design octagon that illustrates the trade-offs in the design of chopper IA with analog DSL.(a) Chopper CCIA with VM-DSL.(b) Chopper CBIA with CM-DSL.

Fig. 12 .
Fig. 12. Relationship between total input noise and f chop .

Fig. 14 .
Fig. 14.Relationship between total input noise and C in .

Fig. 16 .
Fig. 16.Simulation results of chopper CCIA with VM-DSL.(a) Input-referred noise and ac response.(b) Histogram of the CMRR over process and device mismatch.

Fig. 18 .
Fig. 18.Simulated noise performance of CBIA with CM-DSL implemented using different topology.(a) Input-referred noise.(b) Total input-referred noise and noise breakdown.

Fig. 21 .
Fig. 21.Simulation results of chopper CBIA with CM-DSL.(a) Input-referred noise and ac response.(b) Histogram of the CMRR over process and device mismatch.

TABLE II DEVICE
PARAMETERS AND DIMENSIONS OF TRANSISTORS IN FIG.

TABLE III DEVICE
PARAMETERS AND DIMENSIONS OF TRANSISTORS IN FIG. 17

TABLE IV PERFORMANCE
SUMMARY AND COMPARISON WITH PRIOR ART BIOPOTENTIAL AMPLIFIERS Fig. 19.Relationship between total input noise and Gm 2 .