A 0.3-V 8.5-µ A Bulk-Driven OTA

—A bulk-driven operational transconductance amplifier (OTA) suitable for ultralow-power and ultralow-voltage applications is described. The amplifier exploits local positive feedback in the first stage to increase its transconductance. The OTA entails a single Miller capacitor for frequency compensation, thus saving area occupation and improving frequency performance. As a distinctive feature of the proposed solution, the OTA is stable for capacitive loads higher than 5 pF. Implemented in a 65-nm standard CMOS technology, the proposed solution occupies an area of 10.6 · 10 − 3 mm 2 and is powered from 0.3 V, with a total quiescent current equal to 8.5 µ A. Experimental measurements show a gain–bandwidth (GBW) product of 1.65 MHz (0.81 MHz) with a phase margin (PM) equal to 70 ◦ (71 ◦ ) when driving a 50-pF (150-pF) load, featuring the best figures of merit compared to other multistage sub-1-V OTAs in the literature.


I. INTRODUCTION
A major trend in the current electronics industry is the extension of battery life in portable devices through the adoption of ultralow-power design techniques.This has reinforced interest in the development of low-voltage, low-current design approaches.By limiting power consumption is in fact possible to reduce the size of the battery (and consequently the overall volume of the device), thus ensuring the same device lifetime.This latter aspect is especially critical for implanted biomedical devices, where a reduced system volume is desirable to limit invasiveness [1].
Considering CMOS technology, the most widely adopted methodology for enabling analog circuits with low-voltage and lowcurrent capabilities is subthreshold biasing, also known as weak inversion biasing.For example, through this approach, excellent operational transconductance amplifier (OTA) topologies have been implemented [2], [3], [4], [5].These solutions allow supply voltages from around 1-0.5 V, but with limited input common-mode swing.
To enable bulk driving, the MOSFET gate must be biased to form a conduction channel inversion layer, and the drain current is modulated by varying the bulk voltage through the body effect.In fact, bulk-driven stages allow minimum supply with wide input ranges, Andrea Ballo, Alfio Dario Grasso, and Salvatore Pennisi are with the Dipartimento di Ingegneria Elettrica Elettronica e Informatica (DIEEI), University of Catania, I-95125 Catania, Italy (e-mail: andrea.ballo@unict.it;alfiodario.grasso@unict.it;salvatore.pennisi@unict.it).
Giovanni Susinni is with Eda Industries S. including rail-to-rail, and are particularly effective under very lowvoltage supply, where the forward biasing of the body-source junction cannot exceed 0.4 V, thus limiting the forward body current in the range of a few picoamperes.However, compared with conventional gate-driven circuits, body-driven counterparts are characterized by lower voltage gain and/or gain-bandwidth (GBW) product, because of the limited value of bulk transconductance, g mb , which is only about 10%-20% of the gate transconductance, g m [21].
To overcome some of these limitations usually found in a conventional body-driven OTA, we present in this brief, a novel three-stage OTA.The main features of the proposed circuit can be summarized as follows.
1) It exploits local positive feedback within the first stage to improve its equivalent transconductance.2) Three cascaded gain stages are adopted to further increase the dc gain, and unlike previous solutions, a single Miller capacitor is successfully exploited to implement frequency compensation, thus reducing the overall area occupation and maximizing GBW under a given standby current.3) Class AB operation of the last stage increases slew rate (SR) performance and current driving capability.4) A better common-mode rejection ratio (CMRR) with respect to a previous similar high-performance solution [10] is also inherently achieved by the proposed topology.The OTA is designed and fabricated using a standard 65-nm CMOS technology.It can operate under a 0.3-V supply and provides a dc gain around 40 dB.Compared with other sub-1-V experimental solutions in the literature, the proposed one offers significant improvements, especially when considering area occupancy and GBW, reflected in the best figures of merit achieved by a body-driven OTA.
Some preliminary results of the proposed OTA have already been presented by the authors in a national conference [22].In this work, the theoretical analysis is extended to include the effects for high capacitive loads.Moreover, extensive simulations, including corner and Monte Carlo analysis, and additional experimental results are provided.

A. Topology, Operating Point, and Large Signal Operation
The simplified schematic of the proposed OTA is depicted in Fig. 1.The circuit relies on a bulk-driven nontailed differential pair M1-M2, whose gate voltage, V A , is set by M13 and current generator I B [10].Note that transistors M1 and M2 are thick oxide transistors, showing a higher value of the body effect parameter.Transistors M3 and M4 with resistors R A and R B implement the load of the differential pair.The body and drain terminals of M3 and M4 are cross-coupled as discussed in [23] for a gate-driven OTA.The provided positive feedback increases the differential input stage transconductance, as will appear clear in the following.The bias current of M1-M2 is accurately set by the current mirror ratio (W /L) 1,2 /(W /L) 13 (where W /L is the MOS transistor aspect ratio), provided that the bulk voltage of M1, V CM , is equal to the commonmode input voltage (v Considering that no current flows through R A and R B at dc, the drains of M3-M4 are at the same potential of their gates, i.e., they This work is licensed under a Creative Commons Attribution 4.0 License.For more information, see https://creativecommons.org/licenses/by/4.0/Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.act as diode-connected transistors.Therefore, transistors M6 and M8 have the same source-gate voltage of M3 and M4, to which we refer to as V SG .Since the threshold voltage of a pMOS is expressed by where V T 0 is the zero-bias threshold, ϕ F is the Fermi potential, γ is the body effect parameter, and V SB is the source-bulk voltage, hence, neglecting the channel length modulation and assuming operation in saturation, and the dc current ratio I D6,8 /I D3,4 is where V SB = V SG was set for M3 and M4, due to the topological symmetry.As a result, the current mirror ratio in ( 2) is lower than that of a conventional current mirror, in which the factor in the square brackets equals 1.In other words, if (W /L) 6,8 = (W /L) 3,4 is set, I D6,8 < I D3,4 is obtained.
As far as I D11 is concerned, it stands in a current mirror ratio with I D8 and sets the quiescent current in the output stage (M12) through the current mirror M9-M10.Class-AB operation of the last stage is ensured by M11 and M12 for sinking and sourcing output current, respectively.

B. Small-Signal Analysis
Similar to what was demonstrated in [10], the first stage exhibits a differential output behavior, even though the input voltage is applied only to the bulk of M1 (or equivalently to the bulk of M2).In addition, the differential-mode transconductance of the first stage is enhanced by the positive feedback of the bulk-drain cross-connection of transistors M3 and M4.This can be demonstrated in the same way as was done in [23], which analyzed a gate-driven cross-coupled input stage.The (unbalanced) differential gain of the first stage, A 0,1 , is hence given by the equivalent transconductance multiplied by the equivalent output resistance and results to be where g mb1,2 and g mb3,4 are the bulk transconductance of transistors M1-M2 and M3-M4, respectively, and r o1 is the parallel of r d1,2 and r d3,4 .Care must be taken during the design phase, so that the denominator of (3) is always positive in all the process corners and temperature values.In conclusion, the gain increase is achieved by setting the denominator of (3) less than 1, but close to 1.The overall OTA differential gain is given by where r o2 and r o3 are the output resistances of the second stage, equal to r d7 //r d8 and of the third stage (the main output), equal to r d10 //r d12 , respectively.
One of the main limitations of [10], of which this solution is an improved version, was the low CMRR, expressed by 1/2 g m3,4 R A,B , and that resulted in the range of a few decibels.In the proposed topology, CMRR is enhanced due to both the increased inputstage differential gain given by (3) and the differential to single ended conversion operated by current mirror M5-M7, not present in [10].In fact, under perfect symmetry conditions (i.e., with the same common-mode currents generated by M6 and M8 and a unity current gain of M5-M7), the common-mode gain ideally nullifies.This condition requires that the drain voltages of M6 and M8 (and of course of M5 and M7) must be equal, yielding Such a condition nullifies systematic offset as well.Unfortunately, ( 5) is hardly met due to different pMOS and nMOS threshold voltage constraints and variations with process and temperature; therefore, a nonnegligible common-mode gain will still be present in an actual implementation.
Among the possible frequency compensation strategies, single Miller approach is exploited [24].In particular, the frequency compensation is achieved through the Miller capacitor C C connected between the output and the drain of M3.This is the first time that this type of compensation is successfully exploited in a body-driven OTA.
Denoting by c o2 the parasitic capacitance at the output of the second stage and by C L the loading capacitance (not shown in Fig. 1), small-signal analysis reveals that the open-loop transfer function can be approximated as where A 0 is the same as in (4), and the other parameters are given in the following: Note that the two last zeros and pole (all real) can be neglected because they depend on parasitic capacitances much lower than C L and C C , and hence, their values are at a frequency much higher than the GBW product, which, from ( 4) and (7), is expressed by It should be observed that ( 14) reduces to the usual expression G mb /C C for C L ≪ g m6,8 g m12 (R//r o2 )r o2 .However, for C L ≫ g m6,8 g m12 (R//r o2 )r o2 , the GBW reduces with increasing values Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply. of C L .Again, the positive feedback enhancing G mb is found beneficial also to improve GBW.

TABLE I TRANSISTOR ASPECT RATIOS AND CIRCUIT PARAMETERS
The evaluation of the phase margin (PM), yields

III. DESIGN AND SIMULATION RESULTS
The OTA in Fig. 1 was designed using a standard 65-nm CMOS technology provided by STMicroelectronics.The above equations were also considered during the design steps.Table I shows the main transistor aspect ratios and circuit parameters.The supply voltage, V DD , is 0.3 V (V SS = 0 V) and the total current consumption is 8.5 µA.It is seen that g mb3,4 R A,B //r o1 is about 0.36 providing a 1.56 boost in the transconductance, as anticipated by (3).
Assuming a load capacitance equal to 50 pF, the required value of C C to get a PM of 70 • is equal to only 470 fF.
Fig. 2(a) shows the simulated bode plot of the open-loop gain at various capacitive loads.As predicted by (14), GBW does not depend on C L for C L ≪ g m6,8 g m12 (R//r o2 )r o2 ≈ 58 pF.This result is confirmed by Fig. 2(b), where the PM, gain margin (GM), and GBW are simulated versus C L .As a distinctive feature of the

TABLE III CORNER AND MONTE CARLO (1000 ITERATIONS) ANALYSIS RESULTS
FOR T = 27 • C (TT CORNER) proposed solution, the OTA a PM higher than 72 • for any capacity load.However, stability is reduced for low value of C L due to reduced GM, which is caused by the reduction of the damping factor of complex and conjugate poles.Consequently, the amplifier is stable for capacitive loads greater than about 5 pF.The simulation of the input-referred noise shows a value of the white noise equal to 250 nV/ √ Hz with a corner frequency value of about 10 µV/ √ Hz.The robustness of the OTA against process and temperature variations has been assessed through extensive corner analysis.The results are summarized in Tables II for the various transistor corners and at −10 • C, 27 • C, and 85 • C, assuming C L = 50 pF.The amplifier is apparently stable in all cases.
Additional analyses were executed considering a ±10% variation of the power supply, confirming the robustness of the OTA.
Finally, 1000 Monte Carlo simulations have been executed, and the results are summarized in Table III, showing a relative standard deviation lower than 20% in all cases.The same parameters for C L = 150 pF are equal to 0.17/−0.07V/µs and 0.62/1.26µs.The maximum input current when a 300-mV pp step is applied is equal to about 600 nA.

IV. EXPERIMENTAL RESULTS
The experimental characterization of the OTA for lower capacitive loads was not possible due to the loading effect of the package, test PCB, and probes, which accounts for a parasitic load almost equal to 50 pF.
Six different samples have been experimentally characterized, and the mean values of the main amplifier performance metrics are summarized in the last column of Table IV, which compares the proposed solution with other recent multistage sub-1-V OTAs.The proposed solution has the lowest area consumption, operates under one of the lowest supply voltages, and can drive the largest load capacitor with one of the best GBW achieved.
The traditional figures of merit, whose expressions are reported at the bottom of Table IV, are adopted to compare the different amplifiers.It can be noted that other solutions exhibit a higher value of IFOM L than the proposed OTA (namely, [10], [11], [12] for C L = 50 pF and [11], [12] for C L = 150 pF), whereas IFOM S is higher  than the other solutions by 4.5× and 6.6× for C L equal to 50 and 150 pF, respectively.
Moreover, when IFOM AS and IFOM AL are considered, the proposed OTA exhibits an improvement equal to about 13× and 1.5× for C L = 50 pF and 20× and 3× for C L = 150 pF, when compared to the other solutions.As a main drawback, the lowest dc gain is displayed by the proposed OTA.

V. CONCLUSION
A bulk-driven three-stage OTA exploiting positive feedback and a single Miller capacitor has been proposed and experimentally validated.The solution can work under a 0.3-V supply and exhibits class AB operation, amenable to drive a 50-pF load with an SR of 0.18 V/µs and a GBW of 1.65 MHz.The proposed OTA is a good candidate for area-constrained ultralow-voltage, ultralowpower applications, such as wireless sensor nodes and implantable biomedical devices.The adoption (apart from M1-M2 and M13) of transistors of the digital core of the design kit has led to a dc gain equal to 38 dB, due to the reduced intrinsic output resistance offered by these devices.However, additional circuit techniques relying on local positive feedback can be adopted to increase the gain as those proposed in [14], [15], and [16].Moreover, the lack of a tail current generator for the first stage leads to reduced values of power supply rejection ratio (PSRR) and CMRR, which, nevertheless, still offer acceptable values.The proposed OTA can be exploited in all the applications requiring sub-0.5-Vsupply and rail-to-rail input operation, like IoT nodes directly powered by single silicon solar cells.

Fig. 2 .
Fig. 2. Simulated (a) ac response at different load capacitor values and (b) PM, GM, and GBW product versus load capacitor.

Fig. 3
Fig. 3 depicts the layout of the OTA superimposed to the chip microphotograph.The occupied area is 10.6 • 10 −3 mm 2 .Fig. 4(a) and (b) shows the measured open-loop frequency response for C L = 50 pF and C L = 150 pF, respectively, of one of the fabricated prototypes.The dc gain is around 40 dB and GBW is

Fig. 4 .
Fig. 4. Measured bode diagram of the OTA loop gain with (a) C L = 50 pF and (b) C L = 150 pF.

Fig. 5 .
Fig. 5. Measured step response in unity gain configuration with (a) C L = 50 pF and (b) C L = 150 pF.

TABLE IV SUMMARY
OF MEASURED PERFORMANCE METRICS AND COMPARISON WITH OTHER MULTISTAGE EXPERIMENTALLY TESTED SUB-1-V OTAS