<inline-formula><tex-math notation="LaTeX">$V$</tex-math></inline-formula>- and <inline-formula><tex-math notation="LaTeX">$W$</tex-math></inline-formula>-Band Millimeter-Wave GaN MMICs

This paper gives an overview of published results with GaN MMICs for millimeter-wave front ends at frequencies above 60 GHz, including power and low-noise amplifiers, switches, phase shifters, frequency multipliers and oscillators. Some design methods and demonstrated experimental results obtained at W band from MMICs fabricated in a 40-nm GaN on 50--<inline-formula><tex-math notation="LaTeX">$\mu$</tex-math></inline-formula>m SiC process are then presented. These include 75 to 110 GHz power amplifiers with 20–27 dBm output power and 10–17 dB gain, switches with 2 dB insertion loss and 20 dB isolation, and continuous phase shifters with 2–11 dB loss and 0<inline-formula><tex-math notation="LaTeX">$^\circ$</tex-math></inline-formula>–90<inline-formula><tex-math notation="LaTeX">$^\circ$</tex-math></inline-formula> of tunable phase shift. Additional MMICs include frequency doublers and triplers, oscillators, circulators and mixers, designed for higher levels of on-chip integration towards a W-band front end.

There are a number of new applications under development at W-band, e.g. industrial vibrometry [21], and CW radar are shown for measuring human respiration and heartbeat [22], while other medical applications include imaging of burns [23], and in biology research W-band radar was used to detect insect wing-beat frequency for observing migrations [24].
High attenuation of the atmosphere and lack of devices that can generate the required power results in limited use of the higher part of the millimeter-wave spectrum. Solidstate power amplifiers (PAs) are limited in total output power, bandwidth, and efficiency, and are expensive due to the need for power combining and low-loss packaging of the analog front end. Although silicon-based circuits have shown high-frequency operation with medium level power from power-combined devices, for watt-level power, III-V semiconductors are needed. High-performing 0.1-μm gate length pseudomorphic InGaAs high electron mobility transistors (HEMT) processes developed in the 1980s [25] allowed a path for millimeter-wave solid-state systems operating at W-band with various front-end MMIC circuits. Innovative techniques in spatial power combining were introduced using GaAs technology, where traditional binary corporate combining became limited by loss. For example, at 61 GHz, a 16×17 lens array using a total of 272 GaAs MMICs achieved a total of 36 W [26]. These developments quickly found their place in commercial and defense industry ranging from airborne and ground-based radars, satellite communications, to missile terminal guidance phase decoys, many of which still remain GaAs-based systems due to the robustness offered by the technology. With research at the turn of the century bringing wide band-gap semiconductors to the stage, gallium-nitride (GaN) has been improving high-frequency performance with operating frequencies in the hundreds of GHz [27], [28]. Fig. 2 shows a useful qualitative comparison of different semiconductor technologies as a function of f T and f max up to 1.5 THz. A number of recent millimeter-wave GaN processes with gate lengths in the 20-90 nm range have shown high performance across V and W bands [29], [30], [31], [32]. In this paper, we give an overview of published results for various GaN MMICs at frequencies above 50 GHz, followed by a more detailed description of various current W-band front-end MMIC designs in the HRL 40-nm technology. Section II reviews published power amplifier GaN MMICs, followed by GaN control circuits such as switches and phase shifters, as well as frequency generation and translation MMICs. Section III describes the design process for three W-band GaN MMIC PAs with on-chip power combining. Sections IV and V focus on control circuits, with switches and continuous phase shifter MMIC design and measurements. Section VI gives a brief overview of an oscillator circuit and several frequency multipliers. Finally, Section VII gives some additional W-band MMIC examples and points to future directions.

II. REVIEW OF V-AND W-BAND STATE-OF-THE-ART GAN MMICS
Various GaN processes on either SiC or Si substrates currently achieve cutoff frequencies above 150 GHz. While SiC as a substrate offers better thermal properties, Si offers lower cost and potential of integration with other electronics. As examples, an f T up to 275 GHz is shown in a 40-nm GaN on SiC HEMT process [30], and f T = 170 GHz in a GaN on Si process in [32]. Breakdown voltages beyond 20 V while operating in the hundreds of GHz range allow these device to achieve high output powers [27]. Power densities as high as 3 W/mm are shown at W-band in GaN on SiC [30], and 2.5 W/mm with 8.5 dB of gain at 94 GHz with a 10 V supply voltage in a 40-nm GaN on Si process [32]. Device efficiency is also increasing at W band, with 45% PAE reported for a 3 W/mm high power device at 94 GHz, while the same device can reach 56% PAE with an output power density of 780 mW/mm [30]. Advanced GaN processes also present minimum noise figures below 2 dB in V and W bands for low noise designs in 40 nm and 90 nm GaN on SiC processes [29], [30]. The ability to design with multiple gate lengths allows for increased complexity, such as low noise/high gain stages followed by high linearity stages in a single LNA [33].

A. V-AND W-BAND GAN MMIC PAS
The general challenges for W-band high-power solid-state transmitters are achieving high output power (ERP) in a small footprint and with reasonable efficiency. Ultra-high power vacuum tubes have been demonstrated to generate several hundreds of kW at W-band, e.g. [34], but suffer from narrow bandwidth and require large high-voltage power supplies and magnets to operate. The wide bandgap of GaN and high associated operating voltages make it the semiconductor of choice for high-power solid-state transmitters. The SiC substrate additionally offers good thermal properties compared to GaAs and Si. The highest published solid-state W-band transmitter produces around 6.8 kW and is intended for an active denial weapon [35]. The transmitter spatially coherently combines 8,192 GaN-on-SiC MMIC PAs, each with over 1 W of power and PAE > 20% around 93 GHz. This approach is modular and therefore scalable, with high demonstrated power-combining efficiency.
Various GaN power amplifiers at V and W bands have been demonstrated. State-of-the-art published results are summarized in Tables 1 and 2 for narrowband and broadband performance, respectively. Power levels as high as 37 dBm with 18.3% efficiency are reported for a power-combined amplifier over a narrow 7% bandwidth at 95 GHz in a 100-nm process [43]. On the other hand, a 44% bandwidth from 70-110 GHz with 26 dBm peak power and a gain of 16±2 dB is shown in [48]. Broadband amplifier design is challenging because of stability and the fundamentally lower efficiency, output power and gain compared to narrowband designs. Fig. 3 shows a summary plot of achieved measured output power over frequency across W band, with photos of the MMIC PAs. Broadband power combining of watt-level MMICs to achieve 37 W from 75-100 GHz is shown in [51].

B. V-AND W-BAND GAN LOW-NOISE AMPLIFIERS
The wide bandgap and operating voltages of GaN HEMTs make them attractive for power amplification, while the noise  performance of GaN low-noise amplifiers (LNAs) display competitive noise figures with other technologies. Additionally, these technologies come with the comparative advantage of high linearity and high power handling. Table 3 summarizes state-of-the-art published GaN MMICs operating within V and W bands . The lowest noise figure of 1.8-2.4 dB is reported in the wideband four-stage design of [53] using the advanced 40 nm T-gate device process, the lowest gate width of all reported GaN LNAs. Another wideband five-stage LNA is also reported in this paper. Furthermore, a five-stage balanced LNA in the same process is presented in [54] with similar bandwidth and gain as in [53], but with greater linearity over input power and less overall power consumption. A four-stage LNA is published in [55] using a 70 nm gate process which reports low noise figure between 2.8 and 3.3 dB.

TABLE 3. Comparison of V -and W -Band GaN LNAs
As the device gate lengths increase and the transistors operate towards their upper frequency limit, reported noise figure trends upward and bandwidth decreases. The dual band design in [56] operates with noise figures of 3.5-4.2 dB and 3.3-3.8 dB for the respective 75-83 GHz and 91-96 GHz bands. The remaining circuits [57], [58], [59], [60] are designed in 100 nm GaN processes. The LNA in [59] is noteworthy for having the highest gain of all the tabulated millimeter wave GaN LNAs, and being the only cascode design, which takes additional stability considerations. Finally, [60] reports the only GaN on silicon substrate LNA with the goal of providing a lower cost circuit, but at the expense of its thermal properties compared to SiC. With the promising noise performance demonstrated to date, challenges remain in noise characterization at higher frequencies and lower noise figures.

C. CONTROL, FREQUENCY GENERATION AND TRANSLATION V-AND W-BAND GAN MMICS
Isolating the transmit and receive path of a transceiver is an essential function for front ends. Active circulators are a promising alternative to ferrite devices and provide the potential for gain in the transmit and receive paths of full-duplex front ends. These have been demonstrated across X-band in a GaAs MMIC [61], showing a path for W-band GaN implementation with an example currently in development shown in the last section. For half-duplex operation, switches have been developed and are reviewed in more detail in Section IV, with insertion loss on the order of 1-2 dB across W band in 100 nm [31] and 40-nm [53] GaN processes.
For fully integrated W-band transceivers, it remains a question whether the best approach is to generate signals directly at W-band, or to do so at lower frequencies and multiply the signal to the band of operation. We first review the state-ofthe-art V-and W-band oscillator GaN MMICs. The frequency multiplication approach is shown in the block diagram of Fig. 1 and frequency multipliers are reviewed in Section VI along with some new results in a 40-nm process.  Table 4 summarizes demonstrated GaN MMIC oscillators. A standard method to design a microwave oscillator is with an unstable HEMT in the common source configuration with a resonator in the feedback path that determines the oscillation frequency and phase noise. The oscillators in [63], [64], [66], [67] realize this feedback by including a transmission line between the source terminal of the device and ground. Frequency tuning is performed by adjusting the reactance looking into the gate. An output buffer can isolate the oscillator core from impedance variations, while its bias can be adjusted to change the capacitive loading on the drain and tune the oscillation frequency [64], [67]. Varactors or diode connected devices with tunable gate bias have been shown to achieve a wider tuning range when connected at the gate of the oscillator core [63], [66], [67]. These oscillator topologies can operate at high frequencies with moderate phase noise performance and higher output power compared to other methods. A push-push VCO is implemented in [62] with two capacitively coupled common-gate configured devices. This oscillator operates at a lower frequency and requires more dc power than the common source designs, but was designed in a 200 nm process, while the rest use 120 nm or smaller gates. Finally, a balanced Colpitts oscillator was designed in [65] which exploits the resonance of an LC tank for its frequency generation. While this design quotes the smallest phase noise of all the circuits, it produces far less output power.
Following this brief review of the state-of-the-art in GaN MMICs at frequencies from 50-110 GHz, the design of several high-performing GaN MMICs in the 40-nm HRL T3 process is showcased with a goal of discussing possibilities and limitations of GaN technology for broadband circuits that cover W-band.

III. EXAMPLE W-BAND GAN PAS IN A 40-NM MMIC PROCESS
All designs are fabricated in the HRL T3 process featuring 40-nm GaN T-gates with f T /f max of 200/400 GHz and a  breakdown voltage of >40 V on a 50 μm SiC substrate [27]. Device-level combining within a MMIC amplifier is done first, by scaling the device and choosing appropriate staging ratios, and then on-chip reactive or isolated combining. To determine the staging ratio and limits of possible power-added efficiency (PAE) and output power, harmonic balance simulations for non-linear Angelov HEMT models are performed. Shown in Fig. 4 is the range of maximum output power and corresponding PAE of 4×37.5 μm, 2×25 μm, 6×50 μm, and 12×50 μm HEMTs, validated at drain voltages of +2 V, +6 V, and +12 V. The associated output power load-pull contours for validated device sizes is shown in Fig. 5. In Figs. 4, 5 only the +12 V drain voltage at a quiescent drain current density of 150 mA/mm is considered. The input of each device is matched to better than −10 dB. The shaded area presents behavior across frequency from 75 to 110 GHz for each validated HEMT model. Note that the 4×25 μm device is the an extracted model, which adds uncertainty to the simulation. The best achievable power ranges between 24.5 and 25 dBm for the 4×37.5 μm device, with an efficiency variation from 18% to 28% across the band. All devices are biased at (V DD =12 V, V GG = -0.2 V), and the respective gain obtained from the HEMT models ranges from 3-4 dB.

A. AMPLIFIER DESIGN AND SCALING
The low HEMT gain implies multiple stages for a useful PA, and power combining for useful output power. Four of the aforementioned HEMT models are used in a 3-stage PA design, where the last stage is reactively power combined. The staging ratio is determined based on interstage matching, as discussed in [50]. The broadband matching networks of the 3-stage PA consist of low-impedance transmission lines and stubs broadband matching, avoiding the use of capacitors as they are more prone to process variation than metal layers. Parallelizing the individual HEMTs with internally shared vias reduces the distance between transistors and allows a more compact circuit layout. dc blocking, stability and biasing is done through SiN capacitors and TaN resistors.
Minimizing the 3-stage PA footprint and designing the input and output ports of the 3-stage "unit" PA to be 50 allows power combining at the circuit level. To further increase output power, two and three of such "unit" 3-stage PAs are combined on-chip in a balanced and serial [52] amplifier topology. To cover the entire 75-110 GHz range, Lange couplers may be used. A closer analysis of the Lange coupler for the serial combining architecture shows that current crowding at millimeter-wave frequencies affects circuit behavior. The coupling factor differs for different port transmission-line feeds of a Lange coupler, requiring an adjustment in distance between the coupled microstrip sections. Fig. 6 shows the current distributions for two Lange couplers fed with 4-angled bends, used in balanced amplifier layout, and two-angled bends used for serial combiners layout. The full-wave simulated surface current magnitude for the coupled lines shows accumulation on the inside of the right angle bend. In addition, the Lange coupler shifts in center operating frequency and errors associated with changed coupling factors across the serial splitter impact the overall performance of the PA. In Fig. 7, a design based on modeling using the traditional 4-angled bend Lange manifold shows amplitude variation of up to 5 dB at 110 GHz. Using EM modeling for a layout representative of how the Lange coupler is incorporated in the PA layout, the finger spacing as a function of coupling factor can be redesigned for improved wideband performance.
Stability is always a concern in PA design, particularly at W-band where 40 nm gate length HEMTs have high gains at lower frequencies. To insure stability of the design, multiple stability analysis methods are used during the design process including K factor and Nyquist stability criterion. Even-and odd-mode loop gain analysis helps ensure the stability of power combined stages [68], [69], [70].
The resulting even-mode loop gain simulations of the Unit PAs show a phase margin greater than 60 • . Suppression of low-frequency gain is accomplished through accurate fullwave simulations of reactive matching networks, the addition of small resistors (about 5 ) in the dc gate paths, and on-chip capacitor ladder networks with increasing capacitor size from the RF path to the dc inputs. To eliminate odd-mode instabilities, resistors are placed on the symmetry lines before and after transistors in stages 2 and 3 and minimized in value using odd-mode loop-gain simulations.

B. MEASURED RESULTS
The balanced and serially-combined MMICs mounted on CuMo carriers and bonded to off-chip capacitors in the biasing  network are shown in Fig. 8. Small-signal measurements show stable gain that correlates well with the model, showing peak gain of 20 dB at the lower end of the band decreasing to 15 dB at 100 GHz and 10 dB at 110 GHz, Fig. 9.
A power-calibrated scalar test setup is used for large-signal measurements. The CW W-band signal from a HP83650 A sweeper in Ka-band is followed by a Quinstar amplification chain (QPW-18402020-J0 Ka-band amplifier, QPM-93003 W passive tripler, QFL-B4SW00 low-pass filter and QPI-W01820-H4W02 W-band driver amplifier) with a maximum output power of roughly 18 dBm. An isolator with ∼1.5 dB of forward transmission loss protects the amplification chain from any DUT mismatch. A 20-dB WiseWave coupler with a W-band power detector is calibrated with a W-band power meter. The results of these measurements are captured in Fig. 10 and show good agreement with simulations. The large signal gain at P in = 10 dBm is roughly 0.5-2 dB lower than simulated, but trends the same in frequency. The measured results, in Fig. 11, show 37.8% bandwidth from 75 to 110 GHz (where the gain is greater than 10 dB), a peak power of 25 dBm and a peak 1-dB compressed gain of 16 dB at 75 GHz.
In the measurement setup described above, the input power at the DUT is limited to 10 dBm. To obtain sufficient drive power for the serially combined PA, one of the 3-stage reactively-combined "unit" PAs is used as a driver, as shown in Fig. 8(b). The large-signal results for both the balanced and serially-combined PAs are included in Table 2.

IV. GAN MMIC SWITCHES
Microwave switches can be realized with the quarter-wave shunt topology. A source grounded HEMT is connected at its drain to a transmission line with electrical length of one quarter wavelength. The gate of the HEMT is then controlled to turn each path on or off. The ON-path is achieved by turning the device off, which acts as a grounded capacitor loading the line. At millimeter-wave frequencies, this off-state capacitance is typically resonated out with a shorted inductive stub placed directly at the drain node such that the impedance of the ON path is purely real and 50 . The OFF-path is achieved by turning the device on, providing a short to the signal which appears as an open after the impedance transformation of the quarter-wave transmission line. The shorted stub at the drain node is in parallel with the source vias to decrease inductance and resistance to ground. This topology has been employed in GaN technologies in [31], [53] to realize W-band SPST and SPDT switches, summarized in Table 5.
For standard semiconductor technologies, high isolation scales with device periphery, resulting in a considerably large total gate width. Consequently, this increases the capacitance  C off which, as previously described, is compensated by a parallel inductance or a shorted stub. This parallel resonant LC circuit and the electrical length of the λ/4 section are the main bandwidth limitation of a switch [31]. As with all millimeterwave circuits, this topology must overcome the challenges of increased ohmic losses and parasitic reactance to maximize performance at W-band. Namely, terminating the quarter wave line with a perfect short cannot be easily implemented with just one HEMT. Two source-grounded HEMTs with gates tied have been demonstrated in InGaAs metamorphic HEMTs to increase isolation in the OFF-path, at the cost of insertion loss over millimeter wave frequencies [71].
We demonstrate this with switch designs in the HRL 40-nm T3 process, with a photo of the various switch layouts, among other components, shown in Fig. 12. A summary of measured results is shown in Fig. 13. The SPDT switch with a single shunted HEMT in Fig. 13(b) achieves an isolation between 15-20 dB and an insertion loss between 0.9-3 dB, while that in Fig. 13(c) achieves an isolation between 30-40 dB and an  insertion loss between 1.2-10 dB. The SP4T switch shown in the photo is currently being evaluated and any measured results will be included in the final version of the paper. To the authors' knowledge, this is the first such comparison of SPDT topologies for GaN devices over entire W-band.

V. PHASE SHIFTERS
Phase shifters are key components in RF front ends for phased arrays. Switched delay-line phase shifters are enabled by the above described RF switches and the design is straightforward. However, the loss through the switches, number of dc controls, and large footprint make this design impractical for a circuit with many phase values at W-band. Vector modulators are also commonly synthesized to achieve phase shift, but cannot easily be implemented in GaN. Reflective phase shifters allow continuous tuning of phase through reflections from variable loads on two ports of a 90 • hybrid coupler. Realizing tunable loads at W-band can be done by connecting HEMTs as varactors. Their small size and wide phase tuning range make them attractive for integrated front ends in GaN.
A 3 dB coupler splits the incoming signal power evenly between the "thru" and "coupled" ports, as displayed in Fig 14. 1/ √ 2 of the signal arrives at the "thru" port with a −90 • phase shift, while the remaining part at the coupled port is shifted by −180 • . The varactors at the "thru" and "coupled" ports reflect the signal with a tunable phase shift corresponding to the varactor reactance, which is controlled through the gate bias voltage of the HEMT. The two signals then combine constructively at the isolated port with a −270 • shift added to the tunable phase. The reflected signals cancel at the input.
An analysis to optimize phase tuning is first performed in order to select the proper HEMT device size. The T3 GaN PDK offers transistors of four standard total peripheries: 50 μm, 150 μm, 300 μm, and 600 μm. Looking into the drain of these sourced-grounded devices, the largest tunable reactance range is found by sweeping the gate voltage from −1 V to +1 V. A 50 μm device is selected for the design, as it provides the greatest tunable reactance magnitude range of 51.4 . The second key component of this design is a hybrid coupler. The Lange Coupler used for this design has less than 30 dB of return loss and at least 20 dB of isolation over an octave bandwidth from 60-120 GHz. The fabricated MMIC phase shifter is captured in the photograph of Fig. 12, and has an overall size of 1.05 mm by 0.75 mm.
The fabricated circuits, first presented in [72], are tested with a calibrated Rohde & Schwarz ZNA vector network analyzer, with ZVA-Z110E millimeter-wave converters for a full W-band characterization . Phase, return loss, and insertion loss are captured for each 5 • increment in phase. The phase states are plotted in Fig. 15, displaying a tunable phase shift ranging from 90 • to 105 • over the entire bandwidth. |S 11 | and |S 21 | for each state are displayed in Fig. 16. Overall, the return loss ranges from 20 to 10 dB, indicating   that the device is well matched over the bandwidth. The insertion loss ranges from 2 to 11 dB across all of the phase states. Phase error is calculated across frequency relative to the phase at 90 GHz. The average measured and simulated phase errors are plotted in Fig. 17. Across the frequency band, the measured phase error is less than 10 • , from −6 • to +4 • ,  and is within 3 • across the band, with the trend well predicted by simulations.
These results provide the greatest degree of phase shift for any GaN design over the entire W-band to the best of the authors' knowledge. Higher degrees of phase shift are realized by cascading multiple Lange sections with varactor tuners (phase shift bits). A similar GaN structure is provided in [53], but shifts a maximum of 45 • for a one-bit structure and 67.5 • for a two-bit structure over W-band. This design has the potential to operate over even wider bandwidths but is limited by the testing setup on hand. Finally, the amplitude error for each bit can be addressed by including a variable gain amplifier as in [73], before or after the phase shifter.

VI. FREQUENCY GENERATION AND TRANSLATION
Frequency generation for an integrated front end is briefly described next. An oscillator circuit at 44 GHz is shown with a measured spectrum in Fig. 18. Refering to the block diagram in Fig. 1, the LO at the fundamental is generated by frequency doubling the output of the oscillator. To accomplish that, a single-ended and balanced frequency doubler is implemented in the HRL T3 40 nm GaN process, shown in Fig. 19. Both  doublers achieve conversion gain and over 10 dBm output power in the W-band frequency range. Reactive matching and cascading of a post-multiplication amplifier stage allows the single-ended topology to exhibit conversion gain and high fundamental suppression, Fig. 20. The single-ended topology outperforms the balanced topology in suppressing the fundamental. The post-amplifying HEMT along with the output matching network provide excellent fundamental suppression of over 35 dBc over the entire output band and over 50 dBc over 78 to 87 GHz.
Phase and amplitude imbalance of the planar Marchand balun as well as process variations degrade the suppression of the fundamental for the balanced topology, as described in more detail in [74]. To achieve the best conversion gain and fundamental suppression, a combination of both topologies is recommended. A doubling circuit arranged in a balanced configuration with post-multiplication amplifier benefits from the power-combining providing increased output power and  the post-amplification providing additional second harmonic power and fundamental suppression.

VII. CONCLUSION
This work presents a review of GaN MMICs from 50-110 GHz published to date, and new MMICs in the HRL 40-nm process designed towards an integrated front end. For a half-duplex case, the next step in integration is the combination of the balanced PA with a driver in the transmit path, followed by a low insertion loss SPDT switch and 3-stage LNA in the receive path. The layout of this chip which is currently being fabricated is shown in Fig. 22, with simulated performance shown in Fig. 23. For a full-duplex front end, future work includes scaling the X-band active circulator in [61] to operate at W-band. This design provides gain in the through path and sufficiently isolates the reverse paths. Linearity and noise must also meet stringent requirements to maintain the integrity of the signals. A fabricated circuit currently under characterization is displayed in Fig. 21.
As GaN technology continues to improve, higher levels of integration are becoming possible. Packaging techniques with thermal management are necessary to make W-band front ends practical. Several different levels of package level integration have already been explored [75], [76]. A comparison between water cooling and air cooling was done for a 37 W power amplifier module [51]. Results indicate a viable solid-state integrated approach for V-and W-band front ends.

Zoya Popović acknowledges support by a Lockheed Martin
Endowed Chair of RF Engineering at the University of Colorado. The authors would like to thank colleagues at HRL Laboratories, Malibu, California, for their professionalism and helpful suggestions.