GaN Integrated Circuit Power Amplifiers: Developments and Prospects

GaN integrated circuit technologies have dramatically progressed over the recent years. The prominent feature of GaN high-electron mobility transistors (HEMTs), unparalleled output power densities, has created a paradigm shift in the established and emerging high-power applications. In this article, we present a review on the developments and prospects of GaN integrated circuit power amplifiers (PAs). The progress of GaN transistors including improvements in their important features, i.e., supply voltage, substrate material, transistor scaling approach, and device modeling are elaborated and the current state-of-the-art processes with 20-nm gate length, 450 GHz cut-off frequency, and over 600 V supply voltage are discussed. We also investigate developments in the GaN integrated circuit PA architectures and their implementation challenges including the reactive matching PAs capable of delivering over 100 W output power and operating up to 200 GHz, PA linearity, back-off efficiency enhancement, reconfigurable PAs, and distributed PA architectures. Finally, we discuss the prospects of GaN technology and possible future improvements, in transistor and circuit levels, which can advance performance and functionality of GaN integrated circuits.

The research and development activities on GaN integrated circuit technologies have been pursued on three main streams: material, device, and circuit. In the material level, different substrate materials have been investigated including sapphire [8], native GaN [14], diamond [15], SiC [1], silicon (Si) [16], and silicon-on-insulator (SOI) [17], [18]. The substrate materials are evaluated based on several factors mainly thermal conductivity, fabrication cost, electrical parasitic components, loss, and mechanical robustness. Currently, GaN-on-SiC is the most popular process used in many commercial products. Other than the substrate material, a number of materials have been explored in GaN processes for the fabrication of the gate electrode, drain/source contacts, metal layers, interlayer via, and through-silicon via (TSV) [19].
In the device level, a number of GaN HEMT structures capable of operating under higher supply voltages or in higher frequency bands, e.g., T-gate structure, have been presented [1], [2], [3], [4]. Moreover, scaling of the minimum gate length of transistors down to sub-100 nm has enabled the operation of GaN circuits in mm-wave bands [67], [68], [70], [89]. An important challenge in the transistor level has been the development of accurate models for GaN HEMTs which include nonlinearities, high-frequency parasitic components, the charge trapping and memory effects, and the thermal heating impact on performance and reliability [24]. Finally, in the circuit level, major developments can be classified to low-loss power combining techniques, harmonic termination networks, integration of bandpass filter (BPF) into the PA circuit, linearization techniques for AM-AM and AM-PM distortions, and broadband uniform and nonuniform distributed PAs. The overall result of these progresses is the development of fully integrated GaN RF PAs with multi-hundred-watt output power, e.g., products by Qorvo [30] and Wolfspeed [31], highly scaled GaN processes, e.g., 40-nm GaN-on-SiC double-heterostructure field-effect transistor (DHFET) [67], [68], 40-nm and 70-nm GaN-on-SiC HEMTs [20], [89], and high-power mm-wave GaN PAs providing 34.8 dBm (3 W) at 84 GHz [83], 37.8 dBm (6 W) at 95 GHz [65], 26 dBm at 120 GHz [70], 15.8 dBm at 180 GHz [70], and 18.5 dBm at 205 GHz [71].
In this article, we present a review on the recent developments in GaN integrated circuit PAs, from transistor to circuit levels, and prospects of GaN technologies. The article is structured as follows. In Section II, progresses in GaN processes and transistors are discussed. In Section III, we present circuit developments on the most popular GaN PA architectures including the reactive matching PAs, Back-off efficiency enhancement PAs, reconfigurable PAs, and distributed PAs. A perspective on future directions is discussed in Section IV. Finally, concluding remarks are presented in Section V.

A. EARLY DEVELOPMENTS
Successful developments of GaN processes started by the fabrication of 2DEG GaN/AlGaN heterojunctions [5], [6], [7]. Special properties of GaN, wide bandgap of 3.4 eV, high breakdown voltage, and high electron mobility and saturation velocity, have made it a promising material for fabrication of high-power and high-frequency transistors. GaN HEMTs have become commercially available since early 2000, where discrete transistors were provided by different III-V semiconductor product suppliers, in unmatched and internally matched configurations, delivering up to 1000 W output power and high power densities, ∼ 50 W/mm, operating with high supply voltages, typically ∼ 50-80 V and even >1000 V for some high-power processes, typical PAE of 50-70%, across RF bands below ∼ 10 GHz [1], [3].
The first fully integrated (aka MMIC) GaN PA, implemented using a 400-nm gate length process on sapphire substrate, was a NDPA with 1.25 W peak power and 25% peak PAE operating at 3 GHz under 15 V supply voltage [13]. Subsequently, extensive improvements have been achieved in the reliability and electrical performance of the fully integrated GaN circuits. A summary of the state-of-the-art GaN integrated circuit processes is presented in Table 1. We briefly discuss the most important features of the GaN processes.

B. SUPPLY VOLTAGE
The primary motivation of using GaN HEMTs is their high supply voltage capabilities, resulting from high breakdown voltages of the process. This results in many advantages compared to counterpart processes like GaAs, especially for PA circuits, including the high output power densities, lower supply current, smaller parasitic capacitors, and broadband impedance matching networks. There is therefore a quest to develop transistors capable of sustaining larger supply voltages. The maximum supply voltage however is limited by several factors including the structure and dimensions of the transistor and physical effects, e.g., GaN breakdown electric field (3 MV/cm) [20].
It is experimentally observed that the breakdown voltage increases with the transistor's gate-to-drain separation L gd until it reaches a saturation. The corresponding electric field (V BR /L gd ) is about 1-2 MV/cm [20], [23]. The breakdown voltage can be increased using improved HEMT structures, e.g., field plate and multiple field plates [21], [22], [23].

C. SUBSTRATE MATERIAL
Substrate material have significant impacts on thermal, electrical, and cost properties of a GaN process. The substrate performance is conventionally evaluated based on thermal conductivity, fabrication cost, electrical parasitic components, loss, and mechanical robustness. Sapphire was the first substrate used in the early GaN processes, while other materials were subsequently investigated: native GaN [14], diamond [15], SiC [1], Si [16], and SOI [17], [18].
Currently, SiC is the most popular substrate in GaN processes [ Fig. 1(a)]. SiC provides an excellent thermal conductivity of 490 W/m·K which allows high power dissipation and prevents self-heating effects. SiC also features a low substrate loss which is especially important for high-frequency and high-speed circuits [1], [9].
Si is another popular substrate material used in GaN processes mainly as a result of the lower cost and the opportunity of heterogeneous integration with CMOS processes [100]. In GaN-on-Si processes, the lateral isolation between multiple transistors is provided through an implant or a mesa etching process, but the coupling through Si substrate degrades the overall isolation [ Fig. 1(b)]. Si however suffers from lower thermal conductivity (230 W/m·K) and, more importantly, higher substrate loss compared to SiC. GaN-on-Si processes are maturing rapidly and widely used in high-power switching applications, e.g., boost converters, bridge converter circuits, and power factor correction (PFC) circuits, operating with up to 600 V supply voltages [16].
GaN-on-SOI process has been recently introduced to integrate GaN power systems on a single chip [17], [18]. The process is similar to GaN-on-Si, except for an additional trench or substrate contact to improve the isolation [ Fig. 1(c)]. The transistors use a p-type gate (p-GaN) and operate in the enhancement-mode. The fabricated devices have a gate width W g of 36 mm, a gate length L g of 0.8 μm, a gate-source spacing L gs of 0.75 μm, and a gate-drain spacing L gd of 6 μm.
The p-GaN HEMTs feature a breakdown voltage of around 600 V and can be used for 200 V switching applications [17].

D. TRANSISTOR SCALING
Scaling of GaN HEMTs have been pursued through new device technologies to improve the operational frequency of transistors [20]. The scaling enhances f T and f max of the transistors but simultaneously degrades their breakdown voltage. This trade-off can be mitigated by using asymmetric HEMT structures with L gs shorter than L gd [see Fig. 1(a)] to prevent the drop of breakdown voltage, e.g., L gd = 8 L gs in [17].
GaN processes with state-of-the-art operational frequency are 40-nm GaN DH-HEMTs with f T / f max of 220/400 GHz and breakdown voltage of 42 V [32], GaN-on-Si HEMTs with 40-nm gate length and 300-nm source-drain distance achieving f T of 250 GHz [33], GaN-on-Si HEMTs with 55-nm gate length and 175-nm source-drain spacing featuring f T / f max of 250/204 GHz [34], and finally, the highest f T / f max of 454/444 GHz and 10 V breakdown voltage for a GaN-on-SiC process with 20-nm gate length and L gs = L gd = 50 nm [35].

E. MODELING OF TRANSISTORS
Development of accurate models for the transistors is essential to leverage benefits of the GaN process. This is challenging as a result of several physical effects which should be precisely modeled, including the voltage-dependent drain current, I ds = f (V gs , V ds ), derivatives of the drain current, g m , g m2 , and g m3 , voltage-or charge-dependent capacitance models, C gs , C gd , and C ds , temperature-dependent large-signal current model (e.g., through electron mobility and threshold/pinch-off voltage of enhancement/depletion mode devices), models for pulsed and CW operation, and nonlinear models for the load impedance VSWR effects [24].
A number of basic models are conventionally used for GaN HEMTs, e.g., Curtice, EEHEMT, and Angelov [25], which are gradually improved through including important effects [24]. There are some physical behaviors unique to GaN HEMTs which call for new physic-based models. MIT virtual source GaN HEMT high voltage (MVSG-HV) model is a scalable physic-based model capable of capturing static and dynamic behaviors of the transistor through self-consistent charge and current models [28]. Charge trapping is an issue in GaN HEMTs, manifesting as memory nonlinear effects in PA circuits or degraded on-resistance, R on , of the transistor (aka current collapse effect) in switching circuits [26]. Charge trapping effect in MVSG-HV is modeled by including trap transistors as virtual gates in the drain-access region. Moreover, the model includes parameters for the subthreshold operation of the transistor, which is important for accurate modeling of class-C biased devices (e.g., auxiliary amplifier in Doherty PAs). In MVSG-HV, electrothermal model comprises a thermal resistance R th in parallel with a thermal capacitance C th . A nonlinear GaN HEMT equivalent circuit electrothermal model is proposed in [27]. Advanced SPICE model for HEMT (ASM-HEMT), an industry standard model, is a surface potential based physical compact model which can include self-heating, channel length modulation (CLM), drain-induced barrier lowering (DIBL), gate leakage current, surface trapping, and bulk trapping effects [29].

III. GAN POWER AMPLIFIERS A. ADVANTAGES OF GAN FOR PAS
The impressive output power densities of GaN HEMTs is the main, but not the only, advantage for high-frequency PAs. The most important offerings of GaN HEMTs can be summarized as follows.
1) The unparalleled output power densities enable highpower compact PA chips which can be used to reduce electronic systems size and cost in many applications.
2) The high supply voltage translates to lower supply current levels, which improves reliability and reduce thermal cooling requirements.
3) The higher power densities allow smaller transistors to be used for a target output power level. Such transistors feature lower parasitic capacitance, leading to wider bandwidth of the PA circuit. 4) The gate width of GaN HEMTs can be selected to achieve an optimum load resistance R opt close to the load resistance R L . This results in an impedance transformation ratio close to unity, which helps to realize low-loss and broadband impedance matching networks [38], [39]. This condition cannot be usually satisfied for other processes with lower supply voltages (R opt ≈ 2V DD /I max ). 5) The high breakdown voltage of GaN transistors allows the realization of waveform-shaping PAs to achieve high efficiencies without reliability concerns due to increased drain voltage.

B. REACTIVE MATCHING PAS
In a typical GaN PA, usually multiple transistors are combined to achieve a desired high output power level. The driver stage(s) can also comprise multiple transistors to provide required output power for driving the output stage. A two-stage PA architecture is shown in Fig. 2. The output matching network provides optimum load impedance for the output stage transistors Z L,opt2 while combining their output signals and delivering to the load resistance R L . The interstage matching network transforms the optimum source impedance of the output stage transistors Z S,opt2 to the optimum load impedance of the driver stage transistors Z L,opt1 . The input matching network transforms the source resistance R S to the optimum source impedance of the driver stage transistors Z L,opt1 while dividing the input power between the transistors. In the reactive matching PAs, the impedance matching networks are realized using lumped LC networks, distributed transmission line based networks, or hybrid of the lumped and distributed elements. The most popular circuit realization is shown in Fig. 3, where the transmissions lines are implemented using meandered microstrip lines or planar waveguides, the capacitors are constructed using the highquality metal-insulator-metal (MIM) capacitors offered by the GaN process, and the ground connections are realized using back-vias through the substrate. The output impedance of the transistors is modeled by the optimum resistance R opt in parallel with an output capacitance C out which should be absorbed into the output matching network. Resistive components can also be used in the input matching network to ensure stability, extend bandwidth, and improve input impedance matching. The design procedure is similar to the GaAs PAs [36]. In an integrated RF PA, assuming high quality factors for capacitors, efficiency of the output matching network can be derived using quality factors of the inductors as η where N L is the number of inductors and α k are coefficients dependent on the impedance transformation ratio and the network circuit architecture [37], [38]. This can provide guidelines to identify critical inductors and maximize their quality factor through layout design techniques.
Several fully integrated GaN PAs using the reactive matching are presented in the literature [40], [41], [42], [43], [44], [47], [65], [69], [70] and developed as commercial products [30], [31]. A performance summary of fully integrated GaN PAs operating in RF bands is presented in Table 2. Stateof-the-art RF GaN PAs are shown in Fig. 4 The output power and efficiency of the GaN HEMTs degrade in mm-wave bands due to the increased loss. The loss of passive elements is also higher in mm-wave bands. This is therefore more challenging to achieve high output power in mm-wave bands. A summary of fully integrated mm-wave GaN PAs is presented in Table 3. State-of-the-art mm-wave GaN PAs are shown in Fig. 5. The highest output power levels achieved in mm-wave bands include 12 W with 30% PAE at 40 GHz [64], 3 W at 84 GHz using a traveling-wave power combining amplifier architecture developed in [83], 6 W with 18% PAE at 95 GHz using a four-path PA with the Wilkinson and Lange coupler power combiners [65], 430 mW with 16% PAE at 120 GHz [70], and 70 mW at 205 GHz implemented using a 70-nm GaN-on-SiC process [71]. Further   details about mm-wave PAs presented in the literature can be found in [63].
The impedance matching networks of the PA can be used to realize other additional functions, e.g., harmonic termination [37], [39], [42], [51] and filtering [38]. Harmonic termination networks can shape the transistor's drain current and voltage waveforms to realize a specific high-efficiency class of operation (e.g., class E, F). A practical implementation challenge is the narrow bandwidth of the harmonic termination networks [51], which increases their sensitivity to process variations and parasitic components. Broadband harmonic matching networks are introduced to mitigate this issue, but at the cost of lower efficiency [37], [39]. Moreover, a bandpass filter (BPF) can be embedded into the matching networks to suppress harmonics and out-of-band emissions. In [38], a minimum-inductance BPF architecture is introduced which can achieve higher harmonic suppression with a significantly lower total inductance (∼ 60%) compared to a standard BPF. This is used to realize the output matching network of a broadband 2.0-4.0 GHz GaN PA.

C. PA LINEARITY
Linearity of the PA is an important consideration in wireless communications, especially when complex-modulated signals (e.g., QAM and OFDM) are used for efficient high-speed data transmission. These signals are sensitive to the amplitude and phase distortions in the PA characteristics. GaN HEMTs suffer from the soft gain compression where the device exhibits nonlinearity from low power levels (e.g., 10 dB lower than 1-dB compression point). This behavior results in the increased AM-AM and AM-PM distortions of GaN PAs. Also, increasing bandwidth of modulated signals leads to higher error vector magnitude (EVM), which is a result of the charge trapping and memory effects in the GaN HEMTs [37], [39].
It is shown that for a fully integrated GaN PA, EVM for QAM signals can be improved (by > 6 dB) through biasing the transistor at the optimum current density [39]. This is a result of the reduced nonlinearity of the transistor's transconductance and gate-source capacitance. Moreover, in [38], a dual-path amplifier architecture is used to combine complimentary compressive and expansive nonlinearity profiles of the two transistors and, as a result, mitigate the AM-AM and AM-PM distortions of the PA. Such circuit-level linearization approaches can provide moderate linearity performance. Nevertheless, digital predistortion (DPD) techniques can be applied to meet the stringent linearity requirements of base stations in the current 5G and emerging generations of wireless communication.

D. BACK-OFF EFFICIENCY ENHANCEMENT
The modulated signals used in wireless communications usually feature a high peak-to-average power ratio (PAPR), typically 6-10 dB, which degrades average efficiency of the PA unless a specific circuit be adopted to improve backoff efficiency of the PA. The most popular PA architecture for back-off efficiency enhancement is the Doherty PA [52], [53]. Doherty PAs implemented as hybrid circuits operating in lower RF bands, typically, < 3 GHz, are extensively investigated in the literature. There are however many practical challenges to leverage the potentials of Doherty PAs implemented as integrated circuits and operating at higher frequencies. The most important issues include the parasitic capacitance and loss of transistors and passive components, large size of transmission lines for on-chip realization, the low gain of the class-C biased auxiliary transistor, and the need for asymmetric transistors for large PAPR signals [53]. A number of circuit architectures are developed for integrated circuit GaN Doherty PAs [54], [55], [56], [57], [58], [59].
In [54], the load modulation network is realized using a T-shape circuit comprising transmission lines (with l < λ/4) and output parasitic capacitance of the transistors. The PA, shown in Fig. 6(a), achieves 3.2 W peak power and 24-37% PAE at 9-dB back-off across 6.8-8.5 GHz. The Doherty PA presented in [55] comprises a power combining load modulation network, using transmission lines and output parasitic capacitance of the transistors, providing asymmetric drain bias for the main and auxiliary transistors, and a Lange coupler operating as the input power splitter and phase shifter. The PA, shown in Fig. 6(b), provides 4 W peak power and 31-39% PAE at 9-dB back-off across 5.8-8.8 GHz. In [56], the load modulation network is realized using coupled transmission lines to extend bandwidth of Doherty PA. The PA chip, shown in Fig. 6(c), achieves 4 W peak power and 22-27% PAE at about 6 dB back-off across 4.5-6.0 GHz.
A number of PA architectures are developed to mitigate limitations of the Doherty PA. Load modulated balanced PA, shown in Fig. 7(a), is a balanced amplifier with an auxiliary amplifier which is used to inject a signal to isolated port of the quadrature coupler. This can modulate the load impedance presented to the two main transistors. The PA efficiency can be improved at back-off over a wide bandwidth through a proper control of the amplitude and phase of the auxiliary signal [60]. A GaN integrated circuit implementation of the load modulated balanced PA, shown in Fig. 7(c), achieves 14 W peak power and > 37% PAE at 9.7 dB back-off across 8.0-9.0 GHz [61]. Another coupler-based PA architecture for back-off efficiency enhancement is unbalanced PA shown in Fig. 7(b) [62]. In this architecture, the class-C biased auxiliary transistor has a larger size, and hence output power, compared to the class-B biased main transistor. The output quadrature coupler is asymmetric with a coupling coefficient C o < −3 dB. The output power back-off level can be controlled by the transistors' power ratio K p and coupling coefficient of the output coupler OPBO = 20 log 10 [1 It is shown that a Doherty-like behavior can be achieved for C o ≈ −6 dB. The high isolation between the main and auxiliary amplifiers, provided by the coupler, and the lower impedance transformation ration at back-off result in inherently wider bandwidth performance compared to Doherty PA. The GaN integrated circuit unbalanced PA shown in Fig. 7(d) achieves 2.7 W peak power and 27-40% PAE at about 6 dB back-off across 4.5-6.5 GHz [62].

E. RECONFIGURABLE PAS
Reconfigurable PA architectures which can adapt their circuitry to the input modulated signal can provide remarkable advantages in the average efficiency and linearity. This concept is extensively used in CMOS digital PAs which are mature technology in industry. In GaN technology however the development of reconfigurable PAs is hindered by process limitations, mainly the lack of compact and high-speed switches. We briefly review some preliminary developments in reconfigurable GaN PAs [72], [73], [74].
In [72], a voltage-mode digital GaN PA is presented. The digital PA is implemented in a 250-nm GaN-on-SiC process and is followed by a hybrid BPF circuit which realizes a class-D/S PA. The PA operating at switching frequency of 840 MHz, with a supply voltage varied from 60 to 20 V, achieves the peak output power of 7.8 W and PAE of 47%. A quad-mode reconfigurable harmonic-tuned PA is presented in [73]. The PA comprises one main transistor with the width of W m and three auxiliary transistors with the width of W a . The transistors are sized such that W m = 3W a , which leads to an output power ratio of 2. The PA is implemented in a 250-nm GaN-on-SiC process, operates at 4.8 GHz, provides 2 W maximum power, and through configuring the operation mode can achieve 60% enhancement in the back-off efficiency and 6 dB improvement of the adjacent channel leakage ratio (ACLR). A reconfigurable PA is proposed in [74], which comprises a dual-band output matching network and reconfigurable interstage and input matching networks. The PA can be operated in one of the two modes: 2-3 GHz or 10-12 GHz. The PA is implemented in a 250-nm GaN-on-SiC process and delivers about 1 W output power.

F. DISTRIBUTED PAS
Distributed amplifiers can provide extremely broad bandwidth by absorbing input and output parasitic capacitance of the transistors in the input and output transmission lines [75]. GaN process can provide several advantages for distributed amplifiers mainly simultaneous broad bandwidth and high output power as a result of high power densities which allow small transistors with low parasitic capacitance be used. A uniform distributed amplifier cannot realize an efficient PA due to the power loss in the output line termination resistor and unequal drain voltage swing of the transistors. These issues are mitigated by using a nonuniform distributed amplifier architecture where the characteristic impedance of the output line are scaled down toward the output port and the output line termination resistor is eliminated [ Fig. 8(a)]. Sometimes, the width of transistors is also scaled down toward the output port to further enhance the efficiency [76].
A summary of GaN distributed PAs is presented in Table 4. The highest output power of 42-60 W is achieved over 1-6 GHz bandwidth using a 250-nm GaN-on-SiC process with 30 V supply voltage [77]. Moreover, in [80], two nonuniform distributed amplifiers are combined using Lange couplers to construct a balanced amplifier with 12.3-13.5 W output power over 6-18 GHz bandwidth. A bandwidth of 0.1-45 GHz is achieved using a distributed amplifier where the gate lime termination resistor is removed to extend the lower band cut-off frequency [86]. The PA provides 1-2 W output power and is implemented in 150-nm GaN-on-SiC.
Most of the developed GaN distributed PAs use limited circuit architectures, mainly nonuniform distributed amplifier with power combing in the power cell level or as a balanced amplifier. This indicates the need for further circuit level research to achieve higher performance. In [84], a distributed amplifier architecture with coupled input and output lines, as shown in Fig. 8(b), is proposed. It is shown that the gate-drain capacitance effects can be canceled by an optimum coupling coefficient between the input and output lines as k opt = 1/ (1 + C g /C gd )(1 + C d /C gd ), where C g and C d respectively denote the input and output line capacitance in each node and C gd is the transistors' gate-drain capacitance. The original circuit is implemented in a GaAs process which can also be used in GaN processes. Moreover, in [87], a tapered distributed amplifier architecture is proposed in which the length of transmission line segments of the input and output lines as well as the width of transistors are tapered by the factors (K g , K d , K m ) [see Fig. 8(c)]. The optimal tapering factors are derived using an analytical model developed for the distributed LNA. This approach can be applied to a distributed PA and derive the optimal tapering factors.

A. TRANSISTOR LEVEL
In the transistor level, one of the major trends pursued has been the scaling of transistors' gate length to enable their operation at higher mm-wave frequencies. The most advanced GaN technology node reported in the literature is the HRL 20-nm GaN-on-SiC HEMT process with f T / f max of 454/444 GHz [35]. This process can be practically used up to around 200 GHz to realize PA circuits. The process features 50-nm gate-source and gate-drain separation and achieves 10 V breakdown voltage, which limits the supply voltage to about 4 V. The relatively low supply voltage limits the output power density of transistors. In the future therefore two trends can be expected. First, the scaling of transistors will be continued to sub-10-nm nodes to achieve higher operation frequencies and higher performance. Second, to improve the output power densities, the breakdown voltage of transistors should be increased through innovative scaling approaches or transistor structures, e.g., using asymmetric gate-drain and gate-source spacing with L gd > L gs .
Another major trend is the development of GaN transistors with extremely high breakdown voltages. Currently, GaN processes with supply voltages of 600 V are available [16]. The quest for higher supply voltages is expected to be continued to push the performance limits of emerging high-power electronic applications. A critical challenge is the trade-off between breakdown voltage and switching speed or maximum operational frequency of the GaN devices. A possible solution can be the development of GaN processes which permit stacking of transistors, i.e., similar to SOI CMOS processes, to apply higher supply voltages without compromising the speed of transistors. This indicates a future trend to address the need for simultaneously high-voltage and high-speed GaN processes.
A limitation of the current GaN processes is their low integration capabilities which hinders to leverage all expected potentials of an integrated circuit process. The most important issues are the large size of transistors, the limited number of metal layers, the low MIM capacitance density in GaN compared to CMOS processes, the availability of only one transistor type for high-power operation, the inaccuracy of the transistor models, e.g., in the subthreshold and non-nominal supply voltages, and the low yield of large GaN chips. These issues should be addressed in future developments to allow the implementation of more complicated GaN circuits and systems with higher levels of functionality.

B. CIRCUIT LEVEL
In the circuit level, there are only a few well-established integrated circuit PA architectures which have been used since the first developments of GaN process. The most popular architectures are the reactive matching PAs, in which output signals of multiple transistors are combined to achieve a target output power over a specific frequency band. The reactive matching networks are tuned over the frequency band. The PA usually comprises one driver stage, and more in mm-wave bands. The main challenge in these PAs is the design of interstage matching networks which should math two complex impedances with large impedance transformation ratio [36]. The next popular GaN PA architecture is the nonuniform distributed amplifier, which can achieve extremely broad bandwidths but their efficiency and output power are usually lower than the reactive matching PAs.
This scarcity of the integrated circuit architectures for GaN PAs can be a result of limited research on circuit design in this process which due to high fabrication costs has been limited to a few specific companies and groups. Moreover, limitations of GaN processes including the transistor models, the large size of transistors, and the low yields of large GaN chips prevent rapid developments in GaN integrated circuits compared to CMOS processes. Possible improvements in GaN processes in the future can open up opportunities for the realization of novel circuit architectures and functionalities to leverage potentials of this promising process.

V. CONCLUSION
In this article, we presented a review of recent developments in GaN integrated circuits power amplifiers (PAs). The progresses of GaN transistors to reach the current state of performance were discussed. The GaN integrated circuit PA architectures and state-of-the-art in output power in RF and mm-wave frequency bands were investigated. Moreover, we presented future perspectives on the possible improvements in the GaN transistors and circuit architectures to leverage potentials of this process.