QubiC: An open source FPGA-based control and measurement system for superconducting quantum information processors

As quantum information processors grow in quantum bit (qubit) count and functionality, the control and measurement system becomes a limiting factor to large scale extensibility. To tackle this challenge and keep pace with rapidly evolving classical control requirements, full control stack access is essential to system level optimization. We design a modular FPGA (field-programmable gate array) based system called QubiC to control and measure a superconducting quantum processing unit. The system includes room temperature electronics hardware, FPGA gateware, and engineering software. A prototype hardware module is assembled from several commercial off-the-shelf evaluation boards and in-house developed circuit boards. Gateware and software are designed to implement basic qubit control and measurement protocols. System functionality and performance are demonstrated by performing qubit chip characterization, gate optimization, and randomized benchmarking sequences on a superconducting quantum processor operating at the Advanced Quantum Testbed at Lawrence Berkeley National Laboratory. The single-qubit and two-qubit process fidelities are measured to be 0.9980$\pm$0.0001 and 0.948$\pm$0.004 by randomized benchmarking. With fast circuit sequence loading capability, the QubiC performs randomized compiling experiments efficiently and improves the feasibility of executing more complex algorithms.


I. INTRODUCTION
The quantum computer represents a paradigm shifting innovation for computing technology, spurring the development of new breakthroughs in science [1], [2]. Superconductingcircuit-based quantum bits (qubits) are a leading platform for quantum information science, with recent demonstrations of quantum advantage [3]. Qubit control hardware generates and routes complex sequences of radio frequency (RF) signals from room temperature electronics to the quantum processor at cryogenic temperature. As the size and complexity of the quantum system increases, the cost-efficient and compact generation of such signals becomes a bottleneck limiting system extensibility in the near term noisy intermediate-scale quantum (NISQ) computing era [4]. Thus, hardware elements in a nextgeneration design should be carefully matched to the needs of both current and potential future superconducting multi-qubit processors, while maintaining the modularity available at the printed circuit board (PCB) design level. However, commercially available lab equipment such as arbitrary waveform generators (AWG) and data acquisition cards (DAQ) are designed for general purpose test and measurement applications, and typically cannot keep pace both in terms of footprint and cost as quantum system complexity increases [5]. A customized quantum engineering solution rooted in extensible primitives is needed for the quantum computing community.
The field-programmable gate array (FPGA) architecture allows for customized solutions capable of growing and evolving with the field [6]. Several FPGA frameworks have been developed for quantum control and measurement [7]- [10]. Nevertheless, current FPGA-based control systems are not fully open to the broader quantum community so it is hard to make a general toolbox for information scientific discovery [11]- [13]. Understanding the full electronics hardware and software stack of the qubit control systems is essential to the system level optimization and extensibility [14]. Furthermore, compiling near-term quantum algorithms directly down to the native hardware descriptions via pulse-level control will improve the reliability of program execution [15]. Recent developments have also explored highly integrated system-onchip (SoC) solution and moved it to the cryogenic stage [16]- [18]. As such efforts mature, they will benefit from a deeper understanding of the control requirements that emerge as system size increases, and will thus rely on broad conceptual explorations rooted in more flexible hardware platforms.
Here we develop and test the QubiC (Qubit Control) system -an open source FPGA based RF control system that integrates qubit pulse generation and quantum state measurement [19]. Leveraging state-of-the-art FPGA technology, QubiC provides fully parametric waveform generation, and allows researchers to access all the control layers. This scalable and cost-effective system will be a potential open source toolbox for the quantum community.

II. QUBIC SYSTEM
We design an FPGA-based qubit control system called QubiC to integrate the execution of gate-based algorithms with native quantum hardware implementation. QubiC is an open source system which can accommodate users and developers from different layers to enable efficient co-design. a single control unit to demonstrate basic functionality and evaluate performance.
The room temperature electronics hardware, the FPGA gateware, and the engineering software are integrated in the QubiC prototype system so as to realize the desired RF pulses to control and measure qubits. This prototype system also provides a platform to explore and optimize real-time feedback control such as fast reset [20], [21], and error correction algorithms.

A. Electronics hardware
The QubiC prototype hardware employs the heterodyne technique to generate and detect RF signals in a compact manner. It includes three basic building modules: the FPGA/ADC(analog-to-digital converter)/DAC(digital-toanalog converter) module to generate/detect the intermediate frequency (IF) signal; the RF mixing module to convert the signal frequency to/from the target frequency; and the local oscillator (LO) generation module to provide low noise LO signals, as shown in Fig. 1. A series of commercial off-theshelf (COTS) evaluation boards are selected and assembled with in-house developed RF mixing modules to test functionality and benchmark performance. Using these COTS evaluation boards enabled us to rapidly develop a hardware platform to study and develop the qubit control logic, while leaving plenty of room for channel density and cost optimization in future iterations.
1) FPGA and ADC/DAC module: The Xilinx VC707 and the Abaco Systems FMC120 boards are chosen for their computational capability and precision analog performance. The VC707 evaluation board contains an Xilinx Virtex-7 FPGA [22]. Each FMC120 board has 4 channels of high speed (1.25 GSPS) 16-bit DACs and 4 channels of high speed (1 GSPS) 16-bit ADCs [23]. One VC707 and two FMC120 boards are assembled in a 1U rack mount computer chassis with a customized cooling manifold to meet the FMC120 board cooling requirements. An external 1 GHz clock is provided to the chassis to run the DACs/ADCs at 1 GSPS, and to run the FPGA DSP at 250 MHz. Compared with the latest RFSoC (radio frequency system-on-chip) chips, this combination gives us more choices with respect to DAC/ADC selection, particularly when tailoring hardware for specific future applications.
2) RF mixing module: We develop compact RF up and down mixing modules that integrate the I/Q (inphase/quadrature) mixer, IF/LO/RF power level adjustments and DC bias fine tuning on a 40 mm × 80 mm 4-layer PCB board with electromagnetic interference (EMI) shielding. The RF mixing module is designed to work with RF and LO frequency between 2.5 and 8.5 GHz. Typical image rejection and adjacent channel isolation are measured to be ∼27 dBc and ∼50 dB. The RF mixing module provides 5×10 −4 (V pp /V mean ) amplitude stability and 1×10 −3 radian (pk-pk) phase stability [24].
3) LO generation module: The noise performance of the LO generation module is critical for high-fidelity qubit operation because imperfections will directly map on to the RF/IF control signal through the RF mixing module. The LO frequency also needs to be adjustable from experiment to experiment to accommodate different chip designs. Additionally, some qubit operations will require multiple, different LO frequencies synchronized to each other. At the same time, the size and cost of LO generation should also be factored into design consideration.
We thus use multiple phase locked loops (PLL) with a shared master oscillator (MO) to generate the LO and clock to meet these frequency and low-noise operation requirements. The Wenzel (501-16843) 100 MHz ultra low noise crystal oscillator is used as the MO for the prototype system [25]. The Texas Instruments LMX2595 evaluation modules are used as a PLL given its 20 GHz wide frequency range and lownoise performance [26]. Specifically, we measure the RMS jitter of the "Wenzel+LMX2595" module at the LO frequency at the qubit readout resonator frequency (6.52 GHz) and qubit drive frequency (5.50 GHz). As shown in Table I, the RMS jitters of "Wenzel+LMX2595" module are 1.0 ps (1 Hz-10 MHz) and 60 fs (100 Hz-10 MHz), which are comparable with the widely-used commercial Keysight signal generator [27]. The relationship between the LO phase noise metrics and the corresponding qubit dephasing spectral densities has been studied and the formula to estimate the operational fidelity bounds on superconducting qubits was derived in [28]. Following the analysis and using the measured phase noise of the "Wenzel+LMX2595" configuration, we estimate that for theX gate shorter than 10 ms, the LO phase noise contributes < 10 −5 to the gate infidelity, which is much lower than the typical gate infidelity in superconducting qubits. This implies that the LO module phase noise is not the dominating factor to the gate fidelity. Moreover, the "Wenzel+LMX2595" module is much more compact in size and lower in cost. 4) Module synchronization: To scale the system up, we design the module-to-module synchronization using three layers of protocols [29].  [30] is used to synchronize multiple DAC chips via the external SYSREF signal. • Direct GPIO (general-purpose input/output) triggers are used to pass and fan out the event information which requires low latency among modules. • Fiber-based synchronization using a protocol similar to the white rabbit [31] system is under development to lock the clock phases among the modules and also provide a high speed data communication path.

B. FPGA gateware
The gateware programmed on the FPGA is the lowest level to implement digital tuneup sequences and algorithmic protocols. Modularity is the key to designing reusable and maintainable FPGA gateware code. The QubiC FPGA gateware is written in the Verilog programming language and it is separated into three modules: the board support package (BSP), the digital signal process (DSP), and the host interface (HOI).
• The BSP is hardware specific and used to implement lowlevel hardware configuration and initialization. • The DSP implements basic qubit control and measurement functions and it is designed to be independent of the low-level FPGA/ADC/DAC selection. The DSP runs in a single clock domain and the HOI and BSP handle the clock domain crossing for the required registers, and also buffers the transmitted and received data. • The HOI handles all the input and output to and from the host computer, which is the interface that hosts higher level software. The QubiC gateware is capable of generating waveform form parameters, which leads to the benefit of pulse sequence reuse. The QubiC FPGA DSP is flexible and extensible. In particular, the QubiC system has the capability of the fast reset by implementing the qubit status classification and the feedback loop in the FPGA gateware with low latency [32]. In this section we will focus on the gateware DSP module and the host interface associated with it.
1) Gateware DSP: The basic requirements of qubit control and measurement are to generate pulses at a specified carrier frequency with arbitrary amplitude modulation, and to also synchronously detect the pulse after it goes through the readout resonator. The hardware module shifts frequencies between the RF and IF, while the gateware DSP module is responsible for the generation and processing of the data stream between the IF signal and the baseband signal. The QubiC gateware DSP block diagram is illustrated in Fig. 2.
The digital modulation/demodulation between the baseband envelope and the IF data stream is realized by a module called  the processing element. Processing elements can be configured to execute digital up or down conversions. When used as the up converter, the module generates IF pulses in-phase (I IF ) and quadrature-phase (Q IF ) components from the gate-specific baseband envelope I BB + jQ BB , the initial phase φ 0 and the digital local oscillator (DLO) frequency, as in The carrier frequency is determined by the physical property of the qubits or the readout resonator. The carrier phase naturally rotates as time evolves; additionally the engineering software can inject additional phase offsets to implement virtual Z gates [33]. The pulse envelope is defined or optimized through the qubit gate calibration process, and stored in the FPGA memory point-by-point as complex numbers, each with in-phase and quadrature-phase terms. Moreover, this pulse envelope can be used repetitively by indexing the same address area, even if the carrier frequency or phase changes. The calculated result then feeds into any DAC through an m-to-n switch. Signals from multiple processing elements can be sent to the same DAC and added together. For each pulse to be generated, the software needs to specify the processing element, and the DAC to be used for the destination.
When the processing module is used in the down conversion mode, it receives the qubit signals from the ADC, and recovers the baseband I and Q components, which is exactly the opposite operation, as defined by Then the baseband I/Q series are integrated by a vector accumulator, and the results are stored in an "accumulation buffer" (acc buffer) for the corresponding channel to determine the qubit final state. The raw ADC, DAC, DLO values are available to the host computer through "acquisition buffers" (acq buffer) and the integrated I/Q data are available to the host computer through the acc buffer.
In the QubiC gateware, the processing element is flexible in the waveform generation. Each processing element has a waveform storage and a phase rotator, but only puts out one waveform at a time. Once stopped, it is available to replay another waveform with another configuration. Waveform envelopes drawn from that memory can be variable lengths in order to start and stop arbitrarily. Currently, the envelope buffer of each processing element is 1k deep and 32 bits wide. The upper and lower 16 bit words of each envelope point represent the real (I) and imaginary (Q) parts of the pulse envelope respectively. The conversions between amplitude/phase and I/Q of a complex signal as in (1) and (2), are implemented with the CORDIC (COordinate Rotation DIgital Computer) algorithm on FPGAs [34], [35].
2) Host interface: A qubit algorithm typically consists of a series of qubit gates and measurements, which are eventually realized by the sequence of RF pulses. In general, a gate may consist of a series of pulses. Gate level experiments adopt a pre-calibrated gate pulse, while pulse level experiments need access the parameters for each pulse. The host computer interface needs to be designed to accommodate both types of experiments by way of parametric waveform generation.
In the current QubiC gateware, each pulse is defined by the pulse start time, the envelope information, and the carrier information. We define a 128-bit command as the interface between the lower level gateware on an FPGA and the higher level software on a host computer: • Trig t (24 bits) Pulse start time relative to the start of the whole sequence. • Start (12 bits) The start address of the envelope data in the envelope buffer. • Length (12 bits) The length of envelope buffer to play for this pulse. • Reserved 31 bits The 128-bit command provides the parametric waveform generation from the lowest FPGA level. The QubiC reuses sequences by updating waveform parameters via commands without recompiling or resending the waveform data.
The commands defining quantum circuits are stored in a 64k deep 128-bit wide buffer on an FPGA. The envelope buffers are also written from the host computer and stored in each processing element. All commands repeat at a defined period until the acc buffer is full. The acc buffer can be cleared by the software after reading the data.
Writing to the command/envelope buffer to generate pulses, and reading from the acc/acq buffer to collect responses are the lowest level software interface provided by the FPGA gateware. At this level, we have to adhere to the restrictions imposed by the gateware implementation, for example, the maximum pulse envelope length and command depth, the frequency and phase resolution, the longest sequence time etc. The complexity of the restrictions imposed at this lower level makes it more difficult to use directly. However, the advantage is that this layer has full access to the FPGA directly, and mainly serves developers who implement software directly on top of the QubiC gateware.

C. Engineering software
The engineering software runs on the host computer, implementing the FPGA buffers/registers input/output and providing the software interface to higher level software or algorithms. QubiC engineering software consists of an application programming interface (API), a portfolio of quantum characterization verification and validation (QCVV) experimental scripts and a graphical user interface (GUI).
1) Application programming interface: The Python 3 based API compiles the quantum processor gate pulse specification and the quantum circuit description to gateware commands and pulse envelopes.
The quantum processor gate pulse specification contains two parts: the frequencies (readout resonator and qubit drive) that represent the specific properties of each qubit and the gates that drive interactions between the control system and the qubits. Each gate is a series of pulses defined by its destination, timing, carrier, amplitude and envelope. The quantum processor and gate specifications are captured in the JSON format file, which is generated or updated during the chip calibration.
The quantum circuit description can be written in our native function call or be imported from TrueQ [36]. The measurement result can also be sent back to TrueQ to allow for post-processing of all the data. A similar interface to Qiskit/OpenQASM/Cirq [37]- [39] is under development.
The compiler is the bridge to translate the circuit description into the envelope and command buffers. There are two distinct types of compilers in the QubiC API. The first one is the OPTM (OPTiMize gate) compiler which is used during the chip characterization and gate optimization. The OPTM compiler accommodates multiple different pulse envelopes, in length, shape or other parameters. The envelope buffers from all the processing elements are collected together and allocated dynamically so that they can all be used in the specified qubits. In the OPTM compiler, the circuit description is written in our native function call. One can add a gate onto a sequence at a specific time and modify the gate parameters at the compiling time. The validation test is necessary in the OPTM compiler and so it takes longer to compile.
Another compiler is the RUNC (RUN Circuit) compiler, which is used to run a quantum circuit with calibrated gates on all the qubits simultaneously. Since only a few predefined gates are applied for each qubit, the envelope memory can be pre-allocated statically to reduce the compiling time. In the RUNC compiler, the circuit description can be imported from other languages, which need to be translated to the QubiC format. The validation tests during compiling are skipped to execute long circuits efficiently in the RUNC compiler.
The OPTM and RUNC compilers coexisting in the QubiC software bring in the flexibility and efficiency for distinct control flows. The OPTM compiler targets a comprehensive chip calibration via tweaking multiple parameters with high accuracy in a broad range, while the RUNC compiler specifies a dedicated structure to perform the advanced quantum algorithms in an efficient manner. Both the OPTM and RUNC are 3-step compilers which are illustrated in Appendix.
2) QCVV experiments support: A calibrated quantum information processor is the necessary prerequisite to perform QCVV experiments. In the current QubiC engineering software, a series of scripts are developed to characterize the quantum information processor and optimize the gates to support the superconducting QCVV experiments. This type of characterization and optimization routine can also be adapted for other architectures at hand. Quantum processor characterization begins with time alignment, which measures the latency for the readout signal and aligns it with the DLO. The single-tone experiment involves measuring all the readout resonator frequencies on the readout bus [11]. We also conduct a punch-out experiment where the drive power is increased significantly to suppress the Josephson nonlinearity of the qubit, yielding a simple spectroscopic signature of viable qubits, and a coarse adjust of the readout amplitude needed to achieve linear operation [40]. The qubit drive frequency can be extracted from a two-tone spectroscopy experiment or the chevron pattern obtained from coherent oscillations. We drive Rabi oscillations with different pulse lengths or amplitudes, and derive a Gaussian mixture model (GMM) for qubit state discrimination. A readout correction is employed to statistically calibrate out the effect of classical readout bit-flip errors.
A bounded minimization method [41] is used to adjust the readout amplitude and frequency together with the qubit drive frequency to maximize the Rabi oscillation contrast. To increase the gate repeatability, the gate pulse length is set to be a multiple of the DAC sampling rate and the FPGA clock rate. The qubit drive amplitude is optimized for each gate by stacking multiple identical gates at the target pulse width to maximize the recovery probability [42], [43]. With the calibrated single-qubit gate, we can measure the qubit coherence time including the qubit relaxation time (T 1 ) and dephasing time (T 2 ). The residual oscillation frequency measured by the Ramsey experiment can help us finely tune the qubit drive frequency. The single qubit gate quality can be validated by the AllXY experiment [44] and by a conventional randomized benchmarking (RB) sequence [45].
Two-qubit gate calibration starts with optimizing the cross resonance (CR) pulse to reach full entanglement [46]. The single qubit gate parameters around the CR pulse to construct a CNOT gate are identified by a curve fitting of a full XYplane measurement of a degenerated state followed by a CR pulse [47]. With the circuits from TrueQ, we can execute a two-qubit RB measurement to obtain the two-qubit process fidelity.
3) Graphical user interface: The QubiC GUI (graphical user interface) is being developed to streamline and simplify the complex sequences of hardware calibration tasks.
The GUI client, which is implemented in Bootstrap and JavaScript, can be used to remotely control the quantum hardware connected by the internet.
The operator can change the qubit bias point in real time, initialize/terminate measurements, and display the results. Fig. 3 shows an example of the user-facing GUI web-page for generating a chevron pattern for coherent oscillations. The GUI server, which is implemented in the Python web framework Flask, runs on a Linux machine located in the proximity of the QubiC FPGA chassis. For any measurement requested by the client, the configuration and the measured raw IQ-pairs are saved in local files in the YAML and HDF5 data formats, respectively. The post processing is done on the server side and the plots are made available for the remote client. Any file saved by the GUI server is time-stamped, which allows for the retrieval of the history or tracking of the time stability of the hardware calibration constants. The finite state machine governs the internal logic of the server and the experiments are executed asynchronously allowing for an early termination by the client.

Gate Configuration Envelope Definition
(a) Gate configuration and envelope definition. The destination parameter is the destination qubit or readout to be controlled, which is named as dest in the gate configuration. The timing parameter consists of the pulse starting time (t0) and the pulse width (twidth). The carrier frequency (fcarrier) and the initial phase (pcarrier) values are encoded in the carrier parameter. The pulse amplitude (amp) is a fraction of DAC full scale. The envelope function (env) can be any Python function (commonly used or customized) returning a NumPy array. parametric waveform generation using the destination, timing, carrier, amplitude and envelope parameters.
A simple example is shown in Fig. 4a where we aim to generate a Y180 gate on Q6 (which is a 180 degrees singlequbit gate around the Y-axis of the Bloch sphere on a qubit labeled Q6) starting at some time (defined in the circuit) after the circuit starts. The in-phase and quadrature components are sent to the IQ channels for the Q6 qubit drive "Q6.qdrv" (dest). The pulse starts immediately (t0) after the gate starts, and lasts 96 ns (twidth). The carrier frequency is specified as "Q6.freq" (fcarrier), while the initial phase is "numpy.pi/2" (pcarrier). The overall amplitude of the pulse is 0.873 of the DAC full scale. The amplitude modulation is applied with a "DRAG" (derivative removal by adiabatic gate [48]) envelope (env) with appropriate parameters. This simple mapping from the gate configuration to the envelope definition function enables us to use any user provided Python function as the pulse envelope to construct a gate.
The above-mentioned Y180 gate pulse is generated by DAC pairs as IF I/Q signals. The IF signals are then up-converted in the up mixing module to an RF signal. In order to measure the Y180 gate pulse, the RF signal is directly connected back to the RF down mixing module, followed by the ADC digitization. As shown in Fig. 4b, we can successfully generate the parameterized RF pulse, which is essential to the pulse level experiments.

IV. TEST WITH QUANTUM PROCESSOR A. Randomized benchmarking
Leveraging standard qubit characterization and gate optimization protocols [47], the QubiC can automatically find and tune a two-qubit system. In order to validate the performance of the QubiC system on quantum hardware, we perform streamlined randomized benchmarking [49] on two of the qubits in an 8-qubit quantum processor [50]. As shown in Fig. 5, the single-qubit process fidelity [51], [52] is measured to be 0.9980±0.0001, while the two-qubit process fidelity is measured to be 0.948±0.004. The RB results demonstrate that the QubiC system can control and measure qubits efficiently, and it should be capable of delivering high-fidelity gates on state-of-the-art processors.

B. Randomized compiling
Randomized compiling (RC) is newly developed technique in quantum computing to tailor and mitigate noise [53], [54]. The RC protocol efficiently compiles an algorithm circuit in a number of different, but equivalent variations. Instead of executing just the original "bare" circuit, the protocol requires execution of all the variations of the circuit. On the conventional control hardware side, it may be challenging to create and upload the various pulse sequences without significant overhead. Here, we show that QubiC can execute this general, yet sophisticated compilation protocol on a quantum computer in an efficient manner.
On the host computer, the circuits are randomly compiled ("Compile") and transpiled to a device's native gateset ("Transpile") [36], [55]. Afterwards, QubiC transfers the native gate sequences to QubiC command sets ("Transfer") and then generates the sequences ("SeqGen"). The QubiC software prepares the hardware and transports the command and the memory to the QubiC hardware ("Run"). The qubit response is acquired from the FPGA ("Acquire") and processed by QubiC software to discriminate the state ("Process").
To evaluate RC efficacy, we compare the measured probability P(x) with the ideal probability P ideal (x) for the given circuit to calculate the total variational distance (TVD), which is defined as where x is the bit string. The TVD parameterizes the probability of measuring an incorrect solution.
We perform the two-qubit RC on the quantum processor, and measure the TVD distributions of bare circuits and RC circuits, as shown in Fig. 6. Compared to the bare circuits, lower TVD values are observed from the RC process, which means the output distributions are more accurate. Furthermore, QubiC can execute the RC protocol relatively quickly, as shown in Fig. 7. The total execution time grows linearly with the increase of the number of RC circuits or the number of two-qubit gates. The "Compile" and the "Transpile" account for the majority of the execution time, which are limited by the host computer performance. The major part of the QubiC execution time is the "Run", while command writing is the most time-consuming task in the "Run". One can observe that the "Run" time increases linearly with the number of RC circuits and the number of two-qubit gates respectively, since the command depth also grows linearly. The speed of the "Run" portion is currently limited by the constraint that the  load command only accepts 16k commands and takes ∼55 ms to execute. This can be made more efficient in future versions of the software. For a 600 µs relaxation time, we can load ∼100 circuits at a time. Currently QubiC takes <17 s for 80 cycles and 100 RC circuits with 1024 shots, which is efficient and promising.

V. CONCLUSION
We develop an open source FPGA based QubiC system which bridges the quantum algorithm and the quantum hardware implementation layers of the computing stack. The QubiC system includes the room temperature electronics hardware, the gateware, and the engineering software running on it to implement the qubit control pulses, and also to perform quantum state readout. QubiC allows researchers to access the full electronics hardware, gateware and software stack, which will enable the execution of a broader class of computation experiments while also facilitating the implementation codesign at each level of the stack in next generation systems. The QubiC prototype system functionality and performance were demonstrated by measuring single-qubit and two-qubit process fidelities. We obtained RB values of 0.9980±0.0001 and 0.948±0.004, respectively, on a 8-qubit superconducting quantum processor operating at the LBNL Advanced Quantum Testbed. Moreover, we demonstrated that QubiC has the capability to run advanced quantum algorithms such as randomized compiling with promising execution speed. QubiC can accommodate the full spectrum of users and developers, and will be a potential open source toolbox for the quantum community.

A. Compiling procedure
The compiler is the bridge in the software API to transfer the circuit description into the envelope and command buffers. The compiling procedure is shown in Fig. 8. The three steps of the compilation are: (i) Scheduler: The first step is scheduling, which takes in the circuit description together with the compiler configuration to generate the gate sequences with relative timing information. For the circuits imported from other language which does not include the timing information, such as OpenQASM, this step is necessary. However, if the circuit is written using native function calls, this step can be skipped by assigning an explicit start time to each gate.
(ii) Time-Pulse Pair: The second step is to combine the gate sequences with the gate configuration to generate a list of pulses described as TP (time pulse) pairs. The qubit chip and gate configuration are generated from the qubit characterization and gate optimization. The gate configuration contains information about the pulses used in the gate, including the carrier, the envelope, and the relative timing. The TP description contains the parameterized gate information, which can then be implemented using different electronics hardware setups. The conventional AWG contains idle periods of zero or constant output. Rather than inefficiently storing repeated values in the waveform memory, we instead employ the TP pairs to store the time and pulse envelope value in the waveform memory. At this level, the TP pair can still be human readable, so for the user who is familiar with the pulse should be able to understand the TP description and also check the relative pulse timing.
(iii) iNdex-Value Pair: The third step includes the hardware configuration, and generates the NV (iNdex value) pair as buffer value for the lower level. This is a hardware dependent layer. The hardware configuration contains the sampling rate, the physical wiring diagram between the DACs and the qubits and the gateware register maps. This only needs to be updated when the quantum chip or the chip wiring changes. Separating this step and configuration gives us the opportunity to run the same pulse on different hardware for comparison.
The outputs of the 3-step compiler are the envelope buffer, the command buffer and the simulator to visualize the pulse from the buffer values. The commands normally sent to the FPGA are redirected to the on-host analysis and visualisation package, when switching to the simulation mode, which allows verification of correctness of encoded gates. The final output from the API is the UDP (user datagram protocol) packet, which will be sent out over Gigabit Ethernet to the FPGA hardware.