Origin of Frequency-Dependent Distortion and Calibration for Ring Oscillator VCO ADCs

This brief identifies the cause of frequency-dependent distortion in ring oscillator voltage-controlled oscillator (VCO) analog-to-digital converters (ADCs). First, a VCO model is presented which takes into account the capacitance at the VCO terminals. This allows the most common drive configurations to be analyzed to determine the origin of the frequency-dependent distortion and the vulnerability of the different drive configurations. A conclusion is that voltage control is relatively robust against this effect. Based on the preceding analysis, a novel foreground calibration procedure is developed. The effectiveness of the proposed calibration method is demonstrated for a manufactured open-loop VCO ADC in 28nm CMOS and compared to results obtained using a prior art calibration method and results without calibration. For a $\mathbf {750 mV_{pp}} 26.5$ MHz signal, the proposed calibration procedure leads to an improvement in THD of 20 dB and 47 dB compared to results using prior art calibration and no calibration respectively.

The outline of this brief is as follows.Section II expands the VCO model of [19] to explain and model this effect.Section III proposes a novel foreground calibration procedure to resolve this issue.The procedure is applied to measurement data in Section IV.Section V concludes this brief.

II. ORIGIN OF THE FREQUENCY-DEPENDENT DISTORTION A. Expanded VCO Model
In [19] a VCO model, shown in Fig. 1 (middle), was introduced based on the VCO I-V characteristic.It consists of a diode between the VCO terminals.To explain the frequency-dependent distortion mentioned above, we propose an expansion of this model by including the capacitance at the VCO terminals.The analysis is presented for the case of simple invertor ring oscillator delay cells, but analogous results are found for other delay cells.Fig. 2(a) shows a VCO output with its driving and subsequent delay cell.Relevant parasitic capacitances at this output are indicated.External capacitances due to the readout are indicated as C ex,v and C ex,g towards V DD and ground respectively.Two states are shown, one where the output is low ('0', left) and one where it is high ('1', right).Transistors that are 'on' are modeled as 0 resistors to simplify the results.Transistors that are 'off' are shown in grey and modeled as an open circuit.This leads to the simplified schematics in Fig. 2(b).In both cases, each terminal is connected to V DD and ground via a capacitance.Both terminals are also connected to each other.
Notice that at any point in time, approximately half of the delay cells will have settled to the '0' state (left side of Fig. 2) and half to the '1' state (right side).There is also a single switching delay cell that is transitioning between the two states.However, as this occurs at a frequency much higher than the input frequency, a quasi-static contribution of the switching delay cell is assumed similar to [19].
The parasitic capacitance contributions from all delay cells are in parallel and can be summed to obtain the expanded model shown in Fig. 1 (right).The top and bottom terminal are  connected to V DD (via C tv and C bv ) and ground (via C tg and C bg ).The top and bottom are also interconnected via C tb .Note that only the current I VCO through the diode will contribute to the VCO frequency.
1) Current Control: We will first analyze the case of current control.The VCO is replaced by the equivalent model discussed above.The capacitors C tb and C bv are both connected from the bottom VCO terminal to V DD and are replaced by their sum C v = C tb + C bv .This results in the circuit shown in Fig. 3(a).The input transconductance will lead to a nonlinear current I in in function of the input voltage V in .Due to the nonlinear diode and transconductor, the voltage V tune will also be a nonlinear function of V in .Furthermore, the capacitances C v and C bg can also show nonlinear behavior in function of V tune and therefore V in .A representative simulation of V tune and C v +C bg using an ideal voltage-controlled current source is shown in Fig. 4. The charge Q c stored on C v and C bg is then a function of V in and can be found as This leads to an I VCO of We can now create an equivalent block diagram of the system.We will model I in (V in (t)) and Q c (V in (t)) as the nonlinear functions g[•] and h[•] respectively.Since the current I VCO passes through the nonlinear VCO frequency characteristic f [•] to obtain the VCO frequency f VCO , we find the block diagram shown in Fig. 5. Due to the chain rule for the derivative, it can be seen that the second term in (2) is proportional to the time derivative of the input signal.For a sinusoidal input, this will lead to terms proportional to the input frequency in I VCO , which is transformed to the VCO frequency f VCO through f [•].This explains the observed introduction of frequencydependent nonlinear components in the output signal.
2) Resistive Driver: The resistive driver can be redrawn using Norton's theorem to find the representation shown in Fig. 3(b).This is identical to Fig. 3(a) obtained above except for an added resistance R eq , which represents the parallel connection of R 1 and R 2 .I VCO can now be written as

) as nonlinear functions g[•] and h[•]
again leads to the model of Fig. 5.
3) Voltage Control: Analyzing Fig. 3(c), which represents the circuit using voltage control, we find that it is much more robust against frequency-dependent distortion.Since V tune ≈ V in , a current proportional to dV in dt flows through the parasitic capacitors C v and C bg .This current is delivered by the input voltage source V in and only has a small influence on I VCO .In practice, the voltage source will have an internal resistance R in .In this case, we can use Norton's theorem and find a Fig. 6.Prior art and proposed calibration, with decimation steps using a decimation filter ('dec') and calibration ('cal').
circuit equivalent to Fig. 3(b), with a current source V in R in and resistance R in .We again find the block diagram of Fig. 5.

C. Mitigation of Frequency-Dependent Nonlinearity
Besides the topology choice, the frequency-dynamic nonlinearity can be reduced in other ways.To improve the linearity using the resistive driver, R 1 and R 2 can respectively be increased and decreased.This will reduce the V tune swing and thus d(h [•]) dt .This will also increase the bias voltage over the VCO, avoiding the more nonlinear regions of the equivalent diode characteristic [19], leading to a more linear h [•].Additionally, this will improve the static frequency characteristic [7] at the cost of SNR.These options are also available using current control, by respectively reducing the I tune swing and increasing the bias current.Finally, an attempt can be made to reduce the capacitance present at the VCO nodes through careful layout.This is not always trivial.However, the large readout capacitances C ex in Fig. 2 can often be reduced by using buffers between the VCO and the subsequent samplers.
Depending on the required linear performance, these solutions might be insufficient.A novel calibration procedure will therefore be presented below.
In [12], an improvement to this scheme for high bandwidth VCO ADCs was developed.Here the calibration is executed on a partially decimated signal including a prior anti-aliasing filtering, as shown in Fig. 6 (blue).This improves the calibration quality by removing out of-band shaped quantization noise that would otherwise be partly converted to in-band white noise after passing through the nonlinearity correction block [12].As the methods described so far neglect the d(h [•]) dt contribution in Fig. 5, they are increasingly susceptible to added distortion at higher frequencies.We will present a solution to this issue in the next paragraph.

B. Proposed Foreground Calibration Method
To solve the frequency-dependent nonlinearity, we propose a foreground calibration method which includes the d(h[•]) dt term.First, one or more calibration measurements with preferably different input frequencies are performed where the ADC is driven by a sine wave and the output D is captured.The output can then be split into three components: (i) the fundamental sine wave, which corresponds to the signal component D sig , (ii) the distortion DIST, which corresponds to the instantaneous distortion of D sig and (iii) the noise r.This is done using a fit of the components at the input frequency f in and harmonics of f in , leading to D sig and DIST.The residue is the noise r.For this procedure, efficient sine-wave fitting algorithms such as IEEE-STD-1057 can be used [22].
For the fitting step of the calibration, we will use the clean output signal, which we define as the output signal without the noise: Here n represents the n-th sample.Using the clean output improves the quality of the calibration and reduces the necessary calibration measurement time.
Returning to the model of Fig. 5, f VCO will have a linear and constant component in terms of V in , i.e., the VCO gain K v and the rest frequency f 0 .The remaining components of f VCO lead to distortion and are modeled by the isolated nonlinearity function NL [•].Fig. 5 can then be redrawn to obtain the block diagram of Fig. 7, where NL[•] is a function of the input V in .However, if we assume it represents a weak nonlinearity, it is possible and much more useful to approximate it in function of the clean output signal D cl [23], as V in is unknown during normal operation.Based on Fig. 5, we can write this as with coefficients a i , b j and c k .c 1 can be included in a i and b j and is normalized to c 1 = 1.The time derivative is approximated as a difference: ).To correct the distortion, an estimate of NL[•] can be removed from the output.However, efficiently determining such an estimate NL[•] is not trivial, as it is no longer a simple polynomial.We propose a two-step procedure.First, an initial estimation of the coefficients âi,0 and bj,0 is performed by neglecting the terms in NL [•] with k > 1.The coefficients are found by minimizing the following least squares function using a QR matrix decomposition into basis Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.N i , N j represent the highest powers of the polynomials used for the fit.The initial estimate of the coefficients is now used for a complete fit, where all powers k up to N k are taken into account to obtain more accurate estimates âi , bj and ĉk .We again perform a least squares fit, now of Due to the two-step method, it is not necessary to split the higher-order terms with k > 1 into their constituent functions and fit them, which would be computationally expensive and require a large amount of calibration measurement data.Once the coefficients are known, these can be used for correction of the ADC output.During normal operation, NL(D) is subtracted from the ADC output to obtain the corrected output D corr , as shown in Fig. 6 (red).Similar to the work of [12] discussed above, this is applied to a partially decimated signal.
IV. RESULTS To demonstrate the performance of our calibration procedure, it is applied to measurement data of a VCO ADC prototype that was manufactured in 28nm CMOS, shown in Fig. 8.It is an open-loop pseudo-differential design using the resistive driver and operates at a clock frequency of 3.5 GHz with an OSR 16.The calibration is performed using N i = N j = 5, N k = 2 and a first decimation with a factor 4.
The nonlinearity correction is implemented off-chip in a bit-accurate manner, as shown in Fig. 9. D and D corr are represented as 14-bit fixed point numbers.Other calculations are performed with the same accuracy.The polynomials [•] are approximated using 512-element LUTs (LUT1 & LUT2 respectively) containing the polynomial values and linear interpolation is performed between the 2 points closest to the input of the correction block.For this, the 9 MSBs are used as the LUT addresses.The interpolation is performed by calculating LUT low + LSBs • (LUT high − LUT low ) using the 5 remaining LSBs (with proper bitshifting), similar to [10].As N k is only 2 in this example, the corresponding terms are calculated directly without using a LUT and subtracted from D. The derivative in the frequency-dependent terms is approximated as a difference.To evaluate the cost of an on-chip implementation, a possible implementation was generated using automatic synthesis and place and route tools.The estimated additional power consumption and area for the correction would be 2.2 mW (of which 1.4 mW in the LUTs) and 0.0015 mm 2 respectively.Fig. 10 shows the THD in function of the amount of calibration data samples.Other measurements in this brief are shown using mixed frequency data using 50000 samples.Fig. 11 shows the measured SNDR and THD for 750 mV pp sine inputs with different frequencies.The results obtained using the proposed calibration procedure are compared to results obtained without calibration and results using the previously discussed foreground calibration procedure from [12].At low frequencies, the performance of the two methods is nearly identical.At higher frequencies, the performance of the prior art calibration degrades due to the frequency-dependent nonlinearity, which is not considered.with prior art calibration and no calibration.Fig. 12(a) shows the measured output spectrum for this 26.5 MHz 750 mV pp signal before and after our proposed calibration method.Similarly, Fig. 12(b) shows the results of a two-tone test.After calibration, all intermodulation products are below 80 dBFS.Table I compares our results to previously published using VCO calibration.A similar THD to the best performing works in prior art is obtained, but at much higher bandwidths.
To further assess the proposed method for ICs with more nonlinearity than our prototype, it is stress-tested with synthetic datasets emulating circuits with uncalibrated THDs of up to −22 dB.These datasets are obtained by extracting the nonlinearity of the mixed frequency measurements, increasing it, applying it to a 26.5 MHz sine input and adding the original noise.The proposed calibration improves the THDs to at least −70 dB in all cases.These results show that our method works as intended and keeps functioning as expected even for very large nonlinearities as shown on the synthetic data.
V. CONCLUSION In this brief, an expansion of the VCO model of [19] including capacitance at the VCO terminals was introduced.This was used to explain and model the frequency-dependent distortion observed in VCO ADCs.Afterwards, a foreground calibration procedure was proposed and its effectiveness demonstrated for a manufactured VCO ADC, leading to an improvement of THD by 20 dB and 47 dB compared to results with prior art calibration and no calibration for a 26.5 MHz input.The proposed method represents a promising option to further improve the linearity of high bandwidth VCO ADCs.

Fig. 2 .
Fig. 2. Analysis of the capacitance of a simple delay cell with initial view (a) and simplified schematic (b).

Fig. 4 .Fig. 5 .
Fig. 4. Simulated V tune and C v + C bg in function of V in .

Fig. 10 .
Fig. 10.Worst obtained THD across measured frequencies for 750 mV pp inputs vs. amount of calibration data samples.
Without calibration, the lowest achieved SNDR & THD are 36 dB & −36 dB at 26.5 MHz.The prior art solution improves this to an SNDR & THD of 59 dB & −63 dB.The proposed method leads to an SNDR & THD of 62 dB & −83 dB.This represents an improvement in THD of 20 dB and 47 dB compared to results

Fig. 12 .
Fig. 12. Measured 131K-point output spectra averaged 3 times for single tone test with 26.5 MHz 750 mV pp input (a) and twotone test using 85 and 89.99 MHz -8.5 dBFS inputs (b) with no calibration and proposed calibration.

TABLE I STATE
-OF-THE-ART VCO CALIBRATION WORKS