Analysis of SAR ADC Performance Enhancement Utilizing Stochastic Resonance

Stochastic resonance (SR) is a phenomenon where the noise of a certain intensity helps to improve the signal-to-noise ratio (SNR) of nonlinear systems. This brief applies this concept to a successive approximation register (SAR) analog-to-digital converter (ADC) to enhance its performance. To improve the effective number of bits of the SAR ADC, some additional comparisons are repeated after the normal binary search. The theoretical analysis of the performance enhancement based on the statistical information provides the optimal number of additional comparisons in terms of the ADC figure-of-merit (FoM). As this scheme allows the use of a high-input-referred-noise but low-power comparator in the SAR ADC, the total power consumption can be reduced even with the additional comparisons.


I. INTRODUCTION
S UCCESSIVE approximation register (SAR) analog-to- digital converter (ADC) is one of the most widely-used ADC architectures, where a comparator makes decisions to quantize the input signal through binary search [1].In practice, to achieve the target signal-to-noise ratio (SNR) in the ADC, the input-referred noise of the comparator must be minimized well below the 1 least significant bit (LSB) resolution by proper design [2].Stochastic resonance (SR) is a phenomenon where noise of a certain intensity helps nonlinear systems to improve their performance [3], [4].SR has been studied in various fields such as optical systems [5], [6], electric and magnetic systems [7], [8] and neuronal systems [9].A handful of prior works applied this concept to enhance the performance of the ADCs [10], [11], [12], which demonstrated that the SNR of the ADC is improved by adding proper noise.
A typical N-bit SAR ADC repeats comparisons N times based on binary search.Through the course of comparisons, there always is at least one critical decision, where the voltage Manuscript received 24 May 2023; accepted 2 July 2023.Date of publication 5 July 2023; date of current version 8 December 2023.This work was supported in part by the Institute for AI and Beyond, The University of Tokyo; and in part by JST, CREST under Grant JPMJCR19K2; and in part by KAKENHI under Grant JP21H03406.This brief was recommended by Associate Editor Q. Liu.(Corresponding author: Tetsuya Iizuka.) Ryoya Shibata is with the Department of Electrical Engineering and Information Systems, The University of Tokyo, Tokyo 113-0032, Japan (e-mail: shibata@silicon.t.u-tokyo.ac.jp).
Tetsuya Iizuka is with the Systems Design Lab, School of Engineering, The University of Tokyo, Tokyo 113-0032, Japan (e-mail: iizuka@ vdec.u-tokyo.ac.jp).
Color versions of one or more figures in this article are available at https://doi.org/10.1109/TCSII.2023.3292318.
Digital Object Identifier 10.1109/TCSII.2023.3292318difference less than 1 LSB must be resolved.The comparator in the SAR ADC must be designed to have low-enough noise for this critical decision, while in other decisions the noise requirement is not that tight.Though the LSB decision at the end of the SAR conversion is always critical, it is normally difficult to identify in advance where the critical decision occurs at the middle of conversion.Some prior works such as [13] tried to find the location of the critical decision to optimize the comparator operation.It utilizes the comparator decision time to identify the critical decision then switches to the majority voting mode to mitigate the noise contribution.However, a majority voting does not make full use of the statistical information as it simply gives a 0/1 binary decision through multiple comparisons.To make better use of them, [14] proposed to increase the number of output levels by a tri-level voting scheme.In [15], the average of 8 LSB decisions is appended to the binary SAR output to enhance the number of bit resolution.Though these techniques successfully improved the ADC performance, the theoretical analysis to optimize the design has not been provided.In [12], statistical estimation methods such as the Bayes estimator are applied to accurately estimate a conversion residue.Reference [16] utilizes a majority voting with multiple comparisons for each bit decision to effectively realize a noise-tunable comparator using a high-input-referred-noise but low-power comparator multiple times.Though the analytical method proposed in [16] can assign the optimal number of comparisons for each bit decision when the total number of comparisons is given, based on the majority voting this method still can not fully utilize the statistical information from the multiple comparisons.
In this brief, based on the concept of SR, we present a method to enhance the bit resolution of the SAR ADC with simpler additional hardware and operation than those in [13], [15].By simply repeating the comparisons after the normal SAR binary search, a count of 1 outputs from the comparator is appended to the binary SAR output to increase the effective number of bits.This brief theoretically analyzes the performance of the SAR ADC followed by SR-based multiple comparisons, which is so-called SR SAR ADC.The analysis and simulation results demonstrate that the SNR of the SR SAR ADC depends on the comparator noise and can be optimized with proper noise intensity, which is the benefit of SR.With the relaxed noise requirement of the comparator, we can improve the power efficiency of the SR SAR ADC compared with the typical SAR ADC.In addition, to show the feasibility of the proposed SR SAR ADC, it is compared with the SAR ADC based on majority voting technique [16].

II. OPERATION OF THE PROPOSED SR SAR ADC
As shown in Fig. 1  Though ideally the two inputs to the comparator are fixed, the decision threshold of it is fluctuated in reality due to the comparator noise, which mainly comes from the transistors in the comparator [2].Thus the additional comparison results fluctuate and have statistical information of V CDAC .In the SR part, since the voltage difference between V CDAC and V th is small, the decision time of the comparator tends to be long, which leads to some decision errors due to metastability.We have checked with the behavioral simulations that even with 1 % decision error, its impact on the SNR is negligible.
In the proposed SR SAR ADC, the output of the counter, which is from 0 to 2 N SR − 1, is simply appended as N SR -bit binary format after the N SAR -bit binary code.Consequently, the output of the proposed SAR ADC is N = N SAR +N SR bits.Supposing that the input-referred noise of the comparator has Gaussian distribution, the count number in the SR part usually has nonlinear dependence on the CDAC residue, which may lead to harmonic distortions in the ADC output.As will be demonstrated in Section IV, however, the analysis only considering the noise agrees perfectly with the behavioral simulation result including the nonlinearity, which means that the impact of the nonlinearity due to the SR part is negligible.Thus the performance analysis in the next section ignores this nonlinearity and uses SNR as a performance metric.

III. PERFORMANCE ANALYSIS
To calculate the SNR of the proposed SR SAR ADC, we need to obtain the signal power P sig and the noise power P noise .Then the SNR is simply given by P sig /P noise .With a sinewave input whose amplitude is V r , P sig = V 2 r /2.In the proposed SR SAR ADC, we assume that the input-referred noise of the comparator is dominant, and other noise such as kT/C thermal noise and reference buffer noise is designed to be sufficiently low for the target SNR performance, so that these other noise sources do not limit the final SNR.With this assumption, we can calculate P noise with the statistical variance of the quantization error.In N-bit A/D conversion, when V in is the input value and V out (k) is the analog output value reconstructed from the digital output code k ranged from 0 to 2 N − 1, the quantization error E q is described as In N-bit ADC where the LSB voltage is denoted as = 2V r /2 N , which means that the input sinewave is full scale, the relationship between V out (k) and k is described as follows: P noise is calculated by multiplying the conditional expectation of E 2 q given V in and the probability distribution function of the input signal f (V in ), then integrating the product over the entire input voltage range.Therefore, P noise is given by where q and the probability of having quantization error E q , then summing the products all over the possible output codes.Therefore, where is the conditional probability of getting the output code k SAR and k SR in the SAR part and SR part respectively when V in is given.k SAR and k SR are respectively given by where k = k SAR +k SR .k b is a binary representation of k.Given V in , we describe the conditional probability of k SAR in the SAR part as P SAR (k SAR | V in ).Then the conditional probability of k SR in the SR part is described depending on the result of the SAR part as given by

A. The SAR Conversion Part
In N SAR -bit SAR algorithm, V CDAC is resolved through the N SAR -time binary search while its value is changed in N SAR steps as Then, the probability P th [i] where V CDAC [i] exceeds the threshold voltage of the comparator V th is described.Here, we assume the input-referred noise from the comparator has Gaussian distribution whose standard deviation is σ .Then P th [i] is given by Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.where The probability where As shown in Fig. 2, in a 2-bit SAR example, when [2]).In a general N SAR -bit case, P SAR (k SAR | V in ) is given by In the above equation, when

B. The SR Conversion Part
In N SR -bit SR part, the proposed SR SAR ADC repeats comparisons 2 N SR − 1 times with the fixed V CDAC and counts the number of 1 outputs from the comparator.V CDAC in the SR part is determined by the conversion result of the SAR part, which is described as V CDAC [N SAR + 1] and is constant throughout the SR part.The operation in the SR part is a random experiment where every outcome is either 0 or 1.The probability of 1 is constant at every comparison.This operation is called as Bernoulli or binomial trial [17].Therefore the probability exceeds the threshold voltage of the comparator k SR times is given by (10) With ( 5), ( 9) and (10), P(k SAR , k SR | V in ) can be calculated.An example of the decision tree when k = 9 and (N SAR , N SR ) = (2, 2) is shown in Fig. 3.In this example, the output is 4-bit as k b = {1, 0, 0, 1}, and V out is calculated by substituting N = 4 and k = 9 to (1), yielding V out = V r × 3/16.Then P noise is given by using ( 2) and (3) to calculate the SNR.

C. Extension to Majority-Voting-Based Technique
Since the performance analysis so far does not assume any specific usage of the comparator, it can be straightforwardly extended to analyze the performance of other ADCs using multiple comparisons.In this section, we apply our analysis framework to [16], which employs a majority voting, to demonstrate the feasibility of our analysis.In [16, (3)], the code mean-squared error (MSE) is defined as where k is an ideal output code in the absence of the comparator noise.Though the calculation of E[(k − k) 2 |V in ] is not explicitly described in [16], based on our analysis framework, we can derive its analytical expression, which is actually given by the same equation as (3), while the probability 3) must be replaced with Though the calculation of P(k | V in ) is different from that in a typical SAR operation due to the majority voting for each bit decision, it is derived in the same manner as for (9).Denoting the probability that majority voting in i-th bit decision results in 1 as When the number of comparisons in i-th decision is N i , P MV [i] is calculated in the same manner as for [16, (14)], which leads to In [16], the optimal number of comparisons for each bit decision is assigned to N i = [1 1 1 3 3 5 7 13 19 29] for 10-bit SAR ADC when the comparator noise σ = , where is the 1 LSB of a 10-bit ADC, and the total number of comparisons is restricted to 82.In this case, the code MSE they derived is 0.234, which perfectly agrees with the one derived through our analysis.

IV. EXPERIMENTAL RESULTS
In this section, we compare the proposed SR SAR ADC with a typical SAR ADC in terms of their figure of merit (FoM).Here we use Walden FoM defined as FoM = P ADC /(f s • 2 ENOB ), where P ADC and f s are the ADC power consumption and the sampling frequency, respectively.ENOB is an effective number of bits.In this brief, it is given by ENOB = (SNR[dB] − 1.76)/6.02.Here we assume that the sampling period of the N SAR -bit SAR ADC is T SAR = 1/f SAR = T S/H + N SAR T comp , where T S/H and T comp are the time to sample-andhold the input and the time for one comparison, respectively.We also assume that for the SAR ADC the energy consumption for one A/D conversion is given by E SAR = P ADC,SAR T SAR = E other + N SAR E comp , where E comp is the energy required for one bit decision in the comparator.E other is the rest energy for one A/D conversion, which is composed mainly of CDAC driver and S/H circuits in the SAR ADC.We suppose that Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.Assuming T S/H = cT SAR (0 < c < 1), for the typical N SAR -bit SAR ADC, the FoM is given by For the proposed SR SAR ADC, on the other hand, the number of comparisons becomes N SAR + 2 N SR − 1.Among these bit decisions, in the SR part the CDAC switches are fixed to have a constant V CDAC .Thus even with the additional SR comparisons, E other is not changed from the typical SAR ADC case, while the comparator consumes more energy for additional comparisons.The energy consumption of the comparator is in a trade-off relationship with its noise.Generally speaking, when we make the input-referred noise of the comparator ×b (b > 0), for the same speed, the comparator energy consumption becomes ×b −2 according to [2].In other words, if we want lower noise, we need to consume more energy in the comparator.Thus the total energy consumption of the SR SAR ADC for one A/D conversion is . Consequently, the FoM of the proposed SR SAR ADC is given by Here we assume that the power consumed by additional circuit blocks such as a counter is negligible.As a sanity check, when N SR = 0 and b = 1, which means that the circuit is operating as a simple SAR ADC, ( 15) is equivalent to (14).Sweeping N SR , the value FoM SR /(P ADC,SAR T comp ) of the proposed SR SAR ADC is plotted in Fig. 4 for two cases where N SAR = 10 and N SAR = 12.σ = / √ 12 comparator noise is used for N SAR = 10 and σ = /(4 √ 12) is used for N SAR = 12 where is 1 LSB of a 10-bit ADC, so that the original comparator has the input-referred noise comparable to the quantization noise.In the following experiments, we use b = 2 to assume the use of a lower-power but larger-input-referrednoise comparator for the proposed SR SAR ADC. a = 0.3 and c = 0.125 are reasonably assumed with reference to [1], [15].The ENOB in (15) was obtained with the analysis in Section III as well as with behavioral simulations.For behavioral simulations, as the random noise is involved, the average value of 128 simulation results is plotted for each point.Two results perfectly agree with each other in both cases, which proves the feasibility of the analysis.For the typical SAR ADC with b = 1 and N SR = 0, the ENOB in ( 14) was also obtained

Estimated Comparator
Noise in [16] Fig. 6.The SNR of the proposed SR SAR ADC versus the comparator noise normalized by , which is 1 LSB of a 10-bit ADC, when (N SAR , N SR ) = (8, 4) compared with the SAR ADC based on majority voting [16].and FoM SAR /(P ADC,SAR T comp ) values are indicated with dotted lines on the same graph.The proposed SR SAR ADC achieves the optimum FoM at N SR = 4 when N SAR = 10 and at N SR = 5 when N SAR = 12, which is more power efficient than the SAR ADC without the SR operation.Fig. 5 shows the dependence on the parameters a and c.Supposing that T comp is fixed by the comparator design, the FoM becomes worse when c increases as it simply slows down the sampling rate.When a increases, which means that the comparator power is more dominant in the ADC, the optimum N SR shifts to a lower value.Fig. 6 plots the SNR versus the standard deviation of the comparator input-referred noise σ normalized by 1 LSB of the 10-bit ADC .The cross marks and triangles show the cases without and with the redundancy,1 respectively.As expected, the SNR changes like a bell-shaped curve [4], which has a peak when σ is a certain non-zero value.Specifically, the SNR is optimal when σ is close to in both cases.
For the performance comparison, the SNR of the 10-bit SAR ADC using majority voting technique [16] is simulated and plotted with circles on the same graph by sweeping σ .Here, both in our SR SAR and the majority voting SAR ADCs, the total number of comparisons is the same.Based on the measured performance described in [16], the input-referred noise of their comparator is estimated to be σ = 1.65 .At this design point, the SNR of the proposed SR SAR ADC without redundancy is slightly below the SNR of the majority voting technique, while with redundancy it improves to the better value though it requires one more additional bit decision.In addition, by decreasing the comparator noise with some more power, the proposed SR SAR ADC becomes advantageous at around the peak of the bell-shaped curve.As the proposed SR SAR ADC in this comparison is an 8-bit architecture while the majority voting technique uses a 10-bit one, assuming the same power consumption in the comparator with the same number of total comparisons, the proposed technique is expected to be lower power with better SNR, which leads to better FoM at this design point.Interestingly, in the SR SAR ADC, suppressing the noise too much reduces the SNR, while in the majority voting its SNR monotonically improves with smaller noise.This phenomenon clearly demonstrates the effect of the SR that helps to improve the SNR of a nonlinear system with proper intensity of noise, which does not appear in the majority voting.For both schemes, repeating decisions with a too-low-noise comparator is not an efficient choice, as the lower-noise comparator usually requires more power and the SNR improvement is limited even with additional comparisons.
To find the optimal design point, Fig. 7 plots the analysis results of the SNR and FoM SR /(P ADC,SAR T comp ) by sweeping N SR and σ for N SAR = 10 as an example.For FoM calculation, a = 0.3 and c = 0.125 are used as in Fig. 4. To take into account the trade-off between the comparator power and its noise, we change the value of b along with σ based on b = σ/( /2 √ 12) where is 1 LSB of a 10-bit ADC.As shown in Fig. 7(a), when σ is close to , the SNR improves along with N SR but the improvement slows down at large N SR where a huge number of comparisons is required.Fig. 7(b) shows that the optimum FoM is achieved at N SR where the ENOB improvement is still significant with reasonable number of additional comparisons.When σ is too small the SNR does not increase with N SR , because here the residue voltage from the CDAC plus the noise can hardly cross the threshold in the SR part.In consequence, as we can not obtain meaningful statistical information, the SR part does not contribute to improve the SNR with too small comparator noise.
V. CONCLUSION In this brief, we analyzed the performance enhancement of the SAR ADC by introducing the concept of SR.The results of the analysis and the simulation reveal that with the proposed SR SAR ADC we can achieve better FoM by using a higher-input-referred-noise but lower-power comparator.

Fig. 1 .
Fig. 1.A conceptual block diagram of the proposed SR SAR ADC.

Fig. 5 .
Fig. 5. FoM SR /(P ADC,SAR T comp ) versus N SR when N SAR = 10 and b = 2 with different a and c values.
, the proposed SR SAR ADC is composed of a sampling switch, a binary-weighted c 2023 The Authors.This work is licensed under a Creative Commons Attribution 4.0 License.
For more information, see https://creativecommons.org/licenses/by/4.0/Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.