0.52-mW 30-GHz LNA in 22-nm FDSOI CMOS

This brief reports a novel low-power 30GHz LNA in 22nm FDSOI CMOS technology. The LNA is based on an active network with CMOS inverting amplifier stages, and input and output feedforward impedance matching networks. It exhibits a peak gain of 11.4 dB, a noise figure of 5.8 dB, with a record power consumption of 0.52 mW from a 0.8 V supply. Owing to its circuit topology, the LNA is compact in size and its core area amounts to <inline-formula> <tex-math notation="LaTeX">$0.20\times0.22$ </tex-math></inline-formula> mm2.

Index Terms-Low noise amplifier, low power, mm-wave, sub-mW.

I. INTRODUCTION
T HE CONSTANT evolution of silicon microelectronic technologies has led to the development of innovative ultra-scaled transistors (active devices) capable of outstanding performances.MOSFETs in cutting-edge CMOS technologies have reached peak transition frequency (f T ) and maximum oscillation frequency (f max ) higher than 300 GHz [1], [2], [3].For instance, thin oxide n-MOSFETs in 22nm FDSOI CMOS technology exhibit f T /f max as high as 347/371 GHz [2].The high values of f T and f max are key enabling factors for emerging applications, such as 5G [3], [4], 6G [5], IoT [3], and quantum computing [6].
The traditional design paradigm for microwave and mmwave integrated circuits relies on the cascade connection of active LC resonant stages [7], [8], [9], [10], [11], [12], [13], [14], made of transistors and large passive components, such as metal-insulator-metal capacitors, spiral inductors and transformers, and transmission lines (TLs).These are typically fabricated with the top thick metal layers of the back-endof-line (BEOL) in order to limit the losses and capacitive effects towards the substrate.Despite the transistors have reached high f max and low values of minimum noise figure (NF min ) [1], [2], [3], their full potential at the microwaves and mm-waves is severely impaired by the losses in passive components [15], [16], [17], especially for very low power consumption (P C ) where losses dominate [15], [16], [18].In order to compensate the losses introduced by the passive components and their interconnections, including vias, from the transistor level all the way up the top thick metal layers of the passives, the current consumption of the transistors has to be increased to reach the desired performances.Compact broadband amplifier solutions with no LC resonant stages are attractive, also in terms area (e.g., [19]), but the inherent parasitic capacitances limit the desired maximum frequency of operation, which is typically mitigated by increasing the power consumption.Overall, low-power amplifier solutions with small footprint on silicon die are very attractive for microwave/mm-wave radios and radars based on phase-array transceivers with a large number of array elements [20], but also for qubit control circuits in monolithic quantum processors scalable to large number of qubits [21].
In this brief, we report the design of the 30GHz low-power low noise amplifier (LNA) based on an active network (AN) circuit topology in Fig. 1.This approach with no passive components in the active network breaks the well-established design paradigm above, providing reasonable performances with lower power consumption.In [20] we have addressed its application as variable-gain low noise amplifier for lowpower tapered mm-wave 5G/6G phased-array receivers.In [21] we have addressed the design implementation tailored for 60 GHz operations at cryogenic temperatures (2K) as a key circuit, i.e., a "qubit size" amplifier for qubit control in monolithic quantum processors.In this brief we present all the features of the low-power amplifier topology of Fig. 1 together with its more inherent as well as more comprehensive design aspects for 30GHz operations and its experimental characterization at room temperature, for more general purposes in microwave and mm-wave communication and sensing applications [22], [23], such as radars [24], [25], radiometers [26] and 5G/6G mobile broadband phased-array transceivers [27].
This brief is organized as follows.Section II addresses the circuit design and implementation, and the postlayout simulation (PLS) results.Section III reports the experimental results.Finally, in Section IV, the conclusions are drawn.

A. Active Network
The AN takes advantage of the complementary current reuse [28] and consists of a self-biased CMOS inverting (SBI) amplifier as a fist stage, followed by a Cherry-Hooper amplifier stage, which is made of a CMOS inverting (INV) amplifier and an SBI.Typically, low-power LNA designs exploit forward body-bias (FBB) to lower, in magnitude, the threshold voltage (V t ) of MOSFETs and, in turn, allow a reduction of the supply voltage (V DD ) [11], [12].However, FBB requires further control voltages and reducing V DD has detrimental impact on linearity [12].The LNA reported here is designed to operate at the nominal V DD of 0.8 V and zero back-gate voltages.
The process design kit (PDK) offers several transistor flavors [3], with different V t and allowed ranges for the back-gate voltages.To achieve the targeted power consumption (P C ) of 0.5 mW from the nominal V DD , we have selected regular-V t (rvt) transistors.All transistors are sized equally with gate width (W) of 3.9 µm.The even transistor sizing for all stages results from a trade-off between linearity and noise performances, and facilitates the layout implementation.
Fig. 2(a) reports the current density (J), i.e., the ratio of the source current of the p-MOSFET and W, the maximum stable gain (G MS ), and NF min of the INV as a function of the DC gate voltage (V G ).
At V G = 396 mV ≈ V DD /2, the DC drain voltage V D amounts to 397 mV ≈ V G and the INV exhibits the peak Moreover, the transconductances of the n-MOSFET and p-MOSFET amount to 3.2 mS and 2.9 mS, respectively.The results prove that the n-MOSFET and p-MOSFET, equally sized, are well balanced, as strain technologies have mitigated the gap between electron and hole mobilities in n-MOSFETs and p-MOSFETs, respectively.Fig. 2(b) reports the G MS and NF min of the SBI as a function of the feedback resistor R f .As R f is increased from 3 to 10 k , NF min reduces from 2.6 dB to 1.5 dB and G MS increases from 10.3 to 11.6 dB.Larger resistors do not improve significantly the performance of the SBI, but lead to a less compact layout.Thereby, we have selected an R f of 10 k as a good tradeoff.Both V G and V D of the SBI are equal to 396 mV and the current density J amounts to 56 µA/µm, as for the INV.
The AN is self-biased: The two SBIs and the INV have V G = V D = 396 mV and are biased at the peak current density of 56 µA/µm.The AN draws 0.52 mW from the 0.8V supply.Fig. 3 shows that the stability factors k and µ of the AN are greater than unity and therefore the AN is unconditionally stable.
At 30 GHz, the AN exhibits a minimum NF (NF AN min ) of 1.86 dB and maximum available gain (G AN MA ) of 23.2 dB.The input impedance (Z AN in ) of the AN amounts to 292-j451 and its complex conjugate (Z AN in ) * is matched to the optimumnoise impedance (Z AN ON ) of AN.As a result, the coefficient , which provides a measure of the proximity between the two impedances, amounts to −12.1 dB.
As mentioned above, to fulfill gain and noise requirements, traditional mm-wave LNA design rely on cascading multiple active LC resonant stages [7], [8], [9], [10], [11], [12], [13], [14].However, these results show that the outstanding performances of ultra-scaled active devices allow the AN to reach adequate performances at 30 GHz, so avoiding the losses (including those of the interconnections and vias through the BEOL) and power and area penalties caused by bulky spiral inductors, transformers, and TLs.

B. Matching Networks
On the basis of the AN performances, the LNA holds the potential to achieve |S 21 | 2 = G AN MA = 23.2dB and NF ≈ NF AN min = 1.86 dB at 30 GHz.However, the full potential of the AN can only be achieved with ideal lossless reciprocal MNs [16].
Because of the IMN losses, the equivalent noise temperature T N of the LNA has the following lower bound [16]: where T 0 = 290 K, T AN Nmin is the minimum equivalent noise temperature of AN, and G IMN A is the available gain of IMN.The IMN is designed to maximize the power transfer at the input port of the LNA.This requirement leads to MNs with a quite large impedance transformation ratio, which is common in low-power designs [12], as the power budget constrains the maximum gate width of the MOSFETs and therefore the input impedance of the active stages is typically much larger than 50 .The J adopted in our LNA design is 2-5 times lower than the optimum-NF min and peak-f max current densities applied in conventional mm-wave LNA designs [9], [11], [13], so leading to larger W and reduced Re{Z AN in } and Im{Z AN in } for the given drain current.To optimize the performances of the LNA with lossy IMN, we have applied the loss-aware design methodology in [15], [16], [18], i.e., input integrated matching for maximum power transfer and minimum cascade noise.
Fig. 4(a) reports the equivalent circuit of the IMN, where R P and R S denote the parasitic series resistances of the primary and secondary spirals of the transformer, with self-inductance L P and L S , respectively, and intrinsic Q-factors Q P and Q S , respectively, M denotes the mutual inductance, and Q PM = ω(L P + M)/R P >> 1 denotes the equivalent quality factor of the primary spiral.G IMN A is bounded by the maximum available gain of the IMN, which is, for a reciprocal network, solely determined by the stability factor [16], here denoted as k IMN .Q SM = ω(L S + M)/R S is the equivalent Q-factor of the secondary spiral and n M = (L S + M)/(L P + M) is the equivalent turn ratio.Neglecting the losses in the capacitors, we get ( As M increases, n M decreases while Q SM and Q PM increase, which, in turn, improves k IMN .Thereby, the coupling coefficient k PS of the transformer can be used as a free parameter to minimize G IMN A and, in turn, minimize the noise temperature T IMN+AN N of the cascade of the IMN and AN, i.e., the cascade noise [16].The results of the input integrated matching for maximum power transfer and minimum cascade noise applied to the schematic design of the IMN are reported in Figs.5(a  The OMN employs the same transformer as IMN and the capacitors in OMN are fine-tuned to achieve maximum power transfer at the output port.
Last, a further consideration it is worth mentioning that, despite this design is focused on the proof of concept of the approach reported above, using the coupling factor to accomplish primarily the noise performance.Alternatively, the coupling factor could be used as a design parameter to adjust other circuit performance, such as the bandwidth extension of the input impedance matching.However, this may depend also on the entity of the desired bandwidth performance.Likely accomplishing specific bandwidth extensions could require more sophisticated matching networks with some further circuit element to be used as an additional design parameter.However, these additional considerations go beyond the work reported in this brief.

C. Design Implementation
The technology offers several BEOL stack options [9], [13].The selected option [9] includes nine copper metal layers (ML 1 -ML 9 ) and one aluminum cap layer (ML 10 ).The layout of the custom-designed transformer is shown in Fig. 4(b); it is implemented in the two topmost thick copper metal layers (ML 8 and ML 9 ) [9].The electromagnetic (EM) simulations have been performed in Momentum by Keysight Technologies.The circuit sizing is reported in Table I.Fig. 5(c) reports the results of the PLS.The LNA exhibits S 21 of 11.8 dB and NF of 5.5 dB at the center frequency (f 0 ) of 30 GHz with a power consumption of 0.52 mW.The LNA exhibits an input-referred 1dB compression point (iP 1dB ) of −24.1 dBm at f 0 and an input-referred 3 rd order intercept point (iIP 3 ) of −15 dBm for two tones at 30.0 and 30.1 GHz.Fig. 6 shows the die micrograph.The core area amounts to 0.20 × 0.22 mm 2 .

III. EXPERIMENTAL RESULTS
On-die measurements have been carried out with the Keysight PNA-X N5245A and FormFactor Infinity Probes GSG i40.Power calibrations were carried out with the power meter N1914A and power sensor N8487A by Keysight.The measurement results are reported in Fig. 7. Fig. 7(a) plots the S-Parameters and NF.The LNA exhibits f 0 of 30.1 GHz, S 21 of 11.4 dB and NF of 5.8 dB.Fig. 7(b) reports the transducer gain (G T ) of the LNA as a function of the input power (P in ) at 30 GHz.The LNA exhibits iP 1dB of −24.9 dBm.Also, Fig. 6(b) reports the results of the two-tone test with a frequency spacing of 100 MHz; the iIP 3 amounts to −14 dBm.
Overall, the measurements show a very good agreement with the PLS results, so demonstrating the effectiveness of the LNA design approach and methodology presented above.In such a design approach, unlike the common microwave/mmwave design approaches, the amplifier stages of the ANs do not include any spiral inductors/transformers for peaking and inter-stage matching networks that require connecting the transistors to the top metal layers all through the BEOL and then introduce substantial losses.This design paradigm shift leads to very compact layouts with reduced parasitics and allows taking better advantage of the inherent performance of ultra-scaled MOSFETs, as these are not heavily impaired by lossy interconnects whose effects are predominant in lowpower designs at high frequencies.However, the effectiveness of this approach reduces as the operating frequency increases, due to the inherent parasitic capacitances of the MOSFETs.Altogether, the results reported here demonstrate the very high potential as LNA element for microwave/mm-wave 5G/6G radios and radars based on phase-array transceivers with a large number array elements [20].However, in [21] we have shown that with the same technology process, i.e., 22nm FDSOI CMOS, it can be still a viable design approach also for operations at 60 GHz, and possibly even beyond owing to the increase of gain, and reduction of thermal noise and losses at cryogenic temperatures.
Table II summarizes the LNA performances and reports the comparison with the prior-art low-power LNAs in the relevant microwave/mm-wave frequency range.The LNA achieves a record P C , about 45% to 95% lower than prior-art low-power microwave/mm-wave LNAs.Among the sub-mW LNAs, it exhibits the best iP 1dB , −3dB bandwidth (BW 3 ) and −10dB bandwidth (BW 10 ), and it has the most compact core area.

IV. CONCLUSION
This brief reports a very low-power microwave/mm-wave LNA in 22nm FDSOI CMOS.The LNA consists of a novel circuit topology with a compact broadband active network and input and output impedance matching networks.The 0.52-mW 30-GHz LNA in 22-nm FDSOI CMOS Michele Spasaro , Member, IEEE, and Domenico Zito , Senior Member, IEEE Abstract-This brief reports a novel low-power 30GHz LNA in 22nm FDSOI CMOS technology.The LNA is based on an active network with CMOS inverting amplifier stages, and input and output feedforward impedance matching networks.It exhibits a peak gain of 11.4 dB, a noise figure of 5.8 dB, with a record power consumption of 0.52 mW from a 0.8 V supply.Owing to its circuit topology, the LNA is compact in size and its core area amounts to 0.20 × 0.22 mm 2 .

Fig. 2 .
Fig. 2. (a) Performances of the INV versus V G : Current density (J); G MS and NF min at 30 GHz.(b) G MS and NF min of SBI at 30 GHz.

Fig. 3 .
Fig. 3. Stability factors k and µ of the AN: The AN is unconditionally stable.

1 ;
) and (b).Fig. 5(a) reports the T IMN+AN N and θ LNA Fig. 5(b) reports the S 11 of the network formed by the IMN and AN

Fig. 5 .
Fig. 5. Design of the IMN (Q P = Q S = 10, L S /L P = 2, C I1 = 100 fF, C I3 = 26 fF): (a) Equivalent noise temperature (T IMN+AN N ) of the cascade of the IMN and AN, i.e., IMN + AN, theoretical lower bound θ LNA 1 , and (b) S 11 of IMN + AN for different values of the coupling coefficient k PS .(c) PLS results: S-parameters, NF, and NF min of LNA.

Fig. 7 .
Fig. 7. Measurement results: (a) S-parameters and NF; (b) G T at 30 GHz as a function of the P in ; IP 3 for two tones at 30.0 and 30.1 GHz.

TABLE II SUMMARY
OF PERFORMANCE AND COMPARISON WITH PRIOR-ART WORKSLNA has been designed and implemented for operations at 30 GHz, and shows good performance with a record power consumption of 0.52 mW and area on silicon, and among the sub-mW LNAs exhibits comparable noise and gain performances, lowest power consumption, best iP 1dB and largest bandwidth.