A 79.2-μW 19.5-kHz-BW 94.8-dB-SNDR Fully Dynamic DT ΔΣ ADC Using CLS-Assisted FIA With Sampling Noise Cancellation

This brief proposes a fully dynamic discrete-time (DT) <inline-formula> <tex-math notation="LaTeX">$\boldsymbol {\Delta }\boldsymbol {\Sigma }$ </tex-math></inline-formula> ADC using a correlated level shifting (CLS)-assisted floating inverter amplifier (FIA) with a sampling noise cancellation (SNC) technique. The CLS-assisted FIA improves amplifier gain with a single-stage configuration, which has lower input-referred noise than the cascaded one. In combination with the proposed SNC, the noise contribution of the 1 <inline-formula> <tex-math notation="LaTeX">$^{\mathrm{ st}}$ </tex-math></inline-formula>-stage integrator can be minimized. We also propose a novel passive integrator cascaded with a passive adder that avoids unwanted inter-stage loading without a speed penalty. The prototype of the proposed ADC fabricated in a 65nm bulk CMOS process realizes a fully dynamic operation and achieves 94.8 dB SNDR with an OSR of 256 for 19.5 kHz bandwidth while consuming 79.2<inline-formula> <tex-math notation="LaTeX">$\boldsymbol {\mu }\text{W}$ </tex-math></inline-formula> from a 1.2V supply at a 10 MHz sampling frequency. The Schreier and Walden FoMs are respectively 178.7 dB and 45.2fJ/conv.-step, which are the best among recent fully dynamic DT <inline-formula> <tex-math notation="LaTeX">$\boldsymbol {\Delta }\boldsymbol {\Sigma }$ </tex-math></inline-formula> ADCs with similar bandwidth.


I. INTRODUCTION
D ISCRETE-TIME (DT) ADCs using dynamic amplifiers [1], [2], [3], [4] are suitable for the analog front end of various sensor devices thanks to their scalability in power consumption with the operating frequency, compared to the DT ADCs using conventional amplifiers. Recently, a floating inverter amplifier (FIA) [5] has been widely used as a power efficient dynamic amplifier [1], [2], [3], [4], [5], [6], [7]. The FIA offers a stable output common-mode voltage as well as robustness to the input common-mode fluctuation as it works in its isolated power domain powered by a floating reservoir capacitor. To achieve high resolution with a DT ADC, the noise contribution of each building block has to be carefully optimized. Suppose that the quantization noise is usually designed to be lower than other random noise within signal band, the input sampling noise and the input-referred noise of the 1 st -stage integrator usually have dominant contribution as these noise are not mitigated by noise-shaping. When FIA is used as an amplifier in the integrator, the input-referred noise of the integrator for a single-stage FIA and a two-stage one are respectively given by 2kTγ /C S and (2kTγ /C S ) × Gm 2 Ro 1 [3], [8]. Here, k, T, C S , and γ are Boltzmann's constant, absolute temperature, input sampling capacitance and noise factor of a transistor, respectively. Gm 2 and Ro 1 are the transconductance of the 2 nd -stage amplifier and the output resistance of the 1 st -stage amplifier at the end of the amplification phase, respectively. Although the singlestage FIA has lower input-referred noise than the two-stage one by a factor of Gm 2 Ro 1 , the gain of the single-stage FIA is not high enough to suppress the subsequent stage noise and quantization noise to negligible level. There are two architectures to solve this trade-off. One is a single-stage cascode FIA [3], which improves the gain of the FIA without degrading its noise performance, but results in a reduced output voltage range. The other one is an amplifier using correlated level shifting (CLS) technique. A single-stage FIA with CLS (CLS-FIA) [2] can also improve the gain without noise penalty by two-phase operation. By employing these amplifier architectures, the noise contribution of the integrator can be efficiently suppressed, thus the input sampling noise becomes the most dominant source and limits the performance of DT ADCs. It has been demonstrated that the input sampling noise improves by adopting the cancellation or attenuation techniques [9], [10], [11], [12], [13]. To the best of authors' knowledge, there is no sampling noise cancellation (SNC) technique for switched-capacitor integrators, as it was not so meaningful when the input-referred noise of the amplifier dominates the total noise performance. However, CLS-FIA shows excellent input-referred noise performance and therefore the sampling noise becomes dominant noise source in an integrator with CLS-FIA. In this brief, the SNC applied to the switched-capacitor integrator is proposed. The proposed technique efficiently combines the SNC with a single-stage CLS-FIA in a switched-capacitor integrator. By sharing the output capacitor for CLS operation also for the SNC purpose, the noise performance of the integrator can be improved with minimal circuit penalty. In addition, to lower the power consumption of the overall ADC while achieving higherorder modulation, a novel passive filter cascaded with a passive adder is also proposed. The proposed passive filter avoids the noise transfer function (NTF) degradation due to unwanted inter-stage charge sharing. These proposed techniques are demonstrated in a single-loop 3 rd -order fully dynamic DT ADC.
II. PROPOSED CLS-ASSISTED FIA WITH SNC Figure 1(a) illustrates the schematic diagram of the integrator using the proposed CLS-assisted FIA with SNC. A simple non-cascoded FIA [5] is employed for the amplifier, but two reservoir capacitors are integrated for consecutive SNC and CLS operations as shown in Fig. 1(b). By using two separate reservoir capacitors instead of a single large one, more stable gain during SNC as well as faster slew rate at the beginning of CLS are achieved. By applying CLS, the effective gain of the FIA is boosted by the two amplification phases, estimation ( A1 ) and level shift ( A2 ) as shown in the output waveform of the FIA V OUT in Fig. 1(c) [2]. To implement SNC, two capacitors C SNC and a few switches are added as indicated by the red lines in Fig. 1(a). For SNC operation, the input sampling capacitor C S first samples the input signal together with the sampling noise at the falling edge of SE at t 1 in Fig. 1(c). Then, while SNC is high, the FIA is activated to amplify the input voltage change and sampling noise. When S becomes low at t 2 , the FIA output is sampled by C SNC .
At this moment, V SNC , the voltage across C SNC , is given by where A OP , V IN , v ns and v nsnc are the open loop gain of the FIA, the input voltage, the sampling noise, and the noise sampled by C SNC , respectively. Next, during the amplification phase ( A ), both the charge on C S and C SNC are transferred to the integration capacitor C I . At the end of the amplification phase t 4 , the output voltage V OUT is given by (2) where N represents the number of cycles. By substituting (1), this equation is rewritten as follows: As given by (4), the sampling noise v ns is ideally cancelled and the additional noise v nsnc is attenuated by A OP . According to [5], A OP can be approximated for the FIA as follows: where n, q, C RES , and V S are the weak-inversion slope factor, elementary charge, the reservoir capacitor, and the change of input transistor's source voltage in the FIA at the end of amplification, respectively. Using this approximation, the additional noise at the output is given by As shown with this equation, by combining the proposed SNC with CLS, C CLS is efficiently reused to suppress the additional noise. In this brief, C SNC = 60 fF, A OP = 8, C CLS = 420 fF and C S = 480 fF are used. Substituting these values to (6), the proposed SNC reduces the sampling noise by 82%. Assuming γ = 2/3 [14], the total noise of the 1 st integrator is suppressed by 44%, which is translated to 2.6 dB SNR improvement. When there is a gain error in A OP , the sampling noise is not completely canceled and appears at the output. Based on process-corner simulations with a temperature range of 0 • C to 80 • C, A OP fluctuates at most 30%. This gain error introduces less than 0.4 dB SNR drop. Therefore, we do not implement a gain tuning capability to avoid performance overhead as well as more design complexity.
III. PROPOSED DISCRETE-TIME ADC Figure 2 illustrates the schematic and timing diagrams of the proposed DT ADC. The ADC consists of a single-loop 3 rd -order 1.5-bit modulator with an input feed-forward path. The 1.5-bit quantizer is chosen because the number of comparators is limited to only 2 thus the DWA is not required, while compared with the 1-bit case, the quantization noise of the 1.5-bit quantizer is smaller and the voltage swing can be limited, which relaxes the requirements for the FIA-based  amplifiers. The 1 st and 2 nd integrators are each composed of the CLS-assisted FIA, with and without SNC, respectively. For the 3 rd stage, the proposed passive integrator described in Section IV is used to minimize the power consumption without penalizing the FoM. To reduce the effect of 1/f noise on the ADC, chopping of the FIA is employed for the 1 st stage. V CM is set to V DD /2. The 1.5-bit quantizer is composed of two StrongARM latch comparators [15]. The reset and amplification phases of the FIAs in the 1 st and 2 nd integrators are operated alternately with a half-cycle phase difference. Figure 3(a) illustrates the signal flow graph of the modulator. The scaling factors are determined by behavioral simulation to ensure that the amplifier outputs are within an appropriate range, e.g., from 200 mV to 1 V. The quantizer gain of 8.5 was adjusted with the reference voltages of the comparators, which are externally provided in the prototype in this brief. Figure 3(b) shows the noise breakdowns of the proposed ADC without and with the SNC. The contributions of other noise sources such as the 2 nd -stage amplifiers are about 0.1% and thus ignored. Though the 1 st -stage noise contribution is slightly increased by employing the SNC, about 44% of the total noise is reduced. The signal transfer function (STF) and noise transfer function (NTF) of the modulator normalized by the sampling frequency are shown with solid lines in Fig. 4. The STF is flat at low frequency, and the NTF exhibits nearly 3 rd -order noise shaping characteristics (60 dB/dec).

IV. PROPOSED PASSIVE INTEGRATOR
WITH PASSIVE ADDER As shown in Fig. 2, the 3 rd stage of the modulator consists of a passive integrator. In the conventional two-stage passive integrator, the signal is transferred from the 1 st stage holding capacitor to the 2 nd stage sampling capacitor by connecting them with a switch, without buffer amplifiers. Therefore, the charge in these capacitors can move in both directions, which is so called inter-stage loading effect [16]. If the passive integrator is applied to a modulator, it causes an unintentional feedback path, resulting in the degradation of the noise shaping characteristics and loop stability. In our work, this unwanted effect will happen between the 3 rd -stage passive integrator and the subsequent passive adder. Supposing that this unwanted effect exists in our signal flow graph in Fig. 3(a), the STF and NTF are both changed to the ones shown with dashed lines in Fig. 4, which exhibit the degraded noise shaping characteristics as well as the peaking due to the reduced phase margin. Moreover, especially in our architecture that uses the passive adder cascaded with the passive integrator, this inter-stage loading will also affect to the scaling factors of the feed-forward paths in the actual implementation, which substantially changes the loop characteristics. To overcome the inter-stage loading effect, a charge-sharing rotation technique is proposed in [16], but it requires three phases: sampling, 1 st -stage integration, and 2 nd -stage integration. Figure 5 shows the proposed passive integrator, whose operation is outlined as follows. First, the sampling capacitor C S31 samples the input voltage. Next, C S31 is connected to the integration capacitor C I3 . In the next sampling phase, C S31 is floated while the replica sampling capacitor C S32 samples the next input voltage. Finally, the C S31 is connected to the output while C S32 is connected to the integration capacitor C I3 . In short, the proposed architecture uses two sampling capacitors in a ping-pong manner to realize integration in two phases. Even though some additional noise is introduced by this pingpong structure, it will be mitigated by 2 nd -order noise shaping through the loop.
V. MEASUREMENT RESULT The prototype of the proposed DT ADC is fabricated in TSMC 65 nm bulk CMOS process. Figure 6(a) shows a die micrograph. The active area of the ADC is 180 μm × 265 μm. The measurement setup of the prototype uses a Stanford Research System DS360 and a Tektronix AFG31252 function generator as the differential input signal and clock sources, respectively. The 1.5-bit bitstream output is captured by a Digilent Digital Discovery logic analyzer and then processed with a PC. The ADC consumes 79.2 µW with SNC and 74.0 µW without SNC from a 1.2 V supply at 10 MHz sampling frequency. Figure 6(b) shows the power breakdown of the ADC with SNC, where the analog and the digital parts  consume 35.7 µW (45%) and 43.5 µW (55%), respectively. Figure 7 shows the measured output spectrum of the ADC with −1.1 dBFS input at 2.01225 kHz with a blue line. The ADC achieves 94.8 dB SNDR and 95.7 dB SNR with the OSR of 256. SFDR is 105.9 dB. The Schreier and Walden FoMs are 178.7 dB and 45.2 fJ/conv.-step, respectively. As shown in Fig. 7 with the red line, SNR is 94.0 dB without SNC, which indicates that the proposed SNC improves SNR by 1.7dB. 1 Figure 8 shows the measured SNDR/SNR versus the input amplitude. The ADC achieves 92.0 dB DR. The measured DR is limited by idle tones that become prominent when the input signal amplitude is below −55 dBFS. Based on system-level simulations, these idle tones are expected to be caused by   the offset due to the mismatch in the switches and capacitors, and can be suppressed by adding dither. Figures 9 and 10 show the power consumption and SNDR/SNR versus the sampling frequency, respectively. The proposed ADC shows power scalability to sampling frequency thanks to its fully dynamic operation. The reduced SNDR at low sampling frequency is mainly caused by the leakage after the C RES in the FIA is almost fully discharged, which limits the amplifiers' output voltage swing and introduces some more distortion. Since the capacitance of the C RES is optimized for 10 MHz operation in this prototype, the SNDR is slightly reduced at low-samplerate operation. Table I shows the performance summary and the comparison with recent fully dynamic DT ADCs. The proposed ADC achieves the highest FoM S and the lowest FoM W among ADCs with bandwidth around 20 kHz.

VI. CONCLUSION
This brief proposes a fully dynamic 3 rd -order DT ADC using a CLS-assisted FIA with SNC. A novel passive filter cascaded with a passive adder is also proposed to avoid the unwanted inter-stage loading effect while saving power for higher-order noise shaping. The measurement results of the prototype fabricated in a 65 nm CMOS process demonstrate that the SNR improves 1.7dB by enabling the proposed SNC in the CLS-assisted FIA. The proposed ADC exhibits the best FoM S and FoM W among recent fully dynamic DT ADCs with similar bandwidth.