Fully Dynamic Discrete-Time ΔΣ ADC Using Closed-Loop Two-Stage Cascoded Floating Inverter Amplifiers

This brief proposes a fully dynamic discrete-time <inline-formula> <tex-math notation="LaTeX">${\Delta }{\Sigma }$ </tex-math></inline-formula> ADC using closed-loop two-stage cascoded floating inverter amplifiers (FIA). The proposed FIA uses a non-cascoded FIA as the <inline-formula> <tex-math notation="LaTeX">$1^{\mathrm{ st}}$ </tex-math></inline-formula> stage and a cascoded one as the 2 <inline-formula> <tex-math notation="LaTeX">$^{\mathrm{ nd}}$ </tex-math></inline-formula>. By using this arrangement as well as applying metal-insulator-metal (MIM) capacitors for floating reservoir capacitors, it stably achieves high gain even with the input common-mode voltage fluctuation without an additional CMFB nor calibrations. The proposed ADC fabricated in a 65nm standard CMOS process realizes a fully dynamic operation without calibration and achieves 88.5dB SNDR, 97.9dB SFDR with an OSR of 256. It consumes 43.5<inline-formula> <tex-math notation="LaTeX">${\mu }\text{W}$ </tex-math></inline-formula> from a 1V supply at a 10MHz sampling frequency.


I. INTRODUCTION
H IGH resolution analog-to-digital converters (ADCs) are always demanded and widely used especially for audio and sensor applications. For these purposes, among different ADC architectures, a ADC is often used thanks to its oversampling and noise-shaping properties [1]. A ADC usually uses operational transconductance amplifier (OTA), which is one of the most power-hungry components in the modulator [2], [3]. Recently, numerous IoT devices and systems that have multiple sensors are commonly employed [4]. To save power for an extended lifetime of those IoT systems, there is an increasing demand for the analog front end to have the scalability of the power and the operating speed in order to realize flexible system management. To achieve high resolution and high energy efficiency at the same time, one of the candidate architectures is noise-shaping SAR ADC, which can be fully dynamic [5], [6]. However, to achieve high SNR, a CDAC capacitance mismatch calibration that complicates the design is essential. In addition, since the CDAC capacitance tends to be large, driving the sampling capacitance also becomes challenging. A discrete-time (DT) ADC utilizing a dynamic amplifier is another candidate thanks to its simple structure without requiring complex calibration [7], [8]. However, using the dynamic amplifier in the loop has its drawbacks; Its moderate DC gain can not sufficiently suppress the thermal and 1/f noise contributions of the latter stages, which leads to the SNR degradation [7]. This issue is not resolved by increasing the OSR. Thus it is necessary to have high gain amplifiers even in high OSR modulators. In [8], an additional 1/f noise reduction circuit is required to improve the SNR. Another drawback is its unregulated output common-mode voltage. As the output common-mode voltage of the dynamic amplifier is typically dependent on the amplification time, the operating condition will change once the sampling frequency is altered. This prevents the scalable operation of the DT ADC. The latter issue has been addressed by a floating inverter amplifier (FIA) [9]. The FIA offers a stable output commonmode voltage as well as robustness to the input common-mode fluctuation as it works in its isolated power domain powered by a floating reservoir capacitor C RES . These properties are utilized in [10] to realize the scalability of power consumption with the sampling frequency in a DT ADC. However, to further improve the DC gain of the FIA with single-stage configuration, it requires large transistors with a large C RES , which would deteriorate its power and area efficiency. In [11], a closed-loop, three-stage cascoded FIA is proposed as a residue amplifier in a pipeline ADC. Though it achieves a DC gain of 82 dB, an additional common-mode feedback (CMFB) circuit is required to have a stable gain, which increases the power consumption and circuit complexity.
In this brief, a single-loop 2 nd -order fully dynamic DT ADC using a closed-loop two-stage cascoded FIA is proposed. Our two-stage cascoded FIA is composed of a conventional non-cascoded FIA as the 1 st stage and a cascoded FIA as the 2 nd . The proposed FIA achieves about 17 dB higher gain without an additional CMFB nor calibrations. By applying this FIA, the proposed 2 nd -order DT ADC fabricated in 65 nm CMOS realizes a fully dynamic operation and achieves 88.5 dB SNDR at a 10 MHz sampling frequency with an OSR of 256.
The rest of this brief is organized as follows. Section II describes the proposed two-stage cascoded FIA. Section III This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/   presents the implementation of the DT ADC using the proposed FIA. The measurement results of the prototype of the proposed DT ADC are summarized and compared with prior works in Section IV. Finally, conclusions are given in Section V. Figure 1 depicts the schematic diagram of the proposed twostage cascoded FIA. The 1 st stage is the conventional FIA and the 2 nd stage is the cascoded one, which has a high output impedance that boosts the gain. This high output impedance also contributes to lower the dominant pole frequency that leads to more phase margin, so that the proposed FIA realizes stable operation with the closed-loop configuration. V CM is chosen for the bias voltage of the cascode MOSFETs to avoid dedicated on-chip bias voltage generators. Although the gain of the 2 nd -stage cascoded FIA is sensitive to the input common-mode voltage since the bias voltage for the cascode transistors is fixed at V CM , its impact is highly relaxed with the proposed two-stage arrangement by applying the non-cascoded FIA as the 1 st stage whose output common-mode voltage is ideally constant. As reported in [9], however, the parasitic capacitance of the reservoir capacitor C RES degrades the stability of the output common-mode voltage. The change of the output common-mode voltage can be approximated as [9]

II. PROPOSED TWO-STAGE CASCODED FLOATING INVERTER AMPLIFIERS
where V OUT,CM , V IN,CM , C P and C OUT represent the output common-mode voltage change, input common-mode voltage change, the parasitic capacitance of the reservoir capacitor C RES and the output capacitance of the FIA, respectively. In the case of the cascaded structure, C OUT for the 1 st -stage FIA is usually small as it is only the gate capacitance of the input transistors in the 2 nd -stage. Therefore, as given by (1), V OUT,CM of the 1 st -stage FIA is non-negligible with a small C OUT in the denominator. Thus [11] chose to use a CMFB circuit to alleviate the impact. In this brief, this issue is mitigated by implementing C RES with a metal-insulator-metal (MIM) capacitor that consists of upper metal layers instead of a metal-oxide-metal (MOM) one. Since the MIM capacitor has much less parasitic capacitance C P than the MOM does, it can suppress the fluctuation of the output commonmode voltage even without using a dedicated compensation circuitry. In our design, to balance the parasitic capacitance at V DD and ground sides, the MIM capacitor for C RES is split into two and the connection of the one is flipped as shown in Fig. 1. Although the density of the MIM capacitor is lower than the MOM capacitor, C RES of the 1 st -stage FIA is 2 pF in our design, which does not occupy a large part of the overall ADC. To relax the design, the 2 nd -stage FIA also uses the same 2 pF C RES , although we may be able to further improve the stability by using a smaller C RES in the 2 nd stage as presented in [6] and [11].   Figure 3 shows with a blue solid line that the proposed two-stage cascoded FIA gain is about 17 dB higher than that of the conventional two-stage FIA and is also robust to the input-common mode voltage without using an extra circuit. Figure 4 summarizes the simulation results of the unity gain frequency (UGF), phase margin (PM), and DC gain of the proposed two-stage FIA over some PVT conditions. As presented in [6], in the dynamic amplifiers, its characteristic changes over time. In the following discussion, we will use the values at the end of the amplification phase, i.e., at 50 ns assuming 10 MHz operation in this brief. The UGF and PM are relatively stable over the PVT, and the PM is more than 30 • over the corner conditions. The DC gain drops in a fast process corner with a high supply voltage, which is mainly because the input transistors of the 2 nd -stage cascoded FIA tend to go into the triode region by the change of the input common-mode voltage under these conditions. This gain fluctuation can be mitigated by more careful transistor sizing or by using tunable bias voltages for the cascode transistors.
III. PROPOSED DISCRETE-TIME ADC USING TWO-STAGE CASCODED FIA Figure 5 shows a circuit block diagram of the proposed DT ADC. It is composed of a single-loop 2 nd -order singlebit architecture with the input feedforward path, which relaxes the linearity requirement of the amplifiers by suppressing the signal component at their inputs. Both of the two integrators are composed of the proposed closed-loop two-stage cascoded FIA. A chopping is applied only to the 1 st -stage integrator to exclude its 1/f noise contribution. V CM is set to a half of V DD . A simple StrongArm latch comparator is used for a 1-bit quantizer [12]. No calibration is applied to the proposed DT ADC. Figure 5 also shows a timing diagram of the proposed ADC. Before the conversion starts, the ADC is in its reset mode where C I1,2 , C F1−3 and C S2 are discharged and all FIAs are reset. While the ADC is working, the 1 st and the 2 nd integrators work alternately. Figure 6 shows a signal flow graph of the proposed DT ADC. With the cascoded structure, the output voltage swing of the FIA is limited. The scaling factors in the loop are properly tuned so that the output voltage of the cascoded FIA is confined within the proper range for sufficient gain, e.g., 300 mV∼700 mV. Signal transfer function (STF) and noise transfer function (NTF) are respectively given by where k is the equivalent gain of the 1-bit quantizer. Equivalent quantizer gain k is determined by the following equation [13], [14].
where v, y, and N represent the quantizer output, quantizer input, and the number of samples, respectively. This k depends on the modulator input. v and y are obtained by behavioral simulations using MATLAB. Input amplitude, frequency, and the number of samples are set to −6 dBFS, 2.01225 kHz, and 1048576, respectively, resulting in k = 10.1. With this k value, Fig. 7 depicts the STF and NTF versus the frequency normalized by the sampling frequency that exhibits almost flat STF up to the Nyquist frequency with the 2 nd -order noise shaping.
IV. MEASUREMENT RESULT The prototype of the proposed DT ADC is fabricated in TSMC 65 nm standard CMOS process. It occupies 190 μm×210 μm as shown in Fig. 8(a). To evaluate the prototype, a differential input and clock signals are applied from SRS DS360 and Tektronix AFG31252 function generators, respectively. The 1-bit output is captured by Digilent Digital Discovery logic analyzer then processed with a PC. The ADC  consumes 43.5 µW from a 1V supply at a 10 MHz sampling frequency. Figure 8(b) depicts a power breakdown of this ADC, where the analog and the digital parts consume 30.3 µW (70%) and 13.2 µW (30%), respectively. Figure 9 Fig. 9 shows the measured output spectrum of the ADC with  −0.4 dBFS input where the peak SNR of 88.9 dB is achieved at the OSR of 256. A red line in Fig. 9 shows the measured spectrum without the input source, which exhibits a lower noise floor without the power line noise. We expect from  this result that the noise contribution of the signal source used to evaluate the ADC is larger than that of the ADC itself. Supposing that the spectrum measured without the input source represents the inherent noise of the ADC, by taking the noise power from the red spectrum while taking the signal and distortion powers from the blue one, the true performance of the proposed ADC is calculated to be 88.5 dB SNDR and 89.2 dB SNR, which are translated to Schreier FoM of 175.0 dB and Walden FoM of 51.2 fJ/conv.-step. Figure 10 shows the measured SNDR versus the input amplitude. The ADC achieves 91.7 dB DR. Figures 11 and 12 respectively show the power consumption and SNDR/SNR versus the sampling frequency that demonstrate that the proposed DT ADC realizes a fully dynamic operation with the power scalable to the sampling frequency. Table I shows the performance summary and the comparison with recent fully dynamic oversampling ADCs. The proposed ADC achieves competitive performance with a highly simple and compact architecture without using complex calibrations.
V. CONCLUSION This brief presents a fully dynamic 2 nd -order DT ADC using closed-loop two-stage cascoded FIA. By implementing floating reservoir capacitors as MIM capacitors, the proposed two-stage cascoded FIA achieves high DC gain and robustness to the input common-mode voltage fluctuation without an additional CMFB circuit. The measurement results of the prototype fabricated in a 65 nm standard CMOS process prove that the proposed ADC realizes a fully dynamic operation and achieves competitive performance with a simple architecture without calibrations.