A Single-Stage, Capacitively-Coupled Instrumentation Amplifier With Complementary Transimpedance Boosting

Capacitively-Coupled Instrumentation Amplifiers (CCIAs) are widely used as AC-coupled, low-noise amplifiers in many multi-channel, area-intensive sensor interface applications. However, the need for a trade-off between the front-end gain and CCIA area, imposed by the input capacitance, restricts the miniaturization of such sensors. We propose a Complementary Transimpedance Boosting (CTB) technique to relieve this challenging gain versus area trade-off. The proposed CTB applies to both the DC and AC paths of a CCIA. CTB also reduces AC gain degradation, suppressing low-side gain peaking of the frequency response without significantly increasing input-referred noise. The Gain-Noise-Area Efficiency (GNA) and Gain-Power-Area Efficiency (GPA) factors are also introduced for holistic comparisons with other front-end amplifiers regarding noise, gain, and power consumption. CTB-based CCIAs (CTB-CCIA) are fabricated in <inline-formula> <tex-math notation="LaTeX">$0.18~\mu $ </tex-math></inline-formula>m CMOS, with the highest single-stage AC gain of 289 V/V achieved. Occupying only 0.011 mm2, a conventional CCIA with the same area will have <inline-formula> <tex-math notation="LaTeX">$14.4\times $ </tex-math></inline-formula> less gain while requiring at least two stages. The CTB-CCIA has a competitive NEF of 4.92 within a signal bandwidth of 0.21 Hz – 8.7 kHz, suitable for multi-channel applications.

However, CCIAs must be designed to have a large AC gain to satisfy the dynamic range of downstream digitization circuits, especially for weak input signals, and suppress the downstream circuit noise contribution.For example, Electroencephalogram (EEG) signal acquisition systems typically require a mid-band gain of at least 80 dB to digitize downstream properly.The AC gain of a CCIA is defined by the ratio of the input capacitor, C in, to feedback capacitance, C f b.Large C in of up to 40 pF is often used in CCIAs to obtain a high closed-loop front-end gain of up to 40 V/V (32 dB) [12], [13].Unfortunately, C in occupies a significant portion of the amplifier area (> 0.1 mm 2 ), severely limiting a further increase in channel count, subject to the silicon area budget.C in can be implemented using stacked MIM capacitors [13] with higher capacitance per unit area.However, it is not compatible with standard CMOS.A large C in also results in a lower input impedance, causing significant signal attenuation and distortion.Alternatively, a physically small value of C f b can be used.However, this method is constrained by the manufacturable precision of the intended process technology [14].Hence, the CCIA's AC gain implementation inevitably imposes an area -as determined by C in and C f b -versus gain tradeoff.The most commonly used practice to address this issue involves reducing the input gain to reduce the input capacitance and cascading additional amplifier stages to increase the overall gain [3].However, this leads to additional power consumption and an increased circuit area.
Therefore, for area minimization, it is desirable to have a single-stage CCIA realization with high gain, low silicon area, and power consumption; To do so, the inevitable gain and power versus C in trade-off first need to be addressed, in addition to having a low noise efficiency factor (NEF).We advance current work by proposing Complementary Transimpedance Boosting (CTB) technique to relieve the trade-off to realize high-gain single-stage CCIAs in a compact area.Our proposed CTB-based CCIAs (CTB-CCIA) achieve a gain (C in /C f b ) of up to 289 V/V while keeping a small C in of only 1.5 pF (with effective C f b = 5.2 fF), occupied 0.011 mm 2 and consuming only 1.1 µW.The CTB technique is also applied to the DC biasing path to increase the feedback DC resistance.On the other hand, the CTB technique helps implement highly compact CCIAs for a desired gain.CTB would also be a valuable technique to boost the gain of trans-impedance amplifiers without being limited by process technology.
Section II surveys the current methods to relieve the gain versus area trade-off.Section III describes the general concept of using circuit techniques to reduce C f b to relax the gain versus trade-off.The idea of CTB is then introduced.Section IV describes the design of the CTB-based CCIA circuit, and Section V presents the measurement results of the CTB-CCIA.

A. Amplifier Gain Versus Area Trade-off
As highlighted by earlier works, the area versus gain trade-off is a well-acknowledged issue and is summarised by the AC gain defined as C in /C f b .C in is usually large to maintain high AC gain, but this comes at the cost of a significant on-chip area.In addition to the two commonly used methods mentioned in Section I, there were other attempts to relieve or circumvent this tough trade-off.
The first such technique involves embedding a large capacitance (8-20 pF) below the signal electrode [15], [16], increasing the input capacitance, thereby increasing the gain.Fig. 2(a) shows that the electrode and capacitor are off-chip but reside on the same substrate.Therefore, there is no need to include any sizeable on-chip input capacitance for each CCIA, relieving the need to make the gain versus area tradeoff.This method is helpful for specific applications with an unused area near the signal electrode.However, compared to standard CMOS technology, the manufacturing process depicted in [15] and [16] cannot realize capacitors with high enough precision needed for well-matched inter-channel AC gains.In addition, additional processing steps are required to Fig. 2. Commonly used methods to resolve the gain vs area constraint: (a) Embedding the input capacitance under the sensor [15], (b) Using the gate capacitance as C fb [17], (c) Using a single CCIA for acquiring multiple inputs with time-division multiplexing [18], [19], and (d) Using T-capacitor in the feedback network [22].embed the capacitances with the electrodes, which is more costly than using on-chip capacitors.Therefore, this method is not entirely CMOS compatible and has not found widespread adoption.
On the other hand, [17] proposed using the OTA's input transistors' small parasitic gate-drain overlapping capacitance (< 38 fF) as the feedback capacitance, which in turn lowers the required input capacitance size with high gain.Figure 2 Sharing a single CCIA for all inputs using time-division multiplexing [18], [19] is another method to reduce the overall amplifier area (Fig. 2(c)).However, the time-multiplexing rate increases proportionally as input channels increase.Consequently, the single CCIA's required bandwidth, power consumption, and input-referred noise increase with the number of input channels, negating its area-saving advantage.Recently, Orthogonal Frequency Chopping (OFC) [20] and Orthogonal Code Chopping (OCC) [21] techniques were also proposed to reduce the total amplifier area for multi-channel sensors.Both methods involve multiplexing the input capacitors into a single CCIA either in the frequency or code domain.However, although both OFC and OCC relax the trade-off between the number of multiplexed channels versus CCIA's Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.
power consumption and noise increase, the input capacitors of each channel still dominate the total area and do not lead to a significant area reduction.
Introducing a T-capacitor network in the CCIA's feedback path, as shown in Fig. 2(d), is another technique to achieve high AC gain [22], [23], [24].For example, recent works that use T-capacitor feedback networks achieved AC gains of up to 35 dB (56 V/V) while only using C in of less than 7 pF [23], [24].However, this method wastes a part of the output signal to signal ground.Also, more shunt capacitors still need to be added to achieve higher AC gains, inevitably increasing the T-capacitor CCIA area.Therefore, this method still faces limitations in further relaxing the area versus gain trade-off.

B. Gain-Noise-Area Efficiency Metrics
Although relaxing the amplifier's gain-area trade-off is getting more attention, CCIAs must also satisfy other requirements, such as low power consumption and low input-referred noise.Hence, when comparing front-end amplifiers, one must often consider each CCIA's input-referred noise, power, gain, and area.Unfortunately, to date, no single metric allows us to take a holistic comparison of CCIAs, considering the area aspect as well.We also observed that state-of-the-art CCIAs are primarily implemented using analog circuit design techniques; therefore, their circuit area still does not scale proportionally with shrinking process technology, as shown in works from 180 nm [25] down to 22 nm [26].For example, the CCIAs that were implemented in 28 nm [14] and 22 nm [26] technology nodes still occupy > 0.018 mm 2 with a mid-band gain of less than 40 dB and have NEFs of up to 7.5.Although such process nodes benefit miniaturization of digital circuits, analog-based CCIAs in these process nodes still require area-intensive MIM/MOM capacitors and lowgate-leakage transistors, resulting in a minimal reduction in amplifier area as compared to those implemented in more mature technologies.
To address the need for holistic comparison of CCIAs in terms of input-referred noise, power, gain, and area, we introduce the Gain-Noise-Area Efficiency (GNA) factor, which effectively captures a signal amplifier's performance (Gain and Noise), area, and supply current trade-off.The GNA factor is not limited to characterizing just CCIAs; it can be used to compare other front-end amplifiers.The GNA is defined as: where NEF is the Noise efficiency factor [27] (the smaller, the better) and is defined as where V ir ms is the input-referred noise integrated over the CCIA's noise bandwidth, I total is the total CCIA supply current, V ther mal is the thermal voltage, κ is the Boltzmann's constant, T is the absolute temperature, and BW is the CCIA's signal bandwidth.The NEF has been an essential metric for comparing any amplifier's trade-off in supply consumption and noise without considering gain and area.The GNA factor expands on the NEF to include signal gain and onchip area, thus providing a broadened means for comparing signal amplifiers.Furthermore, the GNA is especially relevant for multi-channel applications (such as 100+ neural channel amplifiers).For example, an amplifier with a higher GNA would indicate that the amplifier has a low NEF and higher gain on a more compact on-chip area (we note the area of analog amplifiers, especially the capacitors, do not scale as much as the digital counterpart).Thus, the GNA factor would be a more holistic way to compare signal amplifiers.A recent work [28] has attempted to summarise this comparison by plotting Power/Bandwidth versus area and noise density versus area of recent works.However, it is not easy to visualize the trade-offs using two separate metrics compared to our proposed GNA factor.
Recent amplifier designs have also started to report the Power-efficiency factor (PEF) metric [29] in addition to the NEF.The PEF includes the supply voltage, V supply of the signal amplifiers in the comparison process.The PEF is defined as Therefore, we expand on the GNA factor defined in (1) by replacing the NEF with PEF to obtain the Gain-Power-Area Efficiency (GPA) factor as follows: The GPA helps compare amplifiers that also provide the PEF metric.

III. PROPOSED COMPLEMENTARY TRANSIMPEDANCE BOOSTING A. General CTB Circuit
The CCIA belongs to the closed-loop inverting gain amplifier family, as shown in Fig. 3.A general definition of the closed-loop gain of the inverting gain amplifier is defined as where Z in and Z f b are the input and feedback impedances, respectively.From ( 5), one can observe that high closed-loop gain is realized either by using a large feedback impedance (small C f b in Fig. 1) or a small input impedance (large C in in Fig. 1).Using a large C in to achieve a high closed-loop gain increases silicon area and reduces input impedance.
A large feedback impedance means that the output signal current flowing toward the virtual ground node of the OTA is highly diminished.This effect can be achieved by physically high impedance components or canceling a portion of the feedback signal current before it reaches the virtual ground mode.Both methods are indistinguishable from the circuit topology point of view; the latter leads to our proposed CTB method, as shown in Fig. 4. The complementary feedback signal currents are forced to partially cancel each other at an intermediate mixing node (n1 and n2) along the feedback path of the amplifier; through Z 2 and Z 3 .Therefore, the feedback signal currents flowing towards the virtual ground nodes, n3, and n4, are highly diminished.Hence, this cancellation effect boosts the feedback impedance (Z f beq ) and the closed-loop gain (Gain closed−loop ), as summarised by ( 6) and ( 5), respectively.
The feedback impedance boost is high when the values of Z 2 and Z 3 are close, leading to a decrease in the denominator term in (6), boosting Z f beq .The input-referred noise would inevitably increase due to the added parasitic capacitance of Z 3 and have to be suppressed; thus, Z 1 is added between the nodes n1(n2) and n3(n4) to suppress any increase in input-referred noise.This effect is explained in more detail in Section IV-C using capacitors.It also has the added benefit of further boosting the trans-impedance as described in (6).
In contrast to the conventional CCIA, the proposed CTB method only requires two additional feedback impedances.However, it would have a much higher closed-loop gain.Regardless of the closed-loop gain, it would also have a much higher input impedance.This method also repurposes fully differential OTA's (FDOTA) inherent balanced-complementary outputs to realize CTB.FDOTAs are commonly used to double amplifier output signal swings at low supply voltages imposed by modern technology nodes.CTB also complements the negative-resistance methods mentioned in [30].However, unlike [30], CTB applies only to the feedback path, not the input path.CTB is also helpful for implementing trans-impedance amplifiers [11] that require large trans-impedances in a compact area.

B. General Stability Analysis of CTB
The circuit of Fig. 4 involves both positive and negative feedback, and stability analysis needs to be done.Fig. 4 is a shunt-shunt feedback circuit, and its closed-loop transfer function is given by: where α is the open loop gain of the OTA, A 1, and is always a positive quantity, and β is the feedback factor given by For amplifier applications, Z f beq is always larger than Z in ; if Z 2 < Z 3 , there will be less positive than negative feedback.Hence, from ( 6) and ( 8), αβ will be positive, and the amplifier will be stable.If Z 2 = Z 3 , there will be an equal amount of negative and positive feedback.Hence, Z f beq = ∞, and the amplifier's closed-loop gain will equal A 1 's open-loop gain.However, this occurs only in the ideal case, and component mismatches may make Z 2 > Z 3, leading to αβ becoming negative, indicating more positive than negative feedback.The circuit in Fig. 4 then becomes an oscillator.
Expanding on the statements above, suppose a unit impedance, Z u represents Z 1 and Z 2 (i.e., Z 1 = Z 2 = Z u ), and Z 3 is a multiple of Z u such that Z 3 = ε Z u , then ( 6) and ( 7) can be rewritten in terms of ε respectively as The term (ε −1) quantifies the mismatch between the positive and negative feedback impedance paths (Z 2 and Z 3 , respectively).In (9), the multiplier term to Z u quantifies the boosting to the unit impedance, Z u, for a given mismatch (ε −1).If Z 2 < Z 3, then ε > 1, and αβ is positive.Therefore, the denominator in (7) characterizing the amplifier expresses negative feedback, and the amplifier is stable.Conversely, if Z 2 > Z 3 , then ε < 1, and αβ is negative.As a result, the denominator in (7) expresses positive feedback, and the amplifier is unstable.But if Z 3 = Z 2 , then ε = 1, and Z f beq = ∞; the closed loop gain described in (10) would converge to α.This means that the closed-loop amplifier gain is equal to the open-loop gain of the OTA when ε = 1.Lastly, if Z 3 is not present in the positive feedback path, then ε = +∞, and the impedance boosting factor has a minimal value of 2.
For a required stable impedance boosting to Z u or a desired closed-loop gain, one can use ( 9) and (10) to obtain the mismatch between Z u and Z 3 while ensuring in design that component mismatch variation keeps ε above unity.The last multiplier term in (10) can be approximated as unity if α ≫ Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.

IV. CTB-BASED INSTRUMENTATION AMPLIFIER DESIGN
A. CTB on the AC Path Fig. 5 shows the circuit diagram of a CTB-CCIA with CTB applied on the AC gain path.For the CTB-CCIA, the equivalent feedback capacitance, AC gain, AC feedback factor, and low-side cutoff frequency are respectively defined by where R p is the effective DC resistance of the DC bias path.PMOS transistors operating in weak inversion [12], [13] are typically used to implement R p as they have lower carrier mobility, resulting in a higher resistance per unit area than NMOS transistors.If αβ CCIA ≫ 1, the third multiplier term in (12) can be approximated to unity.One can notice that as the value of C 3 approaches that of C 2 , the effective feedback capacitance, C f beq decreases proportionally.Consequently, the closed-loop AC gain, Gain C T B−CC I A is boosted proportionally.From Section III-B, the maximum theoretical gain is equal to A 1 's open loop gain when the negative and positive feedback signal paths (Z 2 and Z 3 or C 2 and C 3, respectively) are precisely matched.But if process variations make C 3 > C 2 (i.e., Z 2 > Z 3 ), the open loop gain, αβ CCIA becomes negative, and the CTB-CCIA becomes an astable multivibrator with an oscillation frequency given by The same analysis in Section III-B is also performed for ( 11) and (12).Suppose a unit capacitance, C u , represents C 1 and C 2 , and C 3 is a multiple C u such that C 3 = ϒC u , then (11) and ( 12) can be rewritten in terms of ϒ as ) The term (1-ϒ) quantifies the mismatch between the positive and negative feedback path capacitances (C 2 and C 3 ).The first multiplier term in ( 16) describes a reduction factor to C u (trans-impedance boosting) for a given mismatch.The first two terms in (17) describe the AC gain boosting due to the same mismatch.If C 3 < C 2 , then ϒ < 1, and αβ CCIA becomes positive.Therefore, the CTB-CCIA characterized by the denominator in (7) operates in negative feedback, and the CTB-CCIA is stable.On the other hand, if C 3 > C 2 , then ϒ > 1 and αβ CCIA becomes negative.As a result, CTB-CCIA's feedback loop, characterized by the denominator in (7), becomes positive, and the CTB-CCIA becomes unstable.If C 3 = C 2 , then ϒ = 1, and Gain C T B−CC I A equals A 1 's open loop gain.Similarly, if there is no positive feedback path, then ϒ = 0 and the gain-boosting factor approaches a minimal value of 2.
For a desired gain boosting, one can use (17) to calculate the mismatch required between C 2 and C 3 while ensuring in design that capacitor mismatch variation maintains ϒ < 1.
Compared to the conventional CCIA and T-capacitor CCIA, the proposed CTB-CCIA, regardless of the target gain, does not require a large C in and only needs two additional small feedback capacitors, C 3, in the AC path.For example, for a single-stage gain of 862 V/V and using unit capacitors of 75 fF, C in , C 2, and C 3 would be 1.5 pF, 75 fF, and 69.8 fF, respectively.This is the largest (calculated) gain designed in this work, as C 3 is kept at 6.9 % smaller than C 2 to ensure C 3 < C 2 considering capacitor mismatch.TABLE I compares the capacitors required for achieving (calculated) 862V/V gain for three single-stage CCIAs topologies: Proposed CTB-CCIA, T-Capacitor-based CCIA [21], and Conventional CCIA.All three CCIAs used the same FDOTA and unit capacitors of 75 fF.However, the conventional CCIA and T-Capacitor-based CCIA [22] require 38× and 7× more unit capacitors (and area) than the proposed CTB-CCIA.Hence, our proposed CTB-CCIA occupies the smallest area and presents the lowest input capacitance load for the same AC gain compared to the other mentioned CCIAs.For silicon validation, in addition to this CTB-CCIA, we designed a series of CTB-CCIAs with different AC gains, and their measured AC gain is reported in TABLE II and Fig. 12(a) in Section V.
Fig. 6 shows the 200-run pre-layout Monte Carlo (mismatch and process variation) simulation of the Gain C T B−CC I A of  the same CTB-CCIA at 1 kHz.The mean value is 0.4 dB lower than the calculated gain due to input signal attenuation by the FDOTA's input gate capacitance.The 3σ mid-band gain variation is +/−1.2dB from the mean value, as only the widths of C 3 and C 2 are matched.
A 200-run Monte Carlo simulation was also run to check the transient response of the same CTB-CCIA to a 200 µV pp square wave at 100 Hz.Fig. 7 shows that the CTB-CCIA's output does not ring and is stable for all 200 runs despite using positive feedback to achieve CTB.

B. CTB on the DC Bias Path
As C f beq achieved using CTB is very small, it is also necessary to substantially increase the DC feedback resistance for applications that require low-side cutoff frequency < 0.5 Hz.Cascading pseudo-resistors in series or using T-resistor feedback topology cannot produce high enough DC resistance to match the ideal C f beq of 1.74 fF of CTB-CCIA.Hence, the proposed CTB technique is also implemented in the DC feedback path (CTB-DC), as shown in Fig. 8, to generate much higher DC resistance than conventional pseudo-resistors.Replacing impedance terms with resistances, (6) directly defines the effective DC feedback resistance of the CTB-DC path.Similar to the CTB-AC path, the resistance of the negative feedback path (M 5 -M 8 ) has to be less than  the positive feedback path (M 9 -M 12 ) to prevent an astable condition.
The CTB-DC biasing path further improves the CCIA in reduced AC gain degradation by the pseudo-resistor's parasitic capacitances and reduces low-side frequency gain peaking in the AC response.Both effects are described in more detail in the following paragraphs.
Fig. 9 shows the parasitic capacitances in a DC feedback path.Consider the case where the ideal switch S 1 is open; R 1 and R 2 form a DC bias path typical of most pseudo-resistorbased DC biasing [1], [2], [3].The parasitic capacitances C p1 , C p2 , and C p4 introduce an AC feedback path parallel to C f beq , reducing the AC gain of the CCIA from the designed value (C in / C f beq ).On the other hand, if S 1 is closed to realize CTB-DC bias, then C p1 , C p2 , C p4 , and C p3 also form a CTB-AC path.But, as described by (11), the effective capacitance would be significantly smaller than when S 1 is open, leading Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.to lesser AC-gain loss.This improvement is experimentally observed in Section V in Fig. 13 and Fig. 16.
Finally, considering only the presence of C p4 (to simplify the analysis) and when S 1 is open, the CCIA behaves as a second-order high-pass filter with a closed-loop gain transfer function described by and the Q-factor is For Q > 1/ √ 2, there would be increasing gain peaking on the low-side frequency response, as observed in [13], [22], [31], and [32].Therefore, to eliminate this gain peaking, it is essential to have In the case of R 1 = R 2 , C f b needs to be more than 1/2 C p4 to prevent gain peaking on the low-side frequency response.
Considering S1 is closed to realize CTB-DC biasing, the closed-loop gain transfer function is where The criteria to eliminate low-side gain peaking is therefore With CTB-DC biasing, (23) shows that the criteria for eliminating low-side gain peaking also depend on R 3 -R 2 .Hence, by keeping the values of R 3 and R 2 close, low-side gain peaking can also be eliminated instead of solely relying on reducing C p4 or the absolute value of resistors, R 1 -R 3 .For example, suppose we keep R 1 = R 2 and R 3 = 2R 2 ; then C f beq only needs to be more than C p4 /6.25 to prevent peaking on the low-side gain response.In other words, when using CTB-DC, a much smaller C f beq can be used (such as that obtained using CTB-AC) before gain peaking occurs on the low-side frequency response.This effect is experimentally observed in Fig. 16 of Section V.
C. Noise Analysis of the CTB-CCIA Fig. 10 shows the simplified noise equivalent circuit of the CTB-CCIA.The input-referred noise power density of the FDOTA is modeled as V 2 F D O T A ( f ), and the noise power density of the pseudo-resistor, R p is modeled by 4kTR p .The input referred noise power of the CTB-CCIA is obtained as where C 1 +C 2 +C 3 +C p4 .Gain CTB−CCIA and f L are defined earlier in (12) and (14).C p4 models the IC layout parasitic capacitances of C 1 -C 3 and their routing.C p5 models the FDOTA's input gate capacitance.
The first term in (24) describes the brown noise power density arising from the low pass behavior of C f beq and R p .The second factor in the second term of ( 24) is insignificant for frequencies above f L / Gain C T B_CC I A and can be ignored.
Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.
If C in ≫ C β , we observe from (24) that V 2 I R F ( f ), like all CCIA topologies, is primarily determined by C in , C p5 , and FDOTA's intrinsic noise [27].Therefore, as an advantage, even though C f beq is significantly reduced through CTB, the total input-referred noise does not increase significantly.Section V's measured noise PSD (Fig. 14) also validates this observation.
We also observe from ( 24) that the contribution of capacitors C 2 , C 3, and C p4 to the input-referred noise is significantly suppressed by the series connection to C 1 .If a wire replaces C 1 (i.e C 1 → ∞), (24) would be reduced to indicating a direct contribution of C 2 , C 3, and C p4 to the capacitive multiplication of V 2 F D O T A (f), which leads to increased input referred noise level for the CCIA.D. Circuit Design of the OTA Fig. 11(a) shows the fully-differential, self-biased cascode OTA circuit used as the FDOTA for the CTB-CCIA.Initially proposed in [33], we have integrated cascode transistors (M2a, M2b, M3a, and M3b) to obtain a higher open loop gain.The circuit shown in Fig. 11(b) generates the cascode bias voltages: VPCAS and VNCAS for the FDOTA.The cascode bias voltages can be shared amongst multiple FDOTAs.
This FDOTA incorporates bias current reuse, where both PMOS FETs (M1a, M1b) and NMOS FETs (M4a, M4b) contribute to total input transconductance for the same bias current.In addition, the W/L ratio of the input differential pairs (M1a, M1b) and (M4a, M4b) are sized to work in weak inversion (g m /I D > 20).Both applied techniques help achieve low input-referred noise per unit supply current.Spectre TM circuit simulation shows that the FDOTA has an open-loop gain of > 84.5 dB at low frequencies and a gain-bandwidth product of > 20 MHz across process, supply voltage (1.2 V +/−10 %) and temperature (−20 o C to 85 o C) (PVT) corners.
All the transistors are sized to ensure they are in the correct operating region for the stated PVT corners.

V. MEASUREMENT RESULTS
A group of CTB-CCIAs with different gain designs are fabricated in a standard 0.18 µm 1P6M CMOS test chip using standard MIM (single-stack, 2 fF/um 2 ) capacitors as the unit capacitors.All CTB-CCIAs are powered at 1.2V.For each CTB-CCIA, we only used 46 unit capacitors of C u = 75 fF.We also kept C in = 1.5 pF, C 1 = C 2 = C u and used the same FDOTA, regardless of the required AC gain.The AC gain is changed by varying the length of C 3 from that of C u while keeping its width the same as C u .TABLE II summarises the average measured AC gains (over ten samples and with CTB-DC bias) of each CTB-CCIA.Fig. 12(a)(top) shows the microphotograph of the CTB-CCIAs with different AC gain designs.Fig. 12(a) (bottom) shows the microphotograph of two conventional CCIAs (Fig. 1) on the same die.CTB-CCIA4 has the highest measured single-stage gain.For CTB-CCIA4, we designed C 3 (69.8fF) to be 6.9 % lesser than C 2 to ensure C 2 > C 3 considering process variation.Each fabricated CCIA's measured AC gain is lower than the designed gain due to signal attenuation by parasitic capacitors from the layout.For example, CTB-CCIA4's expected gain is 862 V/V, but its measured gain is 289 V/V.Even though CTB-CCIA4's measured AC gain is lower than the designed gain, to the authors' knowledge, this is still the highest single-stage gain amplifier implemented on-chip reported to date.Fig. 12(b) shows the layout of CTB-CCIA4, which has the highest measured AC gain; it only occupies 0.011 mm 2 , which is only 24 % of the on-chip conventional CCIA shown in Fig. 12(a) (bottom), yet has a 72 % higher gain.A conventional Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.CCIA occupying the same compact area and input-referred noise would have at least 14.4 times lesser gain than our implementation, require a second gain stage, and consume additional power to achieve a total gain > 200 V/V.Fig. 13 shows the measured AC frequency response for 10 samples of CTB-CCIA4.Both responses with the CTB-DC biasing and conventional DC bias (a series connection of 2 pseudo-resistors) are included.In addition, the AC response of a simulated conventional CCIA (C in = 1.5 pF, ideal C f b = 75 fF) is also included.We observed +0.8 dB/−0.6 dB of  The PSD of a conventional CCIA simulated using the FD-OTA (A1) with ideal fb = fF, and C in = 1.5 pF is also mid-band gain variation as we only matched the widths of C 2 and C 3 , while the length of C 3 was drawn for a target value of 69.8 fF.As a result, an average mid-band gain of 49.2 dB (289 V/V) was achieved.Interestingly, the average AC gain increases by 3.5 dB when the CTB-DC biasing is used.This indicates CTB-DC tunes out the gain-depleting parasitic capacitances within the pseudo-resistors, as explained in Section IV-B.Also explained in Section IV-B, we also observed that with CTB-DC, the CTB-CCIA's AC response has a reduced gain peaking on the low side frequency response as compared to conventional pseudo-resistor biasing.From the frequency response and using (12), CTB-CCIA4 has an average C f beq of 5.2 fF.It is 7.6 times less than the state-ofthe-art [17].
Fig. 14 shows the input-referred noise PSD of CTB-CCIA4 with and without CTB-DC biasing.The measured noise floor is comparable to the same but ideal conventional pseudo-resistor-biased CCIA, confirming that CTB does not significantly increase the CCIA's input-referred noise as described in (24).However, the 1/f 2 noise between ideal and measured CCIAs at low frequencies differs due to differ-  ences in simulated and actual feedback DC resistances and AC gain, as explained in [22].In addition, the low supply current of 0.9 µA of our FDOTA limits the input-referred noise floor of the CTB-CCIA, which can be lowered by increasing the bias current.We also note that adding chopper stabilization or dynamic matching techniques can suppress the low-frequency noise.However, it is not the primary intention of the current work.Integrating over the signal bandwidth of 0.21 Hz-8.7 kHz, CTB-CCIA4 has an input-referred noise of 12.7 µV rms , NEF, and PEF of 4.92 and 29, respectively.Fig. 15 shows the step response of the CTB-CCIA4 to an input 100 Hz square wave signal with an amplitude of 200 µV pp .This step signal input was obtained by sending a 100 mV pp square wave from a function generator through a 500× resistor divider.Similar to the simulation shown in Fig. 7, the CTB-CCIA's step response does not exhibit any ringing, indicating that it stable despite using positive feedback to achieve CTB.
While measuring multiple samples, we observed that the quiescent DC level of the common-mode outputs is higher than the designed value of 0.6 V by 80 mV to 90 mV.In addition, there are also DC offsets of +/−11 mV between the differential outputs of the FDOTA.An example of these offsets can be observed from the step responses shown in Fig. 15.Both the output offsets (common-mode and differential) restricted the CTB-CCIA's output swing to a maximum of 120 mV pp at 1 % THD and degraded the CMRR and dynamic range.This is consistent for both the conventional and CTB-DC bias for each CTB-OTA.
To better demonstrate the proposed CTB-DC biasing performance, we designed and measured the frequency response of another CTB-CCIA (with measured 40 dB AC gain) with a configurable DC bias circuit.Shown in Fig. 12(a) as CTB-CCIA5, this CTB-CCIA can be configured with three different DC bias circuits at any one time on the same CCIA core: the proposed CTB-DC bias, conventional T-resistor-network DC bias, and conventional seriallyconnected pseudo-resistors.Each pseudo-resistor is voltagetunable and set to the same tuning voltage for each DC bias configuration.As the configurable DC bias circuit has more parasitic capacitances that degrade the high AC gain of CTB-CCIA4, it was only integrated into CTB-CCIA5, solely for pseudo resistor performance comparison.Fig. 16 shows that the proposed CTB-DC bias lowers the high-pass corner frequency by 6× and 17× compared to the conventional T-resistor DC bias and the conventional serially connected pseudo-resistors implementation.Also, as described in Section IV-B, applying CTB-DC suppresses the low-side frequency response peaking and increases the AC gain.
Furthermore, since the measured AC gain is 40 dB and C in = 1.5 pF, the effective C f b is 15 fF.Therefore, the proposed CTB-DC biasing has an equivalent DC resistance of 707 T and is more than 6× higher resistance for the same area occupied by conventional DC biasing methods.It is also 7× higher than the state-of-the-art DC biasing method [10].
TABLE III summarizes the measured performance of our proposed CTB-CCIA4 and compares it with state-of-the-art single-stage CCIAs that are realized in a wide range of CMOS processes.Compared to state-of-the-art, the proposed CTB-CCIA4, despite using a more matured CMOS process (180 nm), is the only work to achieve >200 V/V in a single stage within a compact area of 0.011 mm 2 .
Although the CCIA in [35] is as compact as our CTB-CCIAs, it only achieved an AC gain of 38.5 dB despite using C in = 6 pF and high-density MIM capacitors (4 fF/um 2 ) that are not part of a standard CMOS process.Similarly, [13] uses high-density MIM capacitors and C in = 25 pF to achieve a high AC gain of 46 dB but utilizes 3 times the area of CTB-CCIA4.In contrast, we only used standard MIM capacitors (2 fF/um 2 ) and C in = 1.5 pF.In addition, the CCIA in [35] uses positive feedback only to boost its input impedance in contrast to increasing the AC gain as in our implementation.
The CTB-CCIA's low CMRR performance can be attributed to the placement of the FDOTA's cascode transistors (M2a, M2b, M3a, and M3b in Fig. 11(a)) in a layout that lacks common-centroid orientation.This leads to an increase in channel length modulation and gain mismatch between the FDOTA's transconductance paths (M1a, M1b, M4a, and M4b in Fig. 11(a)), resulting in a degradation of the overall CTB-CCIA CMRR performance.
Our CTB-CCIA's dynamic range is not as high as the current state-of-the-art due to the absence of noise reduction techniques to suppress flicker noise.Additionally, the topology of our FDOTA inherently lacks a high output swing and is further limited by output DC offsets, as previously mentioned.
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TABLE III PERFORMANCE COMPARISON WITH STATE-OF-THE-ART SINGLE-STAGE AMPLIFIERS
Most state-of-the-art targets low but are limited by the gain versus area trade-off.This work emphasizes compact, high-gain CCIAs with reasonable NEF/PEF.Hence, Table III's GNA and GPA factors in comparing CCIAs implemented across different CMOS technologies.For example, even though the CCIAs in recent works [14], [26], [36] are realized on sub-100 nm CMOS processes, their GNA and GPA are still lower than those implemented with >100 nm CMOS processes.Also, even though CTB-CCIA4 is implemented in a standard 180 nm CMOS process, it achieved higher GNA and GPA than the state-of-the-art.
Like CCIA implementations in [24], [35], and [26], our CTB-CCIA's output stage is unable to provide a high current drive.Therefore, an amplifier with sufficient current drive is still required after the CCIA to drive downstream digitizing circuits.However, for CTB-CCIA, only a unity-gain driver would be required (resulting in lower power consumption) since the CTB-CCIA can handle all signal amplification.

VI. CONCLUSION
This work reports the CTB technique to realize compact, single-stage CCIAs with high gain.CTB performs complementary cancellation of the feedback signals from an FDOTA.As a result, the effective feedback impedance and closed-loop gain are boosted with minimal area and power consumption.Circuit analysis of the CTB technique and circuit simulations were presented to show that CCIAs using this technique are more compact yet stable and have low noise performance.Fabricated in 180 nm CMOS, prototype CTB-based CCIAs have achieved an effective feedback capacitance as low as 5.2 fF and DC bias resistance as high as 707 T .One of the CTB-CCIA also has the highest single-stage gain of 289 V/V to date while occupying only 0.011 mm 2 and consuming 1.1 µW; a conventional CCIA with the same area will have 14.4× less gain while requiring two stages.Despite using a more matured CMOS process, the proposed CTB-CCIA is the first on-chip, single-stage CCIA to break the 200 V/V limit with a high GNA of 5340 mm −2 and GPA of 906 mm −2 compared to the state-of-the-art using finer CMOS processes.Analysis and measurements have also shown that CTB-DC biasing improves AC gain and suppresses gain peaking on the low-side gain-frequency response in CCIAs.
(b) illustrates that this method achieved a high C in /C f b gain of up to 40 V/V (32 dB) with only C in = 1.5 pF.However, this requires a non-cascoded amplifier input stage, leading to low open-loop gain (< 60 dB).Low open-loop gain reduces the accuracy of the closed-loop gain and constrains any further increase in the closed-loop gain.

Fig. 4 .
Fig. 4. Proposed concept of CTB on the feedback path.

Fig. 5 .
Fig.5.The schematic of proposed CTB-CCIA with CTB applied to the AC gain path.Back-to-back diode strings on nodes n1 and n2 are used for antenna effect mitigation.

Fig. 8 .
Fig. 8.The schematic of proposed CTB-CCIA with CTB applied to both the AC gain and DC bias paths.

Fig. 11 .
Fig. 11.(a) Circuit schematic of the FDOTA.(b) Circuit schematic of the cascode voltage generator.Transistor sizes in micrometers (W/L) are also provided.

Fig. 12 .
Fig. 12.(a) Chip microphotograph of a group CTB-CCIAs (Top) along with the conventional CCIAs (Bottom) on the same die.(b) Closed-up view of chip microphotograph of the proposed CTB-CCIA4 with 289V/V mid-band gain at 1 kHz.

Fig. 13 .
Fig. 13.Measured AC response of 10 samples of the proposed CTB-CCIA4.Shaded areas indicate variability amongst samples.

Fig. 14 .
Fig. 14.Measured results noise PSD of the proposed CTB-CCIA4 with and without CTB-DC biasing.The PSD of a conventional CCIA simulated using the FD-OTA (A1) with ideal fb = fF, and C in = 1.5 pF is also

Fig. 15 .
Fig. 15.Step response of CTB-CCIA4 to a 200 µV pp square wave.High resolution acquisition is enabled to check for any ringing at the outputs.

Fig. 16 .
Fig. 16.Measured high-pass corner and the AC responses of the same exact CCIA core (gain = 40 dB) using the proposed CTB-DC bias vs. Conventional DC bias (T-resistor and basic pseudo-resistor).

TABLE I COMPARISION
OF FULLY DIFFERENTIAL, SINGLE STAGE CCIA TOPOLOGIES TO ACHIEVE AC GAIN OF 862 V/V (CALCULATED)

TABLE II LIST
OF FABRICATED CTB-CCIAS, AND MEASURED GAIN