Ultra-Low-Power Sub-1 V 29 ppm/°C Voltage Reference and Shared-Resistive Current Reference

This paper presents a curvature-compensated sub-1V voltage reference (VR) and a shared-resistive nanoampere current reference (CR) in a 130nm CMOS process. The CR is used to generate a bipolar junction transistor complementary-to-absolute-temperature voltage, which is summed up with a proportional-to-absolute-temperature voltage generated using a summing network of PMOS gate-coupled pairs. The measured output voltage and current references from 10 chips (<inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {REF}}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$I_{\mathrm {REF}}$ </tex-math></inline-formula>) at room temperature are 469mV and 1.86nA, respectively. The measured average temperature coefficient of <inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {REF}}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$I_{\mathrm {REF}}$ </tex-math></inline-formula> are 29ppm<inline-formula> <tex-math notation="LaTeX">$/^{\circ} \text{C}$ </tex-math></inline-formula> and 822ppm<inline-formula> <tex-math notation="LaTeX">$/^{\circ} \text{C}$ </tex-math></inline-formula> over a temperature range from <inline-formula> <tex-math notation="LaTeX">$- 40^{\circ} \text{C}$ </tex-math></inline-formula> to <inline-formula> <tex-math notation="LaTeX">$120^{\circ} \text{C}$ </tex-math></inline-formula>. The minimum supply voltage of the voltage-current reference is 0.95V, and the total power consumption is 30nW.


I. INTRODUCTION
U LTRA-LOW-POWER solutions are required in order to sustain the ever-increasing demand for wireless sensor nodes. The vast network of battery-operated low-power wireless sensor nodes is constrained by the battery usage [1], [2], [3]. The battery usage can be reduced by a radiofrequency (RF) powered wake-up receiver (WuRx). It ensures that the wireless sensor node stays in a deep-sleep state unless activated by a wake-up signal [4], thus increasing the lifetime of the battery. Fig. 1 shows the architecture of an RF-powered WuRx. The analog frontend of the WuRx consists of an RF-DC converter, which harvests the incoming RF energy to DC energy [5]. The signal processing system includes an envelope  detector, a comparator, an oscillator, and a digital processor, which operate in a low-voltage domain to reduce the power consumption. The power management system consists of a voltage reference (VR), a current reference (CR), a poweron reset (POR), and a low-dropout regulator (LDO) [4]. The strict performance requirements of the signal processing system in a WuRx demand an accurate low-power temperaturecompensated voltage-current reference (VCR) with a low supply voltage startup [6], [7]. The nanowatt power budget adds to the challenge of designing a robust and accurate VCR. This work presents an ultra-low-power VCR shown in Fig. 2, which is an integral part of a WuRx. This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ A classical approach to achieving a temperature-compe nsated VR is by combining a proportional-to-absolutetemperature (PTAT) voltage and complementary-to-absolutetemperature (CTAT) voltage circuits [8], [9], [10]. VR circuits can be broadly categorized into bandgap-based references, CMOS-based references, and hybrid references, which combine bandgap-based and CMOS-based reference circuits. The bandgap reference (BGR) is a conventional VR with a highly accurate reference voltage and low process corner and temperature variation [11]. Sub-BGR designs have achieved a sub-1V VR for a low power consumption and a considerable accuracy [11], [12], [13]. The BGR-based VRs have a minimum supply voltage of roughly 0.9 V owing to the forward bias voltage of a bipolar junction transistor (BJT) [14].
Recently, sub-threshold CMOS-based VRs have received much attention because of their low supply voltage operation and ultra-low-power consumption [10], [14], [15], [16], [17]. The ultra-low-power CMOS-based VRs employ native MOS devices where the leakage current determines the output voltage V REF . The dependence on the threshold voltage V TH of a MOS transistor in this topology results in an inevitable sensitivity to process corner variations [15], [16], [17]. Therefore, BGR-based designs are still the first choice to generate high-precision VRs for energy harvesting systems.
This paper introduces a novel curvature-compensated sub-1V VR and a shared-resistive nanoampere CR with an overall power consumption of 30 nW. The proposed VCR shown in Fig. 2  This paper is an extended version of [8], with an improved VCR which works for a wider temperature range from −40 • C to 120 • C and a higher supply voltage range from 0.95 V to 3.6 V. The extended paper addresses the curvature compensation of V REF for the wide temperature range using design parameters. The paper additionally includes a trimming circuit built to optimize the TC of the VR and minimize the spread of the CR, analysis of the supply voltage fluctuations, overall power consumption, chip-measurement results, and a comparison with the latest published results. The paper is organized as follows: Section II describes the operation principle and the design of the CR. Section III describes the design procedure of the curvature-compensated VR. Section IV presents the measurement results and the comparison with the state of the art. Section V concludes the work.

II. SHARED-RESISTIVE CURRENT REFERENCE
The proposed VCR has been designed in an in-house modified 130 nm CMOS technology. The initial design, however, was done in a primitive n-well 130 nm CMOS process where the NMOS transistors have no possibility of a buried p-well. For the sake of backward compatibility, most of the NMOS transistors in the VCR design have a bulk connection to ground.
The low-voltage CR is built for an RF-powered WuRx with strict requirements for low power consumption and a reliable startup [2]. The CR exploits an improved version of a beta-multiplier current reference by combining PTAT and CTAT currents to generate a temperature-compensated reference current. Specific contribution of this CR is the design of a shared-resistive design which generates an additional sub-50 mV voltage reference V SUB . The transistors are biased to operate in the sub-threshold region to ensure the low-power operation. The drain-source current I DS in the sub-threshold region [28] and the drain-source resistance R DS in the sub-threshold region can be written as: where W/L is the transistor aspect ratio, μ n is the mobility, C OX is the oxide capacitance, n is the sub-threshold slope, V T is the thermal voltage, V GS is the gate-source voltage, V TH is the threshold voltage, and V DS is the drain-source voltage of the transistor. The dependence of R DS on I DS in (2) highlights the high-nonlinearity of a MOS transistor operating in the sub-threshold region. A conventional temperature-compensated nanoampere CR combines a PTAT current β-multiplier circuit [28], [29] (see Fig. 3a, Fig. 3b) and a V GS /R circuit [30] to generate a CTAT current I CTAT (see Fig. 3c). The area-effective resistorless β-multiplier in Fig. 3a is widely used in microampere CRs, where the MOS transistor is biased in the linear region. However, the deployment of the MOS transistor in the sub-threshold region as a resistor brings a non-linear temperature dependence (see (2)). Unlike [30], the proposed CTAT circuit in Fig. 3c uses the PTAT current (see Fig. 4b) as a bias current for the transistor MN 2 . The temperature dependence is highlighted in the schematic simulation results in Fig. 3d, which show the generated current I PTAT versus temperature for the resistorless β-multiplier and the standard β-multiplier. The standard β-multiplier requires a poly-resistor which occupies a significant area for a nanoampere I PTAT generation. The generated current I CTAT in the V GS /R circuit is plotted alongside in Fig. 3d.
The proposed CR is based on a combination of the I PTAT generator in Fig. 3b and the I CTAT generator in Fig. 3c. The temperature compensation of the CR is done by the mutual compensation of the temperature dependence of I PTAT (∂ I PTAT /∂ T ) and I CTAT (∂ I CTAT /∂ T ). The PTAT current generator in Fig. 3b has equal currents flowing through the transistors MN 0 and MN 1 . As a result, one can write the following expression connecting MN 0 and MN 1 [18]: where V TH is the difference between the threshold voltages of MN 0 and MN 1 arising because of the body effect, and k is the transistor multiplier ratio between the transistors MN 1 and MN 0 . V TH can be expressed as [31]: where γ is the body bias coefficient, φ S is the surface potential, and V S1 is the source voltage of MN 1 . The resistor R 4 connected between V S1 and V SS generates a PTAT current I PTAT . I PTAT , derived from (3) and (4), and it's first-order temperature coefficient ∂ I PTAT /∂ T can be simplified and expressed as: I CTAT flows through R 5 across the voltage V G . The CTAT current I CTAT and it's first-order temperature coefficient ∂ I CTAT /∂ T are [30]: A poly-resistor is chosen instead of a diffusion resistor due to its higher sheet resistance. The p+ poly-resistor R 4 in the design has a typical PTAT behavior of less than 500 ppm/ • C [31]. As a result, the dominant terms in (6) and (8) are the first terms ∂T can be written from (1) as: where K1 = W L μ n C OX (n − 1), and I PTAT2 is the drain-source current of MN 2 . Combining (8) and (9), ∂ I CTAT /∂ T can be rewritten as: Depending on the substrate doping level and the oxide thickness of a transistor, ∂ V TH /∂ T is between −3 mV/ • C and −0.5 mV/ • C [32], resulting in a strong CTAT behavior of the first term 1 (10). The third and fourth terms of ∂ I CTAT /∂ T in (10) contribute to a small PTAT behavior. The second term −I CTAT (10) has a CTAT behavior that reduces with increasing temperature due to the dependence on the term I CTAT . This causes a mild slope reduction of the I CTAT curve at higher temperatures as seen in Fig. 3d. Overall, I PTAT and I CTAT temperature curves have a strong linear behavior (see Fig. 3d). This is attributed to the dominant first-order temperature coefficients in (10). The proposed CR is designed by combining the PTAT and CTAT sub-circuits and matching the dominant first-order temperature coefficients. The reference current I REF is generated by combining a fraction of the reference current I PTAT and I CTAT , and mutually compensating ∂ I PTAT /∂ T and ∂ I CTAT /∂ T . The fractional summing of the currents is achieved using a current mirror ratio of 4 (see Fig. 4).The overall temperature dependence of (6) and (10) depends on technology parameters such as V TH , the sub-threshold slope factor n, the poly-resistors R 4 and R 5 , and the drain-source current of MN 2 (I PTAT ). The most significant contributing factor of ∂ I CTAT ∂T is 1 . For the given design, the first-order temperature compensation of I REF requires a ratio R 5 /R 4 = 2.75. I PTAT is adjusted to fine-tune the overall temperature dependence of I REF . For a poly-resistor width of 300 nm, this implementation would require a large 0.02 mm 2 area for R 5 /R 4 = 39 M/13 M to generate a 2 nA [33]. A 0.02 mm 2 resistive area has an associated bottom-plate parasitic capacitance with respect to the substrate in the order of 60 aF/μm 2 * 0.02 mm 2 = 1 pF [34]. The CR is designed for an RF-powered WuRx whose harvested output voltage has fast transients at high input RF power levels (V DD /t = 10 5 V/s) [2]. This fast transient at V DD causes a false startup wherein the bias current is determined by the low-impedance path of the parasitic bottom-plate capacitance of the poly-resistor. Hence, it is critical to minimize the overall resistive area and its associated parasitic capacitance.
The proposed CR in Fig. 4 addresses the limitation of the large resistive area by combining I PTAT and I CTAT across a shared resistor R 3 . The shared-resistive path for the currents also generates a first-order temperature-compensated voltage drop V SUB = (I PTAT + I CTAT )R 3 . Equations (3) and (7) can be rewritten for Fig. 4 as: By maintaining the same resistor ratio, the resistors in Fig. 4 are now R 2 /R 1 = 11 M/4 M. The improved design in Fig. 4 compared to the combined circuits in Fig. 3b and Fig. 3c helps achieve a 0.012 mm 2 area with a 60% reduction of the overall resistive-network area for a similar performance. Furthermore, the CTAT current V GS /R circuit is dependent on the absolute value of V TH of MN 2 in Fig. 4. The 4-bit digital trimming circuit shown in Fig. 4 helps compensate for the variation of V TH (MN 2 ) and poly-resistors across process corners by shunting the bank resistors. The single trimresistors' exact value was found during the design optimization process in the Cadence Virtuoso environment. The CR is designed for a supply voltage range from 1 V to 4 V. Cascode transistors in the current mirrors help to increase the output resistance and reduce the channel length modulation effect of the current mirror transistors. It helps to increase the line sensitivity of the CR against supply voltage variations at the cost of an increased voltage headroom for the cascode transistors.
The beta-multiplier PTAT circuit is self-biasing and has two stable operating points: the desired one and the unwanted one, where no current flows [29]. The implementation of the required startup circuit is shown in Fig. 4. The medium-volt thicker gate-oxide transistor N 2 with a V TH > 0.6 V has been used in the startup circuit. It turns on as soon as there is sufficient gate-source voltage, resulting in the gate node of MP 6 being pulled down to start the flow of current through the CR. This turns on the transistor MN 3 , which eventually pulls down the gate node of N 2 towards the ground V SS . The medium-volt startup transistor N 2 is dimensioned such that the worst-case leakage current during the off state is in pA range. The low leakage current helps to ensure that the startup circuit is completely turned off once the CR is operational.

A. Simulation Results
The output current I REF = (I PTAT +I CTAT )/4 was set to 2 nA at 27 • C.   3σ variation of +/-20%. The output V SUB with a μ of 40 mV and σ of 2.7 mV has a good mean-TC of 468 ppm/ • C, as seen in Fig. 6. The reference voltage V SUB is used as a reference input for the relaxation oscillator in the RF-powered WuRx in Fig. 1.

III. SUB-1 V VOLTAGE REFERENCE
The RF-powered WuRx in Fig. 1 requires a sub-1 V VR which is critical for the analog/mixed-signal circuits operating in a 0.5 V low-voltage domain. The proposed curvature-compensated sub-1 V VR generates an output V REF by summing a CTAT voltage V CTAT and a PTAT voltage V PTAT , as shown in Fig. 7. The 2 nA reference current I REF , presented in Sec. II is used for the generation of V CTAT and V PTAT . This VR mainly targets on optimizing the TC by proposing a second-order effect analysis of V CTAT and V PTAT . Specific contributions of this work are: 1) Design of a VR whose temperature compensation is predominantly dependent on design parameters, which helps to easily port the VR design to other CMOS technology nodes; 2) A low power sub-threshold design approach wherein the PTAT generator cells [36] are connected in a unique current and voltage summing series formation; 3) The VR design has a very high robustness against fluctuations in the bias current and process corner variations. The temperature compensation of V REF is done by the mutual compensation of the first-order temperature dependence terms (∂ V CTAT /∂ T , ∂ V PTAT /∂ T ) and the second-order temperature dependence terms ( The CTAT voltage V CTAT = V BE /3 is generated by the base-emitter voltage V BE of the vertical PNP-transistor Q 1 , connected to a triple-well NMOS-diode voltage divider [11]. The output V BE /3 of the voltage divider is connected to a unity gain buffer to avoid loading the node. The current consumption of the unity gain buffer is 2 nA. A 100 fF capacitor C C improves the stability of the unity gain buffer. The CTAT voltage V CTAT , it's first-order temperature dependence term ∂ V CTAT /∂ T , and it's second-order temperature dependence term ∂ 2 V CTAT /∂ T 2 can be modeled as [35]: where E is a technology constant parameter, α = 4 − n, V BGR = 1.205 is the bandgap voltage of silicon at 0 K, and I C is the temperature-compensated BJT collector current. Assuming a typical V BE = 600 mV, α = 3.2, and T = 300 K, (14) can be approximated as: ∂ V CTAT /∂ T as shown in (14) and (16) has a typical-negative value, and it depends on the technology parameters α and V BE . ∂ V CTAT /∂ T can be modified by adjusting the current I C dependent term V BE (see (1)). The second-order term ∂ 2 V CTAT /∂ T 2 ≈ −4 μV/K 2 depends on the absolute value of V BE (see (15) and (16)). The compensation of both first-order and second-order temperature dependences of V CTAT is achieved using a PTAT voltage reference V PTAT . The PTAT voltage in conventional BGR-based circuits is generated using bipolar PNP transistors and resistors [31]. However, the nanoampere power budget of the VR requires the usage of large resistors. As an alternative, gate-coupled PTAT generator cells [36] are used in a series connection formation to achieve a low-power V PTAT . The PTAT cells include unit-cell transistors with multiplier ratio m. Every gate-coupled PTAT cell in Fig. 7 generates a drain-tosource voltage V DS,i across transistor N i (i = 1, 2, 3, 4, 5, 6). The output voltage V DS,i for the PTAT cell (N i , N ii ) can be modeled as: where K A,i is the ratio of the aspect ratio of the transistors N ii and N i , K I,i is the drain-current ratio between the transistors N ii and N i , and φ f is the Fermi-potential (φ f ∘ T ). The aspect ratio K A and the drain-current ratio K I are the design parameters that define the voltage drop V DS across the PTAT cell. The PTAT cell 6 in Fig. 7 has a high K I,6 = 5.5 and K A,6 = 3. The voltage drop in PTAT cell 6 is large enough to ignore the channel-length modulation term 1/(1 − e −V DS V T ) in (17). The channel-length modulation term cannot be ignored for the PTAT cell 1 where K I,1 = 1 and K A,1 = 1 (see Fig. 7). The first-order temperature dependence (∂ V DS /∂ T ) and the second-order temperature dependence (∂ 2 V DS /∂ T 2 ) of the individual PTAT cell can be derived from (17): The PTAT cell has a first-order positive temperature dependence as seen in (18). Iterative design of tunable design parameters K I and K A helps to adjust ∂ V PTAT /∂ T and compensate ∂ V CTAT /∂ T . An additional positive second-order temperature dependence of ∂ 2 V DS,i ∂ T 2 arises from the channel-length modulation term (1 − e −V DS V T ) as seen in (17) and (19). The series connected PTAT cell design differs from the parallel connection topology of the PTAT cells in [11]. The series connection helps reuse the drain current in the PTAT cells and achieve a high K I factor.
The total V PTAT generated from summing up the six cells and V REF can thus be written as: The first-order temperature compensation of V REF = V PTAT +V CTAT requires the compensation of ∂ V PTAT /∂ T and ∂ V CTAT /∂ T . As shown in (16), the target for ∂ V PTAT /∂ T is 0.75 mV/K. Equation (18) shows that ∂ V PTAT /∂ T = 6 i=1 n V T ln (K A * K I )/T ≈ 0.1 mV/K * ln (K A * K I ). The equation highlights the need to design a PTAT component that has a high K A and K I . Choosing a high K A is the easier design option, but it results in an extremely low pA bias current through the unit transistor in the PTAT unit cell. Low bias currents are an issue in fast corners as well as high temperatures where the leakage current is also in pA range. On the other hand, a high K I factor is beneficial to increase the ∂ V PTAT /∂ T term and match ∂ V CTAT /∂ T . As a trade-off between overall power consumption and minimum current through the unit-transistor cells in cell 1, the VR is designed with a series 6-stage PTAT cell formation to provide a high current-gain K I and a realistic value of K A . An iterative design optimization of K I , K A , and the current mirror ratios are done to achieve a second order temperature compensation of V REF (see (14), (15), (18), and (19)).
Transistors operating in the sub-threshold region are prone to process variations and modelling error of the sub-threshold slope factor. As a result, the VR in Fig. 7 includes a 4-bit trimming circuit in cell 6 to change the aspect ratio term K A,6 . It helps to compensate the variation and mismatch effects by increasing or decreasing the PTAT slope factor through a digital control. The unit-cell design with a multiplier ratio m helps achieve a compact layout with a good matching between the transistors. The bulk nodes of the PTAT cell transistors N i and N ii (i = 1,2,3,4,5,6) are connected to the ground V SS . As result, high ohmic p-wells at various intermediate potential levels are avoided. It improves the latch-up immunity and reduces the risk of startup issues.

A. Simulation Results
The DC post-layout simulation results in Fig. 8 show the temperature dependence of V CTAT and V PTAT to design a V REF . The normalized plots highlight that ∂ V PTAT /∂ T cancels out ∂ V CTAT /∂ T over the temperature range from −40 • C to 120 • C. The second-order temperature dependence in (19) is positive, resulting in an increasing ∂ V PTAT /∂ T over temperature until 80 • C. Since the bulk of the PTAT-cell NMOS transistors (see Fig. 7) are connected to V SS , the V TH term in (17) becomes more significant for increasing V DS,i at higher temperatures. The increasing V TH results in a reduction of ∂ V PTAT /∂ T at higher temperatures, as shown in Fig. 8. On the other hand, V CTAT has a negative first-order and second-order temperature dependence as shown in (14) and (15). Thus, the ∂ V CTAT /∂ T curve has a similar behavior as the ∂ V PTAT /∂ T curve. As highlighted in Fig. 8, the ∂ V CTAT /∂ T shows a mild dependence on the bias current I REF which generates the voltage drop across the BJT Q1. Across the temperature range, the output V REF is first-order and second-order temperaturecompensated. Fig. 9 quantifies the effect of process variation on the output voltage V REF . V PTAT is dependent mainly on design parameters, and has little variation across process corners. On the other hand, V CTAT generated using a vertical PNP-transistor is prone to process variations. It is slightly compensated by the variation of the bias current I REF , which is generated using poly-resistors. In the fast corner, I REF is 30% higher due to the lower resistance of the poly-resistors [31]. The higher output bias current I REF helps to generate a higher V CTAT and compensate the lowering of V BE of the vertical PNP-transistor (see (13)). Similarly, the decrease of I REF helps to compensate the increase of the V BE in the slow process corner. It results in a highly robust V REF with +/− 0.8% variation across process corners, as shown in Fig. 9.
The Monte-Carlo post-layout simulations of 500 runs for V REF in Fig. 10 show a mean μ V REF of 473.5 mV, and a sigma σ of 4.5 mV (+/-2.7%) for a trimming code of 0100.   The low-power nature of the current mirror in the design presents a challenge to ensure a correct startup at lower levels of V DD . The post-layout transient simulation in Fig. 11 shows that the V BE is generated as soon as the CR is operational. The output voltage V CTAT generation is dependent on the startup time of the nanowatt unity-gain buffer. The current mirror in the VR gets biased at this time, resulting in the drain nodes of the current mirror transistors getting pulled up to V DD −V OV . The effect is seen in the simulation curves of the Post-layout simulated power consumption of the VCR versus changes in supply voltage V DD and temperature.
intermediate PTAT nodes V P1 and V P3 , which are pulled to this voltage level before starting to find the right operation point at 0.7 ms. The PTAT cells start from the left-most cell 6 until cell 1 because of the series nature of the design. The ramp-up of the PTAT cells of the VCR is considerably slower in a slow corner and cold temperatures. A 1 pF MOS capacitor C L with an area of 100 μm 2 connected at the output V REF helps to reduce the output ripple.
The line regulation (LS) and PSRR are DC and AC supply sensitivity indicators. As seen in (21), the output V REF has an inherent low dependence on the supply voltage. Accordingly, we have, where g m,N 11 is the transconductance of the PTAT cell 1 transistor N 11 in Fig. 7. The source-follower design structure of the PTAT cell limits the output resistance and, thus, improves the PSRR, as seen in (22). The PSRR of the VR is also dependent on the PSRR of the CR (see (22)). Fig. 12 shows the post-layout simulated power consumption of the VCR. It consumes 32 nW at 20 • C for V DD = 2 V. Fig. 12 shows that the total current consumption is almost unaffected by changes in V DD . It is because of the fixed bias current used in current mirror branches in CR (see Fig. 4) and VR (see Fig. 7). The bias current has a low dependence on supply voltage variation. The NMOS voltage divider is an exception which does not have a fix bias current. The threshold voltage of the NMOS transistors in the divider varies across the temperature range from −40 • C to 120 • C. As a result, the total current consumption changes by a factor of 1.7x across the temperature range.

IV. MEASUREMENT RESULTS
The proof-of-concept voltage-current reference VCR as a part of a testchip was designed in an in-house 130 nm CMOS technology. The initial design was done in an n-well CMOS  process where the NMOS transistors had no possibility of a buried p-well. As a result, most of the NMOS transistors in the design have a bulk connection to ground. The VCR occupies a chip area of 0.04 mm 2 as shown in the chip microphotograph and the layout inset in Fig. 13. A total of 10 bare-die samples from a nominal process lot were directly bonded onto an FR4 PCB and measured. The PMOS gate-coupled pairs have a common-centroid layout to minimize mismatch effects. The poly-resistors used in the CR are the most significant contributors to the overall area of the VCR. The unit-cell design approach of the transistors in the CR and the VR helps to build compact layout structures with common-centroid topology.
The chips have been characterized in the temperature range from −40 • C to 120  absolute value of the poly-resistors (see (5) and (7)) and the V TH variation of the transistor MN 2 (see Fig. 4). Additionally, the V TH variation of MN 2 has a direct impact on the first-order temperature coefficient of I CTAT (see (7) and (8)). The V TH variation, thus, causes a few CR samples to have a clear CTAT or PTAT behavior, as seen in Fig. 14. The CR trimming circuit has been designed to compensate process corner variations and reduce the spread of the output I REF with minimal impact on the TC. Thus, CR measurements done with an individual trimming for every sample reduces the σ/μ spread of I REF from 0.29 nA/1.9 nA to 0.2 nA/2 nA. Measurement results of I REF reveal a bigger σ spread compared to the post-layout simulations (σ = 0.23 nA). It arises from the usage of the minimum width poly-resistors which are highly prone to mismatch [33].
The output voltage of the VR has been connected to an on-chip unity-gain buffer to increase the output drive strength and connect to a Keysigt 34470A digital multimeter.   dependence on the supply voltage variation. V REF has a mild dependence on V DD at cold temperatures and higher supply voltage level of 3 V. It arises from a technology dependent bulk effect in the NMOS voltage divider (see Fig. 7) built using triple-well transistors.
The minimum supply voltage V DD of the sub-1V VR is defined by the emitter-base voltage of the bipolar transistor and an overdrive voltage of the current mirror (see Fig. 7). As seen in Fig. 17, the VR starts up at a minimum V DD of 0.95 V. With increasing V DD , the VR achieves a line sensitivity of 0.2%. It can be attributed to the low dependence of the output V REF on V DD (see (22)). On the other hand, the minimum V DD of the CR is only limited by the voltage drop across the transistors in the PTAT current reference sub-circuit (see Fig. 4). The CR requires a minimum V DD of 0.85 V (see Fig. 17). A line sensitivity of 4% is achieved from a supply voltage V DD range from 0.95 V to 2.5 V. Fig. 18 shows the post-layout simulated and the measured PSRR of the output voltage V REF versus frequency. As seen in the measurement results in Fig. 18, the VR has a PSRR of 49 dB at 10 Hz, which is an indicator of the line regulation. It highlights the low dependence of V REF on supply voltage as also shown in (21). The PSRR has been measured only up to 2 kHz in order to exclude the effect of the output buffer amplifier connected at the output node V REF . At 868 MHz which is the input frequency of the RF-powered WuRx, the VR achieves a PSRR of 37.6 dB, as seen in simulations. A typical 2 mV P−P V DD ripple at this frequency affects V REF by only 0.03 mV P−P making the VR highly suitable for RF energy harvesting applications.

V. COMPARISON WITH RELATED WORKS
In order to compare the performance of the proposed VR with the related works, a Figure of Merit (FoM) that considers the temperature range (T RANGE ), the TC, the power consumption, and the silicon area, can be expressed as [16]: The FoM, as seen in (23), is higher for wide-temperature range VRs. The second-order temperature compensation of the VR helps to achieve a good performance over an extended temperature range from −40 • C to 120 • C. Fig. 19 shows the FoM of the recent voltage references (VRs and VCRs) with respect to the power consumption. As far as the performance of the voltage reference is concerned, the designed VCR has the best FoM number compared to other VCRs in [14], [37], and [38].
As far as the performance of the standalone VR is concerned, Fig. 19 highlights three distinct groups of VRs. The high-power BGR-based VR in [39] is designed for a high accuracy at the cost of higher power consumption, achieving a smaller FoM. The ultra-low-power CMOS-based VRs in [10], [15], [16], and [17] achieve a higher FoM. They do not have an inbuilt CR and employ native MOS devices where the leakage current determines the output voltage V REF . The leakage current based CMOS VRs are not suitable for energy harvesting sub-systems which typically have a significant high frequency 2 mV P−P output ripple on the harvested supply voltage (f = 868 MHz) [2]. The high frequency ripple on the supple voltage causes an inrush current through the low-impedance path of the parasitic capacitors. If the inrush current is higher than the bias current, it can trigger a wrong operation point in the ultra-low-power leakage current-based CMOS VRs. On the other hand, the designed VR and the nanowatt VRs in [11], [12], [37], and [38] achieve a good tradeoff between accuracy and power consumption. They are less susceptible to process corner variations and high-frequency supply voltage ripples. They achieve a very good FoM for a low-power consumption, as seen in Fig. 19. Table I shows the comparison of the performance of the designed VCR with the previously reported VCRs and VRs.   Table I. The works in [10], [15], and [38] report a lower power consumption at room temperature, but their power consumption increases by a factor of more than 50x over the temperature range. The minimum supply voltage V DD of 0.95 V satisfies the requirement of RF-powered WuRx applications. The designed VCR additionally includes a sub-50 mV VR unlike the other listed VCRs.

VI. CONCLUSION
This paper presents a novel nanowatt voltage-current reference fabricated in a 130 nm CMOS process. The core of the design lies in a shared-resistive nanoampere CR with output current I REF , used as a bias current for the generation of the curvature-compensated sub-1V VR. The VR includes a hybrid architecture combining BGR and CMOS-based references. An iterative approach of optimizing the design parameters was done to achieve a second-order temperature-compensated output voltage V REF  The design methodology of the VCR temperature compensation mainly depends on the design parameters and it has a low dependence on the technology parameters. As a result, the VCR design can be easily implemented in other bipolar CMOS processes. The novel design of the CR results in the generation of an additional sub-50 mV voltage reference which can be used as a low-voltage reference for analog/mixedsignal blocks. The proposed voltage-current reference is highly suitable for RF-powered wake-up receivers and ultra-lowpower IoT nodes.