A Detailed Model of Cyclostationary Noise in Switched-Resistor Circuits

The Switched-Resistor (S-R) technique is becoming more and more interesting to implement low-voltage low-power active- RC filters with high tuning range and front-end amplifiers for biomedical circuits and systems. This approach exploits MOS switches driven by a duty-cycle-controlled clock signal to achieve tunability of the equivalent resistance and, hence, of the RC time constant. Since S-R circuits can be considered as linear periodically time variant (LPTV) systems with sampled outputs, we exploit the theory of the adjoint (inter-reciprocal) network in order to develop a detailed model of the cyclostationary noise involved in this kind of circuits. The proposed model allows to gain insight into the different noise sources and transfer functions involved, highlighting the circuit parameters on which the cyclostationary noise depends. Validation of the proposed model has been carried out by comparing analytical results against periodic noise simulations referring to a commercial 130nm CMOS process. The validation activity has confirmed the good accuracy of the proposed noise model and provided some useful design guidelines to optimize the noise performance of S-R circuits.


I. INTRODUCTION
N OWADAYS, an ever-increasing number of integrated devices for biomedical applications requires high resistance values to implement very large time constant with a small area footprint and low input noise. In fact, biological signals, characterized by a dc component due to electrode-skin contact, require analog front-end amplifiers based on AC coupling with very low cut-off frequencies (below 1Hz) in order to remove the dc offset and properly process the signal itself. The implementation of these very large time constants on a CMOS integrated circuit is severely limited by the area requirements both of capacitors and of resistors. In fact, the capacitance per area is limited to a few fF/μm 2 , if extra technological steps to exploit special dielectric materials are not implemented. Large physical resistors also require a huge Silicon area, hence alternative approaches such as Switched-Manuscript received 16  Capacitor (S-C) or pseudo-resistor have been proposed to minimize the area footprint.
High resistance values are required also in new generation neural recording multi-electrodes systems, which exploit multiplexing techniques and implement front-ends based on transimpedance amplifiers (TIAs) [1]. TIAs for biomedical applications often require high-valued feedback resistances which can be tuned over a wide range of transimpedance gains and exhibit low input referred noise [2].
Designers of CMOS integrated circuits for biomedical applications typically exploit the Switched-Capacitor [3] or the pseudo-resistor [4], [5] approaches to implement large resistance values in order to handle the tradeoff between tuning range, noise and linearity. Nevertheless, it has to be pointed out that, in order to tune the resistance value of Switched-Capacitor resistors, the clock frequency has to be varied, thus changing the sample rate of the system, and this can be a disadvantage in many applications. Furthermore, the noise generated in Switched-Capacitor circuits is inversely proportional to the capacitance value, resulting in a further tradeoff between area and noise minimization [6]. Coming to pseudo-resistor implementations, their resistance value is typically tuned over a wide range by changing the gate-source voltage. However, when using this technique, the value of the equivalent resistance is strongly non-linear and also very sensitive to the common mode voltage and to process, supply voltage and temperature (PVT) variations. To mitigate these issues, many pseudo resistor topologies have been recently proposed [5], [6], [7], [8] which, however, result in worse noise performance and higher power consumption. Furthermore, the noise contributions in pseudo-resistors strongly depend on MOS devices sizing and operating points, but typically an active device generates more noise than a passive element such as a polysilicon resistor due to flicker and shot contributions [8].
In the latest years, the Switched-Resistor (S-R) approach has become more and more popular within the community of integrated circuits designers [9], [10], [11], because it allows implementing very high equivalent resistances with excellent tuning capability and good linearity performance. In fact, the S-R approach allows to boost up the value of a physical resistor through the adjustment of the duty cycle of the clock signal that drives the switch in series with it, without modifying the sample rate of the system. Another interesting characteristic of the S-R technique resides in the fact that, in S-R circuits, the output voltage is already sampled, and this allows to simplify the ADC design without considering This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ an additional sample-and-hold block. All these characteristics make the S-R approach a valid alternative solution to Switched-Capacitor and pseudo-resistor approaches, especially in biomedical applications. In fact, the S-R approach has been successfully exploited in [12], [13], and [14] to implement tunable filters, TIAs and analog front-ends for biomedical integrated circuits.
Designers of biomedical integrated circuits need accurate noise models in order to satisfy constrains in term of area occupation and power consumption while achieving the target performances for their circuits. Nowadays many noise models are available for Switched-Capacitor [15], [16] and pseudoresistor circuits [4], [17], which are able to handle analog tradeoffs in front-ends design. To the authors' knowledge, no accurate model has been presented so far for the S-R approach, and noise is typically modeled as the thermal noise related to the equivalent (average) resistance [11].
The derivation of an accurate noise model of S-R circuits is not trivial due to the cyclostationary nature of noise in these circuits. In fact, the noise analysis of LPTV (linear periodically time-variant) circuits, such as S-R systems, has to be carried out by determining the time variant frequency transfer functions for each noise source of the circuit. For this purpose, many theoretical contributions have been proposed in the literature starting from the '50s, simplifying every time the complicated analysis [18], [19], [20].
Recently, some novel theoretical contributions have been proposed in the literature to solve LPTV circuits [21], [22], [23] such as S-C circuits, mixers, and samplers. A simple method proposed by Pavan for the analysis of N-path passive filters [24], [25], [26] exploits the adjoint network theory [21], [27] to build a LTI (Linear Time-Invariant) equivalent circuit that shows a transfer function equivalent to the one of the sampled LPTV system.
In this paper we demonstrate that the conventional noise model adopted for the S-R [9], [28] is inaccurate for values of duty cycle below 1%. We then propose a new analytic noise model of S-R circuits, based on the approach proposed by Pavan, which is able to describe in an accurate way all the main noise sources that involve MOS switches and polysilicon resistors. The proposed model has been validated varying devices parameters and duty cycle values, highlighting a high accuracy in predicting the white noise components with average errors below 1%.
The paper is structured as follows: section II reviews the basics of cyclostationary noise in LPTV systems. The proposed detailed noise model is introduced and explained in section III; firstly, the adjoint network related to the S-R circuit under analysis is derived and then the equivalent transfer function for each noise source is analytically evaluated. The validation of the model is presented in section IV, highlighting the accuracy of the model and providing noise optimization guidelines. Conclusions are finally drawn in section V,

II. REVIEW OF CYCLOSTATIONARY NOISE IN LPTV SYSTEMS
A linear periodically time-varying system can be characterized by an impulse response h (t, τ ) in which the input signal x(u) is applied at the instant of time u = t − τ , whereby t represents the observation time and τ is the difference between the observation time and the time of application of the impulse itself. Since the system is causal, h (t, τ ) = 0 f or t < τ. In such a system, the excitation time plays the role of explorer of different system conditions that distinguish the time-varying nature. For a generic time-varying system the output response can be expressed as follows: Now considering a complex exponential input signal x (u) = e j 2π f u , (a generic input signal can be expressed as sum of infinite complex exponentials) the output y (t) of the system can be rewritten as: The above equation leads us to define the time-varying transfer function H (t, j 2π f ) that links the time-domain response of the system with the single-frequency input signal: If we assume that the system is periodic with period T s , then the impulse response is also periodic, and the following property holds: In a similar way, the above property holds also for the timevarying transfer function, which can therefore be expanded in Fourier series referring to the time t. This last assumption allows us to express the frequency response (3) as: where are the coefficients of the Fourier series expansion of the timevarying transfer function (3). Hence, the time-varying impulse response can be seen as a sum of time-shifted nonperiodic impulse responses; then, in frequency, a sum of the harmonic transfer functions H k ( j 2π f ) multiplied by the different complex exponentials related to the time-shifts. If we consider the sampled output y (nT s ), combining (2) and (5) we obtain a discrete sequence of samples which can be considered as the output of an equivalent LTI system: The above considerations show that, due to the periodicity property, the output samples of a generic LPTV system are Fig. 1. An LPTV network varying with sample period T s , whose output i 2 (t) is periodically sampled at T s , with a time offset t 0 . Fig. 2. Determining the impulse response h eq (t) of the equivalent LTI system using the adjoint network. An impulse voltage is injected into the "output" port of the adjoint network, and the open circuit voltage in the input port is h eq (t).
equal to the output samples of an equivalent LTI system built using as equivalent frequency response the sum of harmonic transfer functions of the LPTV system itself.
An interesting approach to derive the equivalent frequency response H eq ( f ) has been proposed by Pavan in [24] and [25], where the adjoint network theory is exploited to compute the equivalent impulse response h eq (t) (i.e., the inverse transform of (8)) in a few simple steps.
As thoroughly descripted in [21], given a network N, the related adjoint networkN has the same graph as N and can be built from it by applying the following substitutions rules: 1) The electrical passive elements (linear resistors, capacitors, and inductors) do not change in the equivalent domainN ; 2) Each switch driven by a waveform φ(t) has to be replaced with a switch driven by a waveform φ(−t); 3) Linear controlled sources in the LPTV system are replaced by the symmetrical (dual) linear controlled sources in the adjoint network. For instance, a voltagecontrolled voltage source has to be replaced with a current-controlled current source with exchanged ports. Let us consider the 2-port LPTV network (N) shown in Fig. 1, excited by the current source i 1 (t) at the port 1, and whose output short circuit current i 2 (t) is sampled with period T s at the port 2. The corresponding adjoint networkN is shown in Fig.2, and when excited with an impulse voltage source δ(t) at port 2 the open-circuit voltage taken at the port 1 ofN gives h eq (t).
By generalizing the above considerations to the multi-input case, as shown in Fig. 3, the output of interest in a generic multi-port LPTV network is assumed to be v o (t), while r generic sources are applied to the input ports. Working in the adjoint domain, the equivalent LTI system of the LPTV network can be obtained by applying an impulse voltage source at the output port of interest, while r open-circuit voltages or short-circuit currents are picked up at the respective r input ports [21], providing the equivalent impulse responses h eq,i (t), i = 1, 2, . . . r . These functions can then be exploited to calculate the sampled output of the original network as the sum of the input sources filtered by the respective equivalent  impulse functions. Fig. 4 details this process for a single input, highlighting also the sampling of the output with a zeroorder hold (ZOH) block, that models the fact that sampling is performed by a square-wave clock with a given duty cycle D and not by a train of ideal pulses.
If the r input sources are assumed to be the noise sources n i (t) of the network, then, referring to the block scheme in Fig. 4, this procedure allows to derive the output noise power spectral density (PSD), taking into account its cyclostationary nature and output sampling. In fact, once the equivalent impulse responses, or the equivalent transfer functions (8), have been determined, the PSD of the output S o ( f ) can be determined starting from the PSD S in of n i (t) as follows: and D is the duty cycle of the zero-order hold block, and then rewritten as: (si nc(x) denotes the function si n(π x)/π x, as usual). This approach will be applied in the next section to develop, for the first time in the literature, a detailed model of noise in S-R circuits, that takes into account its cyclostationary nature to achieve good precision even for very low duty cycles.

III. SWITCHED-RESISTOR NOISE MODEL BASED ON ADJOINT NETWORK THEORY
The scheme of an ideal S-R is depicted in Fig. 5. The conventional S-R model [9], [11] is based on a MOSFET Transmission Gate (TG) switch, characterized by its onresistance r on , in series with an ideal poly resistor R p (the off-state resistance of the switch r o f f is assumed to be infinite). A duty-cycle-controlled clock is applied to the TG switch to set the average current that flows in the series. A detailed model of the S-R technique accounting also for parasitic capacitances and off-state resistances has been recently presented in [29] by the authors to accurately predict the equivalent resistance R eq of a S-R.
If the noise behaviour of a S-R circuit has to be described, the only model available in the literature [9], [28] is the one based on the thermal noise generated by the equivalent resistance: It can be easily shown that the model in eq. (12) gives a reasonable accuracy only for duty cycle values higher than about 1 to 10%, even when the equivalent resistance obtained by the model in [29] is used. Integrated filters for biomedical and IoT devices often require high resistance values to implement the very large time constants needed to process the low frequency biological signals [30]. By using the S-R technique, the value of a reference resistor is multiplied by a factor dependent on the duty cycle of the clock signal. Since the silicon area occupied by a physical resistor is related to the desired resistance value, chip area can be strongly reduced if a small physical resistor is used and the equivalent resistance is boosted through the S-R technique. To achieve resistance multiplication factors higher than 100, the value of the duty cycle has to be reduced below 1%, and in all these cases the above noise model is not enough accurate.
When using a polysilicon resistor, the resistance value R p is changed by varying the length L R of the physical resistor, according to [31] (R p = r L R , where r is the resistance per unit length of the polysilicon strip), and the associated parasitic capacitance results C Rp = 1 3 c r R p , (where c is the parasitic capacitance to substrate per unit length of the polysilicon strip).
Since the SR approach is interesting to implement very high resistance values with small silicon area, we have chosen the resistor type with the highest resistivity among the available resistors in the target 130nm process.
The main difference when using other kind of resistors is in the value of the associated parasitic capacitance, but the model is able to handle any kind of resistor. To quantify the accuracy of the conventional S-R noise model we refer to a commercial 130nm CMOS technology and consider the power spectral density (PSD) of the S-R circuit in Fig. 5 for R p = 100k and a transmission gate (TG) switch with minimum sized MOS transistors. Periodic steady state (PSS), periodic AC (PAC) and periodic noise (Pnoise) simulations within the Cadence Virtuoso TM environment have been exploited to estimate the equivalent resistance R eq and the noise PSD as a function of the duty cycle D. Fig. 6a shows the S-R noise PSD for different values of the duty-cycle D, highlighting how the conventional model in eq. (12) (dashed line) is different from the Pnoise simulation result (solid line) especially at low duty cycle values. To better quantify the accuracy, we report in Fig. 6b the relative error of the conventional model in (12) with respect to Pnoise simulations for different duty cycles.
The values of both the maximum (259%) and average (75%) relative error confirm that the conventional model in (12) is not able to adequately describe the cyclostationary noise in S-R circuits for duty cycle values lower than about 1%. This is due to the fact that the conventional model in (12) does not take into account the effective noise sources and how noise propagates to the output. As an additional remark, it has to be noted that, using the approximation R p D in place of R eq results in an even higher error between predicted and simulated noise, due also to the poor estimation of R eq . In this paper, in order to develop a model, suitable to accurately describe the cyclostationary noise in S-R circuits, we start from the detailed model of the S-R technique presented in [29] and add to it the most relevant noise sources, thus obtaining the equivalent circuit reported in Fig. 7. The detailed S-R model proposed in [29] is characterized, other than by the parasitic capacitance C p , also by a finite channel resistance in the off state, that significantly affects the average current flowing in the S-R at low duty cycles. Hence the equivalent circuit in Fig. 7 includes five main noise sources: • the noise source i As shown in Fig. 7, the values of the noise sources due to the MOS transistors of the switch depend on their switching states. In fact, the MOS devices operating in strong inversion (on phase) generate a noise which is significantly different from the one obtained when operating MOS transistors in cutoff (off phase). In particular, it is found that, for low values of the duty cycle D, the TG switch exhibits a not negligible noise.
It has to be remarked that only white noise sources have been considered in the model; in fact, a preliminary simulation campaign allowed us to verify that flicker noise contributions of MOS transistors are negligible with respect to their white noise counterparts on the integrated noise of the S-R. This point will be better clarified in section IV.
In order to simplify the circuit in Fig. 7, the four noise sources related to the TG switch have been represented with an equivalent noise model that highlights the operating parameters in both the working phases.
In the simplified model reported in Fig. 8, the ideal switches are controlled by clock signals with opposite phases and both the channel resistances and the noise sources of Mp and Mn are substituted with the corresponding equivalent resistances and noise sources as follows: where the symbol || denotes the parallel connection between two resistances. The circuit in Fig. 8 is clearly a LPTV cyclostationary network with sampled output: the clock driving the TG, as shown in Fig. 5, periodically modifies the network changing the value of the switch equivalent resistance from the on to the off value, and samples the output with a zero-order hold. The approach described in section II can therefore be applied to evaluate the equivalent output noise, sampled by the clock signal, due to the different noise sources. Since different noise sources have to be considered for the TG in the on and off phases, the approach has to be applied twice, considering the clock signal and its complement.
By applying the adjoint network theory to the equivalent circuit in Fig. 8, the equivalent impulse responses related to the three equivalent noise sources taking into account both the on and off phases of the TG switch can be computed. These equivalent impulse responses can then be used to evaluate the sampled noise contribution due to each noise source i n (i  Fig. 9. The block scheme reported in Fig. 9 highlights that the generic output noise contribution i no related to a specific input noise source i n has to be calculated by considering two equivalent transfer functions H eq,on and H eq,of f . Each one of these equivalent functions is computed by applying an impulse signal δ(t) to the adjoint circuit in each one of the two working phases as will be better detailed in the following. Fig. 9 also shows that the filtered signals are sampled with period T S . Since a clock with duty cycle D is used for sampling, a zero-order hold (ZOH) block has to be considered. This can be modelled with a rectangular function Rect(t) whose hold time is different for the two clock phases.
In particular, the hold time is DT S for the on phase (block ZOH(D) in Fig. 9) and (1-D)T S for the off phase (block ZOH(1-D) in Fig. 9). Fig. 10 illustrates the sampling instants of the two ZOH blocks which are at T − s in the off phase and at T + s in the on phase respectively. In the following subsection A, we compute the adjoint network related to the noise sources i R p n , whereas in subsection B we work on i sw on n , and i sw of f n . Fig. 9. Block scheme for the computation of the output noise contribution related to the generic input noise source i n .  Finally at the end of this section we will combine the different contributions in order to determine the PSD of the output noise of the S-R circuit.

A. Adjoint Network for Computation of the Noise Contribution Due to the Polysilicon Resistor i R p n
The adjoint network to calculate the equivalent transfer function related to the noise source of the polysilicon resistor R p is shown in Fig. 11.
An impulse voltage source δ(t) is applied at the port where the short-circuit current is measured in Fig. 8, and the output voltage is taken across the resistor R p , where the current noise source were applied in the original circuit. The switch is modelled by two resistors (r sw on and r sw of f ) with in series ideal switches controlled by clock signals with opposite  phases, as better detailed in Fig. 12, that also highlights the relationship between the clock phases in the original and adjoint networks.
We evaluate the equivalent impulse response when an ideal impulse signal is applied in any time instant t belonging to the interval [0, (1 − D) T s ] (off phase), given by the open-circuit voltage across R p : where u −1 (t) is the unitary step function. Once the memory element has been charged through the impulse signal, we can analyze the periodic decay of the charge across the parasitic capacitor C p , illustrated in Fig. 13, determining from it the recursive equation describing the phenomenon [24], [25]. Fig. 13 clearly demonstrates what was modeled in (5), i.e. that the overall impulse response can be seen as a sum of time-shifted nonperiodic impulse responses. The discharge voltage across the capacitor, and therefore the equivalent impulse response, is characterized by a periodic trend, in which the time constant of the discharge changes its value during each clock cycle according to the clock value as shown by the following equations: From the equations (17) describing the recursive phenomenon [24] we obtain: where γ = αβ The function p of f (t), drawn in Fig. 13, describes the exponential decay of the equivalent impulse response in the first working interval 0 < t < T s after the impulse has been applied and can be expressed as the sum of two terms p of f,A (t) and p of f,B (t) defined in each half period as follows: The two equations (24) describe the discharge of C p through the switch in the off and on phases, respectively. Applying the Fourier transform at the recursive impulse function we obtain the equivalent frequency response in the off state: By transforming also the p of f (t) function in frequency domain we can explicitly express the equivalent frequency response as a function of circuit parameters.
Hence, after algebraic manipulation, H R p eq,of f turns into: According to Fig. 9, the output noise component due to the noise source i R p n is obtained combining both the equivalent frequency responses in the off and on phases. In order to compute the equivalent frequency response in the on phase, defined when the impulse signal is applied in any instant t belonging to the time interval [(1 − D) T s , T s ] we can follow the same steps made for the computation in the off state. In this case, the impulse signal is applied at the beginning of the time interval [(1 − D) T s , T s ], resulting in a clock configuration shifted with respect to the off -state clock configuration by a quantity dependent on D. By analyzing the adjoint circuit in Fig. 14 resulting in the transfer function, as in (31), shown at the bottom of the next page.

B. Adjoint Network for the Computation of the Noise Contributions Due to the TG Switch Input Noise Sources
A similar analysis can be repeated for what concerns the noise sources associated with the TG switch: as shown in Fig. 15, the impulse input voltage is still applied at the port 2 of the adjoint network, but now the output voltage is taken across the switch resistance. More in detail, we are interested in calculating the transfer functions related both to the noise produced by the switch in the on phase i sw on n and to the noise produced in the off phase i The periodic decay of the charge, reported in Fig. 16, allows us to deduce the recursive equation as we did in the previous subsection. In this case, for (1 − D) T s < t < T s , the equivalent impulse response is equal to zero, since the switch connected to r sw o f f is open (r sw of f I = 0). The periodic discharge process, shown in Fig. 16, highlights a discontinuous trend, in which the discharge process of the capacitor goes on through the R p and r sw on resistances. We can write for the successive phases:    function, already defined in the previous subsection, thus obtaining: Combining the equation (27a) with (35), we obtain the equivalent frequency response related to r sw o f f in the off phase: In the same way, we can compute the impulse response h sw on eq,o f f (t) taking the output across r sw on , still considering the input applied in the time interval [0, (1 − D) T s ] . In this case, at the application time of the impulse the switch connected to r sw on is open, and consequently the impulse response is equal to zero in the first semi-period.
For the successive phases, equations similar to (33) can be written to describe the discharge of C p , but considering the alternate phases, as shown in Fig. 17:: Also in this case we can rewrite (38) in a recursive form, exploiting the function P o f f,B already defined in the previous subsection: After computing the Fourier transform of the recursive equation (39) and substituting the expression of into it, we get the equivalent frequency response related to i sw on n in the off state: The same analysis has to be repeated for an impulse input voltage applied in the time interval [(1 − D) T s , T s ], (on phase), to calculate the transfer functions related to the noise sources i sw on n and i sw of f n for a sampling instant in the on phase. From the analysis of the adjoint network in Fig. 18, following the procedure already described, we obtain:

C. Complete Model of Cyclostationary Noise in S-R Circuits
The evaluation of all the equivalent frequency responses in the previous subsections allows us to assemble the complete model of cyclostationary noise in S-R circuits. At this purpose, denoting with S  Fig. 9 to compute the PSD of the overall output noise. As a first step we compute the overall output noise PSD in the on phase S on ( f ) as follows: Finally, combining (42) and (43), the complete expression of the cyclostationary noise PSD in a S-R can be computed as shown in the equations (44), as shown at the bottom of the next page.

IV. VALIDATION RESULTS
The proposed noise model has been validated considering a S-R implemented in the 130nm CMOS technology from STMicroelectronics using low-leakage MOS devices. A high resistivity polysilicon resistor with nominal resistance R p of 100k and an associated parasitic capacitance C Rp of 9.18 f F has been used to implement the S-R circuit. The TG switch has been implemented with minimum sized MOS devices resulting in r sw on about equal to 13.83k and r sw o f f in the T range. The TG switch is driven by a 100kHz clock signal whose duty cycle D is varied from 0.0001% to 100%.
Periodic steady state (PSS), and periodic noise (Pnoise) simulations are used to estimate the noise PSD as a function of the duty cycle D. The number of harmonic tones in the PSS and Pnoise simulations has been set to 1,000 and 50 respectively.
The analytical model developed in the previous sections has been approximated using a finite number of spectral replicas k equal to the number of harmonic tones considered in the Pnoise simulation. The PSD of the output noise of the S-R is reported in Fig. 19 for D = 0.0005% showing how the proposed model agrees well with simulation results in spite of the very low value of the duty cycle. In fact, even if we have neglected flicker noise in the model, the average and maximum relative error across the frequency range from 1H z to 100k H z are lower than 0.5% and 1.9% respectively. Furthermore, the RMS noise (integrated from 1H z to 100k H z)  More in detail, for low values of D the dominant noise contribution is the white component of MOS devices in the TG switch and the noise coming from the polysilicon resistor is negligible. On the contrary, the noise coming from the polysilicon resistor becomes dominant for duty cycle values higher than 0.1%. The relative error between Pnoise simulation and the proposed noise model vs. D (referring to the traces in Fig. 20) is reported in Fig. 21, showing how the proposed model exhibits a maximum relative error of 9.8% for values of D in which noise contributions of the TG and the polysilicon resistor result quite similar to each other. The average relative error across the duty-cycle range is 2.3% confirming the good accuracy of the proposed model. Similar results have been obtained by evaluating the PSD at 1Hz.

A. Validation of the Model When Varying Circuit Parameters
A more complete model validation has been carried out by considering the variations of main circuit parameters such as  the width and length of MOS transistors implementing the TG switch and the value of the polysilicon resistor R p with the associated parasitic capacitance C p . Fig. 22 shows the maximum (a) and average (b) relative error (@ 1k H z) of the proposed model with respect to the Pnoise simulation across the whole D range as a function of the width W of MOS transistors implementing the TG switch by keeping the length L equal to the minimum allowed by the technology. The maximum relative error is also in this Similarly, Fig. 24 shows the maximum (a) and average (b) relative error (@ 1k H z) of the proposed model with respect to Pnoise simulation across the whole D range as a function of the length L of MOS devices implementing the TG switch by keeping the width W equal to the technology minimum. In this case the maximum error approaches 26%, and is much higher than the maximum error over W . Fig. 25 shows the PSD @ 1k H z of the output noise current of the S-R estimated   The power spectral density evaluated over the considered values of L highlights a good prediction of the model for the whole L range, except for large value of L (in particular for L = 10μm), where the Flicker noise contribution is relevant with respect to the white noise contribution. Fig. 26 shows the maximum (a) and average (b) relative error of the proposed model with respect to Pnoise simulation across the whole D range as a function of the value R p of the polysilicon resistor and the associated value C p of the relative parasitic capacitance. The resistance values associated to parasitic capacitances for the adopted technology are reported in Table I. The average and maximum error of 4.7% and 1% respectively highlight an accurate prediction of the model for a wide range of R p values. Table II summarizes  We would like to point out that, even if the proposed model is less general than PSS+Pnoise simulations which allow to describe almost all nonlinear circuits with a periodic steady state response, the proposed model is suitable to adequately describe cyclostationary noise in switched resistor applications, and provide a dramatic reduction of simulation run-time as shown in Table II.

V. CONCLUSION
In this work we have presented a detailed model of the cyclostationary noise in S-R circuits. At this purpose, the theory of the adjoint network applied to LPTV systems has been successfully exploited. The proposed model has been validated by comparing analytical results against Pnoise simulations carried out with the design kit of the 130nm CMOS technology from STMicroelectronics. The proposed model exhibits an average relative error across the whole duty cycle range of 2.3%. The average error over the considered W values ranging from (0.15 μm to 50 μm) are below 2.7%. Considering a minimum sized TG switch, the maximum relative error of the model is below 9.8% and this maximum error is found for values of D in which noise contributions of the TG and the polysilicon resistor result quite similar to each other. Due to its accuracy in describing the noise filtering effect of the parasitic capacitances, the proposed model allows a better optimization of the switched resistor (polysilicon value and switch sizing), in terms of the tradeoff between noise performance and linearity, (linearity get worse if the switch resistance is not negligible with respect to the polysilicon resistance).
The proposed analytical model highlights the effect of the different noise sources and the relative transfer functions, allowing to gain insight into the dominant noise contributions and into the effects of the different circuit parameters on the cyclostationary noise. The figures reported in the validation section give a clear picture on the effect of W , L and R p on the cyclostationary noise of the S-R. As shown in Table II, the proposed analytical model allows a dramatic reduction of simulation run-time especially when design parameters are swept to optimize the circuit.