Scalable Multi-Stage CMOS OTAs With a Wide CL-Drivability Range Using Low-Frequency Zeros

This work introduces a multi-stage CMOS OTA design technique that allows cascading identical gain stages (for arbitrarily scalable high DC gain) while driving an ultra-wide range of capacitive loads (<inline-formula> <tex-math notation="LaTeX">$\text{C}_{\text {L}}\text{s}$ </tex-math></inline-formula>). At the heart of the proposed design is a new frequency compensation technique (FCT) that relies on low-frequency left-half-plane zeros to allow the proposed OTA to operate for a desired closed-loop behavior. In this work, classical gain-stages (i.e., differential pair and common source transistors) are used to design fully-differential 2-, 3-, 4- and 5-stage CMOS OTAs. The proposed 2-to-4-stage designs have been fabricated in TSMC 65 nm CMOS process and the measurement results show that the 2-stage OTA is achieving a DC gain of 50 dB with a <inline-formula> <tex-math notation="LaTeX">$\text{C}_{\text {L}}$ </tex-math></inline-formula>-drivability ratio (i.e., <inline-formula> <tex-math notation="LaTeX">$\text{C}_{\text {L,max}}/\text{C}_{\text {L,min}}$ </tex-math></inline-formula>) of <inline-formula> <tex-math notation="LaTeX">$10,000\times $ </tex-math></inline-formula>, the 3-stage OTA is achieving a DC gain of 70 dB with a <inline-formula> <tex-math notation="LaTeX">$\text{C}_{\text {L}}$ </tex-math></inline-formula>-drivability of <inline-formula> <tex-math notation="LaTeX">$1,000,000\times $ </tex-math></inline-formula>, and the 4-stage OTA is achieving a DC gain of 90 dB with a <inline-formula> <tex-math notation="LaTeX">$\text{C}_{\text {L}}$ </tex-math></inline-formula>-drivability of <inline-formula> <tex-math notation="LaTeX">$1,000,000\times $ </tex-math></inline-formula>. This is a 10-to-1000-time improvement in the state-of-the-art, as the highest <inline-formula> <tex-math notation="LaTeX">$\text{C}_{\text {L}}$ </tex-math></inline-formula>-drivability reported to date is <inline-formula> <tex-math notation="LaTeX">$1000\times $ </tex-math></inline-formula>. Accordingly, the proposed OTAs can cover a wider range of applications than any other reported works.

Scalable Multi-Stage CMOS OTAs With a Wide C L -Drivability Range Using Low-Frequency Zeros Mahmood A. Mohammed , Member, IEEE, and Gordon W. Roberts , Fellow, IEEE Abstract-This work introduces a multi-stage CMOS OTA design technique that allows cascading identical gain stages (for arbitrarily scalable high DC gain) while driving an ultra-wide range of capacitive loads (C L s). At the heart of the proposed design is a new frequency compensation technique (FCT) that relies on low-frequency left-half-plane zeros to allow the proposed OTA to operate for a desired closed-loop behavior. In this work, classical gain-stages (i.e., differential pair and common source transistors) are used to design fully-differential 2-, 3-, 4-and 5-stage CMOS OTAs. The proposed 2-to-4-stage designs have been fabricated in TSMC 65 nm CMOS process and the measurement results show that the 2-stage OTA is achieving a DC gain of 50 dB with a C L -drivability ratio (i.e., C L,max /C L,min ) of 10,000×, the 3-stage OTA is achieving a DC gain of 70 dB with a C L -drivability of 1,000,000×, and the 4-stage OTA is achieving a DC gain of 90 dB with a C L -drivability of 1,000,000×. This is a 10-to-1000-time improvement in the state-of-the-art, as the highest C L -drivability reported to date is 1000×. Accordingly, the proposed OTAs can cover a wider range of applications than any other reported works.
On the other hand, since these applications are being fabricated using advanced nanometer CMOS technology nodes, OTAs are facing challenges to achieve high DC gain values. Consequently, many CMOS OTA architectures have been proposed in the literature to meet the various design requirements to drive a wide range of C L while achieving adequate DC gain. Despite having stability challenges once configured in closed loop, cascading gain stages is believed by the authors to be the preferred method to achieve sufficient DC gain in modern CMOS technology processes operating with low voltage supply levels [12], [13]. Fig. 1(b) shows the cascading scheme of N gain-stages to achieve high DC gain. Ultimately, such OTAs are configured in a closed loop as also seen in Fig. 1(b), where the output voltage (V O (t)) must remain bounded. To easily discuss the previously reported works, one can categorize them based on the number of gain stages placed in cascade and evaluate their C L -drivability ratio (i.e., C L,max /C L,min ).
As for 4-stage CMOS amplifiers, they can provide higher DC gains, but once they are configured in closed-loop, they are a challenge to stabilize. Therefore, only a few works have proposed 4-stage designs to drive a wide range of C L s, such as [32] and [33]. However, the maximum C L -drivability ratio was limited to 30× [33]. To the best of the author's knowledge, there is no reported 5-stage OTA with a wide C L -drivability.
Therefore, in this work a new FCT is proposed to enable cascading multiple gain-stages while driving an ultra-wide range of capacitive loads. The proposed FCT is ideally applicable to N-stage CMOS OTAs, which offers wider design choices for DC gain and power consumption. However, for simplicity and as a proof of concept, 2-, 3-, 4-and 5-stage CMOS OTAs are demonstrated in this work. Furthermore, the proposed FCT uses a multi-Miller R-C compensation circuit across the gain stage to position the Pole-Zero Pair (P-ZP) created by the R-C compensation networks below the unity-gain frequency (ω t ) of the compensated OTAs. On doing so, the P-ZP will increase ω t of the compensated OTA once the zeros are positioned at low frequencies. The additional increase in ω t can be traded off for higher C L by placing the dominant pole at higher frequencies.
This paper is structured as follows: the overall proposed idea is presented in Section II. In Section III, the design choice for the gain-stages is introduced. In Section IV and V, the detailed implementation of the proposed FCT is discussed. In Section VI, verification of the proposed technique is discussed based on schematic and post-layout simulations. Section VII shows the experimental results and robustness of the proposed FCT, while Section VIII compares the proposed 2-, 3-, and 4-stage OTAs with the state-of-the-art works. Finally, Section V concludes the work presented in this paper.

II. CASCADING MULTI-STAGE CMOS OTAS AND
INCREASING THEIR C L -DRIVABILITY: THE OVERALL PROPOSED IDEA The proposed design of the scalable multi-stage CMOS OTA, shown in Fig. 1(b), consists of cascaded-gain stages which can achieve an overall DC gain ( A DC,N ) of where Ai is the gain provided by the i th gain stage and N is the number of gain-stages. On the other hand, and since this is a CMOS-based OTA, poles and zeros will be part of the OTA's realization. Usually, in such OTAs, in addition to the 3-dB frequency, each gain stage will produce a P-Z Pair. Therefore, the open-loop input-output Transfer Function (TF) takes on a cascade of bilinear forms as follows where ω P0 is the 3-dB frequency, ω Pi and ω Zi are the openloop P-Z pairs which are produced by the compensation circuit of each stage. The diagram of Fig. 1(b) and its bilinear TF of Eqn. (2) can be realized by using the differential-ended circuit level implementation of Fig. 2. The gm-blocks will be responsible for achieving the required DC gain, while the R-C compensation networks (which are connected across each stage) will properly place the open-loop P-Z pairs at the required frequencies.
The purpose of the proposed architecture is to provide a uniform scalable DC gain while driving a wide-range of capacitive loads. Therefore, all gain-stage will be designed to achieve the same Ai. However, for such cascading of multi gain-stages to be stable and to allow the OTA to drive a wide range of C L s (regardless of the number of gain stages) a new FCT is proposed in this work using low-frequency zeros. It is the application of these low frequency zeros that make this work unique in the field of OTA design.

A. The Use of Low-Frequency Compensation Zeros
The objective of the proposed FCT is to identify the placement of the proposed scalable multi-stage OTA's poles and zeros, so that the load-drive capability and unity-gain bandwidth are maximized (while the OTA is exhibiting a stable closed-loop response). This is further constrained by requiring the settling time of a unity-gain closed-loop configuration be bounded by some desired value denoted by T D S . This can be mathematically expressed as follows: subject to: Solving this problem will lead to an OTA with a higher GBW and greater C L driving capability. It is important to Fig. 3. Transistor level implementation of the scalable N -stage CMOS OTAs. The circuit uses a differential-ended configuration, the right-hand side is shown here only, and an identical left-hand side has been omitted for simplicity.
note that this problem includes both small and large-signal effects. Eqn. (3) contains a two-dimensional objective function involving ω t and C L , which are inversely inter-dependent. That is, if C L increases, ω t decreases. This makes it difficult to identify the maximum. Instead, this optimization problem is performed in two steps using the following sequential, noniterative procedure. The first step is to solve the problem expressed as maximize: subject to: This can be performed using a small-signal AC analysis, so it takes very little time to perform with a transistorlevel simulation. This step places the poles and zeros at desired frequency locations for maximum unity-gain frequency while having the minimum required capacitive load, C L,min , (say 0.5 pF). Next, a transient analysis is performed on the OTA in a closed-loop configuration subject to an input step V in with different load conditions, i.e.

maximize:
subject to: While this approach can be executed in a sequential, noniterative manner, the result may not be optimal but orders of magnitude simpler to implement with excellent results. Consequently, to satisfy Eqn. (4) and (5), the proposed FCT positions the open-loop P-Z pairs of Eqn. (2) at frequencies below ω t and above ω P0 , without being excluded or canceled (i.e., unlike conventional FCTs [34]), such that Based on the P-Z pair arrangement in Eqn. (6), ω t can now be maximized (to satisfy Eqn. (4)) where it is no longer equal to the GBW (as it is usually the case in conventional FCTs) but it is now given by According to Eqn. (7), the lower the zeros' frequencies the higher ω t is; hence the higher C L is for a desired settling time.
Interestingly, having open-loop P-Z pairs below ω t creates P-Z doublets in closed-loop. It was shown [35] that the closedloop P-Z doublet deteriorates the OTA's settling time. Therefore, such P-Z pairs' arrangement has not been introduced in the literature before. However, a fundamental theory has been introduced in [12] revealing that the impact of the P-Z doublets on the settling time of CMOS OTAs can be minimized by positioning the open-loop zeros (i.e., ω Zi ) at low frequencies provided there is sufficient DC gain. Consequently, this theory revealed untapped opportunities to cascade many gain stages, which will be exploited in this work.
Since the objective of the proposed FCT is to identify the positions of the OTA's poles and zeros according to Eqn. (6), it is required to identify what governs these poles and zeros from the circuit level realization's perspective. Once these relationships are identified, the detailed steps of implementing the proposed FCT can be easily revealed.

III. THE CIRCUIT LEVEL IMPLEMENTATION OF THE PROPOSED SCALABLE MULTI-STAGE CMOS OTAS
The proposed design of the scalable multi-stage CMOS OTA, shown in Fig. 2, consists of a differential input-stage, cascaded by many identical gain-stages. Fig. 3 shows the transistor level implementation of the differential stage, which serves as the first stage (i.e. M 1 -M 5 ), followed by identical common-source (CS) gain-stages (the second stage consists of M 6,2 and M 7,2 while subsequent stages consist of transistors identical to them, i.e., M 6,3 and M 7,3 , …, M 6,N and M 7,N ).
Having a differential pair followed by CS gain stages is a conventional way to configure OTAs. However, when N = 2, this particular OTA has long been assumed to be limited to applications with pF-range loads [36]. Here, through employing the proposed FCT on this circuit, it will be shown that it can increase its C L -drivability up to the nF-range. Also, when N = 3, similar architectures have been described in the literature having a Nested-Miller Capacitor (NMC), as in [22], to help stabilize the OTA. Interestingly, this NMC is of no use in the proposed design technique, and this will contribute to having an area-efficient OTA design. Moreover, using this conventional architecture will show that the proposed FCT is unconstrained by a specific OTA circuit topology.
As mentioned earlier, the purpose of the proposed architecture is to provide a uniform scalable DC gain, where each gain-stage will produce the same DC gain. Hence, all gain  stages will be biased at the same voltage, and all transistors' sizes of the CS gain stages will be identical. However, one can design the gain stages to have different DC gains and get a non-uniform increase in A DC without increasing the compensation effort.
These gain stages are biased with the current mirror transistors M CM , M 5 and M 7,i . However, to ensure proper biasing of the output voltages, the Common-Mode Feedback (CMFB) circuits of Fig. 4 have been included in the design. These CMFB circuits are based on standard techniques as described in [36] and [37]. If the 2-stage OTA is to be designed, then the CMFB circuit of Fig. 4(a) is to be used, and the CMFB voltage (V CMFB ) is to be created at the drain of M C1 . But if N = 3 (i.e., the 3-stage OTA is to be designed), V CMFB is created at the drain of M C2 (in Fig. 4(a)). When more than three gain-stages are required, the DC gain will significantly increase, thus, the CMFB circuit of Fig. 4(a) will not be able to hold the biasing voltages at the output of all gainstages. Therefore, an extra CMFB circuit will be used to keep the biasing voltages of these additional gain-stages within the required values. Fig. 4(b) shows the extra CMFB circuit that will be included when N ≥ 4. In this case, the CMFB circuit of Fig. 4(a) will be connected at the differential output of the 3 rd gain-stage, while the CMFB circuit of Fig. 4(b) will be connected at the differential output of each new gain-stage (i.e., N ≥ 4). Now, to identify the exact DC gain equation of the proposed OTA, the small signal model is to be discussed. Fig. 5 shows the ideal single-ended small-signal model of the circuit level realization seen in Fig. 2. From circuit theory, one can identify that the small-signal low-frequency gain of each stage is (g m · R O ). Therefore, the overall DC gain, A DC,N , can be expressed as

A. The Small-Signal Model of the Proposed OTA
where g m,i is the transconductance of each stage, R O,i is the output resistance of each stage. The first step in the proposed design technique involves setting the voltage gain of the OTA to some desired value. This will pin-down the required sizes of all transistors to meet power consumptions and overdrive voltage requirements. Also, this step will define the values of the small-signal parameters (i.e., g m,i and R O,i ) of all stages.
Once g m,i and R O,i are defined, the multi-Miller R-C compensation circuits will control the positions of the openloop P-Z pairs. Interestingly, positioning the poles and zeros is not limited to the use of Miller R-C compensation circuits, as other compensation schemes can also be used for this purpose.
According to the TF of Eqn. (2), the OTA will have a different number of poles and zeros based on the designer's choice for N. For example, if N = 2, one can identify that the 2-stage OTA has three poles and one zero. Typically, only twopoles of this circuit are of concern, as the third is assumed to be at a frequency much higher than ω t . As a result, the frequency locations of the two-poles and the zero are approximated based on some assumptions as follows [36], [37]: The third pole at ω P_ par -typically ignored in the analysis -has an important design value in the proposed theory and needs to be considered here. It can be approximated by [37]: where C O,1 represents the total shunt capacitance to ground on the output node of the first stage of the OTA and it consists of numerous parasitic elements.
Since the R-C compensation circuits are creating paths between the inputs and outputs of all gain-stages, coupling between stages and correlation between the poles and zeros' positions will occur. Therefore, apart from the two-stage OTA, identifying the exact positions of poles and zeros and/or deriving their exact expressions (using the R-C compensation circuit of Fig. 3) is limited. Also, due to the existence of the parasitic capacitances (i.e., C O,1 , C O,2 , …, and C O,N-1 ), parasitics poles will also exist and they will also correlate with the open-loop P-Z pairs. In addition, relying on the exact equations of poles and zeros will require re-defining them whenever a new stage is added, hence re-designing the R-C compensation circuit with the addition of each new gain-stage. This will highly complicate the design process. Moreover, adding the CMFB circuits of Fig. 4 to the small-signal model to derive the exact poles and zeros' equations will add a new complexity dimension.
Consequently, to avoid the complexity of using the exact poles and zeros' equations, a scalable FCT is proposed in this work. The proposed FCT starts by designing the compensation circuit of the 2-stage OTA first to satisfy Eqn. (4). This is achieved by adjusting R C1,(2−stage.) and C C1,(2−stage.) such that ω Z 1 is positioned at low frequency (LF) so that ω t is increased, provided it meets certain conditions (to be described later). Then, the proposed FCT will scale the R-C compensation circuit for higher stages while maintaining sufficient values for ω t . Finally, the proposed FCT follows Eqn. (5) to increase C L -drivability of the proposed OTAs for a desired settling time. These steps will be clarified in the following sections.

IV. IMPLEMENTATION OF THE PROPOSED FCT -STEP (1):
INCREASE ω t UNDER SMALL C L USING LF-ZEROS Conventional FCTs are usually applicable for specific number of stages and/or specific OTAs' circuit topologies. However, the proposed FCT has the advantage of being ideally applicable to N-stage CMOS OTAs, as well it is not constrained by any specific circuit topology, and it is technology independent. Therefore, the key idea of this work is to accurately perform the proposed FCT which is described by Eqn. (4) and Eqn. (5). In this section we shall start by following the technique described by Eqn. (4) to design the 2-stage OTA of Fig. 3, then scale it for higher stages.
A. Implementation of the Proposed FCT Having N = 2 The starting point in implementing the proposed FCT is to begin with a two-stage OTA, thus, Eqs. (9) -(12) will govern the positions of ω P0 , ω P1 , ω Z 1 , and ω P_ par , respectively.
Usually, in conventional 2-stage OTAs, where Miller R-C compensation networks are used, stability is ensured by positioning ω P1 at low frequencies (by increasing the value of C C1 ) and placing ω P0 and ω Z1 at frequencies above ω t or by positioning them at the exact same frequency to achieve a pole-zero cancellation [34]. Thus, ω t in such conventional designs is the GBW, and will be referred to (here) as: ω t,re f . Fig. 6(a) shows the magnitude response (i.e., black-dashed line) of such conventional designs, where ω t,re f is given by However, relying on large values of C C1 to compensate for the 2-stage OTA will slow down the OTA's response, increase the silicon area, and most importantly, prevent the R-C compensation circuit from being scaled for higher stages as will be discussed in the next subsection. Consequently, the proposed FCT adapts a different arrangement of poles and zeros to enhance ω t while having a small C L (C L,min ) (i.e., say 0.5 pF); hence, Eqn. (13) will be extended to accurately express the new proposed arrangement of the poles and zeros. Then, the additional increase in ω t can be traded off for higher C L .
According to Eqn. (13), it should be obvious that the value of ω t,re f can be increased by increasing A DC,2 and/or ω P1 . However, A DC,2 has already been pre-defined, consequently, increasing ω t,re f is simply achieved by increasing ω P1 , or in other words; by reducing the value of C C1 according to Eqn. (9). The new position of ω P1 after reducing C C1 is shown (in blue) in Fig. 6(a). Interestingly, pushing ω P1 to higher frequencies, by reducing C C1 will allow ω P0 to become the 3-dB pole of the OTA instead of ω P1 (i.e., ω P0 mainly depends on g m,2 and C L ). This will become useful when increasing the C L -drivability in the next section. However, reducing the value of C C1 alone is a bad design practice because it will alter the stability of the OTA as ω P1 will move towards ω P0 , and at the same time, ω Z1 will be shifted to higher frequencies (i.e., as depicted by Eqn. (11)). Therefore, the gain roll-off will drop to values around −40 dB/dec, and thus, the Phase Margin (PM) will also drop. But, if one can properly re-position ω Z1 (after reducing C C1 ) according to Eqn. (6), ω Z1 will counteract the effect of the two poles on the gain-roll off and the PM. As a result, the stability issue can be controlled and the new expression of ω t can be seen in Eqn. (7).
To re-position ω Z1 according to Eqn. (6) and shift it from higher to lower frequencies as seen in Fig. 6(a), one can use a large R C (i.e., ∼ k). As a result, the impact of the proposed FCT in this 1 st step, compared to the conventional design, is shown in the AC response of Fig. 6(a).
Since A DC,2 is pre-defined, and ω P0 is almost independent of the R-C network, Eqn. (7) indicates that the maximum value of ω t (i.e., near-optimum) can be achieved, ideally, by increasing ω P1 while decreasing ω Z1 . However, the limitation of the upper value of ω t is ω Ppar , seen in Eqn. (12) and Fig. 6(a); as there is no full-design control over this parasitic pole. Also, increasing ω P1 while decreasing ω Z1 should be done so that the PM is greater than some desired value. For example, to obtain a PM of 60 • , one can arrange the poles and zeros as shown in the AC phase response of Fig. 6(b). Here, the PM is where θ P,i is the phase of the i th -pole and θ Z ,i is the phase of the i th -zero.
To achieve this at the circuit level, one can start with the minimum possible value of C C1 given by a certain CMOS technology (i.e., slightly higher than C O,1 ). Then, R C (∼ k) is increased in value to achieve the required PM so that ω t ≤ ω Ppar , or until the value of R C becomes impractical in the given CMOS technology. This will allow the R-C circuit to occupy a small-silicon area. Accordingly, with this, the 1 st step of the design process, described by Eqn. (4), would have now been completed for N = 2.

B. Scaling the Two-Stage R-C Compensation Circuit for N ≥ 3 Under C L ,min
To design the 3-stage OTA, a new gain-stage is added to the 2-stage OTA as depicted in Fig. 2 and Fig. 3. Also, to design a 4-stage OTA, two gain-stages are added to the 2-stage OTA, and so on. Each new gain-stage comes with its own compensation circuit. Consequently, a new P-Z pair will be added to the TF with each new stage as described in Eqn. (2). Also, according to Eqn. (7), ω t will significantly increase, as A DC,N will also increase. However, this new value of ω t will most likely exceed the previously defined upper limit of ω t , and parasitic pole at ω Ppar will impact the OTA's PM. Therefore, it would be necessary to re-adjust the value of ω t by re-positioning the poles and the zeros, according to Eqn. (6), whenever a new stage is added to keep ω t ≤ ω Ppar . This can be done by re-sizing the R-C circuit with the addition of each new stage.
Instead of deriving new equations for the poles and zeros for each stage separately, and by knowing that the P-Z pairs have an inverse relationship with R C and C C , the values for C C which was found for the 2-stage OTA can be adjusted according to the constraint equations listed below [12]: and While the R C s can be sized in the opposite manner described by the following two constraint equations [12]: and Thus, the new compensation capacitor (C C(N−1),(N−stage) ) is sized to the minimum capacitance value, which was found for the 2-stage OTA (i.e., C C(N−1),(N−stage) = C C1, (2−stage) ). This highlights the difference between the proposed technique and the conventional methods that rely on large C C1 values to realize 2-stage CMOS OTAs.
Since the constraint equations in (15)-to- (18) show an intuitive technique of sizing the R-C compensation circuits for N ≥ 3, and since there is no need for exact positioning of the poles and zeros, one can slightly tweak these patterns to enhance the open-loop and closed-loop responses if necessary. For example, such tweaking can be done if an exact PM of 60 • is required under C L,min of 0.5 pF. Although such re-sizing of the R-C circuits is not considered systematic, an algorithm can be applied to meet the pole-zero constraints of Eqn. (6).
At this point the proposed scalable N-stage CMOS OTA is compensated to drive C L,min under the required PM. Step (1) is transferring the dependency of the dominant pole to ω P0 (i.e., C L,min ), one should distinguish between compensating the OTAs with C L only and the proposed FCT. Interestingly, one can remove the R-C compensation circuit and rely only on C L to position ω P0 below ω t while leaving the P-Z pairs (i.e., ω P1 , ω Z1 , ω P2 , ω Z2 …ω Pi and ω Zi ) uncontrolled. On doing so, the stability can be achieved once C L,min is increased such that ω t is shifted to frequencies much lower than the P-Z pairs. However, this technique is associated with some important drawbacks. First, this technique is technology dependent, in other words; leaving the P-Z pairs uncontrolled, will allow the parasitic capacitances (which are technology dependent) to decide their frequency positions. Second, this technique will work, if and only if, a large C L,min is required (i.e., in the range of tens of nano-Farads). Also, this large C L,min is increasing with the addition of extra gain stages, due to the increase in A DC,N (i.e., ω t ). For these reasons and others, this dependency of the dominant pole on C L has been claimed to be a bad design practice in [38]. Nevertheless, this will not be an issue in the proposed FCT, since the P-Z pairs have already been positioned at the required frequencies. Consequently, one can define the range of C L that prevents the P-Z pairs from alternating the OTA's stability. To easily capture the shortage of relying on C L only to compensate the OTA, and to clearly discuss the advantages of the proposed FCT in increasing C L -drivability of the proposed OTA, Fig. 7 introduces the relationship between the PM and C L .
The PM is an open-loop parameter that can indicate the closed-loop step response behavior. Fig. 7 shows how the PM is changing with the increase in C L based on different scenarios of positioning the OTA's poles and zeros in the proposed FCT. Accordingly, it indicates the behavior of the closed-loop step response. Also, one can use Gain Margin (GM) to indicate the closed-loop behavior as will be done while verifying the proposed OTA designs.
Since the design achieved through Step (1) was still loaded with a very small C L (i.e., C L,min = 0.5 pF) and achieved a sufficient PM (say 60 • ), one can carry on from this point and investigate the impact of increasing C L on the PM. According to Eqn. (9), increasing C L,min will result in shifting ω P0 to lower frequencies, thus, shifting ω t to lower frequencies as well. As can be seen in Fig. 7, this will create three different regions based on the new positions of ω t with respect to the P-Z pairs. In each region the impact of increasing C L on the PM will depend on the position of ω Zi with-respect-to ω Pi , thus, three cases will be created in each region. To clarify this, let's consider the cases when N = 2, and discuss the PM behavior in these three regions based on the position of ω Z1 and ω P1 .

A. Region (1): ω t > P-Z Pairs
This region starts at C L,min , where the OTA exhibits a stable response (as discussed in Step (1) of the proposed FCT) and the P-Z pairs are positioned below ω t . As C L increases, ω t moves towards the P-Z pair and a slight drop in the PM will occur. However, this will not affect the closed-loop response as the PM ≥ 45 • . Therefore, the impact of positioning ω Z1 with-respect-to ω P1 will not impact the OTA's stability in this region. Nonetheless, it is recommended to achieve sufficient values for PM in Step (1) (i.e., PM ≥ 60 • ) to expand this region as much as possible. This can be done by positioning ω Z1 at low frequencies.
In this region, one can clearly distinguish between the proposed FCT and the conventional techniques that depend on C L only (i.e., the dashed-dotted black line in Fig. 7), where stability cannot be ensured at small values of C L .

B. Region (2): ω t ∼ P-Z Pairs
Once increasing C L to higher values, such that ω t will be located slightly above, in between, or slightly below the P-Z pair, the impact of positioning ω Z1 with-respect-to ω P1 will become significant. In other words, according to Eqn. (14), if ω Z1 is positioned at low frequency (i.e., Case (1): ω Z1 < ω P1 ), it will compensate the PM drop that will be caused by ω P1 , and the PM will be kept above 45 • (i.e., the solid-blue line in Fig. 7 is always within the blue shaded area). However, ω Z1 will have less impact on the PM if it is positioned slightly above ω P1 (i.e., Case (2): ω Z1 ≥ ω P1 ). Consequently, the PM might drop to values below 45 • and above 10 • (i.e., the dashed-red line is entering the light-redshaded area in Fig. 7). Nonetheless, the step response will exhibit a stable underdamped behavior, which will be seen as an increase in settling time. However, if ω Z1 ω P1 (i.e., Case (3)), the PM drop (with the increase in C L ) might reach values below 10 • , hence, the step response will become unstable within a specific range of C L (i.e., the dotted-green line will enter the green-shaded area between C L,1 and C L,2 in Fig. 7). Consequently, Case (3) shows the worst case of stability with the proposed technique. Although the step response might exhibit a stable response for 0 • ≤ PM ≤ 10 • , it is assumed unusable in Fig. 7 (i.e., the dark-red shaded area) as it will be associated with excessive ringing [39].
Interestingly, further increase in C L , within Region (2), will allow ω t to be at frequencies lower than the P-Z pair, thus, the PM will start increasing toward 90 • .
Despite having a stable response for 10 • ≤ PM ≤ 45 • , the amount of ringing might introduce untolerated noise for some applications. Therefore, the P-Z pairs must be optimized for such applications by setting the local minimum PM (PM ,min ) to a given value (say 45 • ) for a range of C L s. If the PM ,min cannot be achieved, then the proposed OTA might not be suitable for the given application.

C. Region (3): ω t P-Z Pairs
Once the PM reaches 90 • , the proposed FCT reaches its definition for the maximum capacitive load (C L,max ), because at PM = 90 • , the R-C compensation circuits will have no more impact on the PM, and C L will compensate the OTA. Accordingly, one can define C L -drivability ratios as Case (1) and (2) Since the P-Z pairs will have no impact on ω t in this region, the unity-gain frequency will be referred to as ω t, f inal (seen in Fig. 7) and it can be written as: ( A DC,N ω P0 ). Also, the step response will follow a single-time-constant behavior.
Apparently, the proposed OTA will exhibit a stable response once increasing C L beyond C L,max , where the PM will always be ∼ 90 • , but it will not be included in the discussion to avoid confusing the proposed FCT with conventional ones.

D. Settling Time Requirements
According to Eqn. (5), the objective of this section is to define the range of C L that corresponds to a desired settling time. Since the design achieved through Step (1) was still loaded with a very small capacitance (i.e., C L,min = 0.5 pF), the settling time (T S,initial ) of the closed-loop amplifier would be very short. Indeed, it is assumed to be much shorter than the desired settling time T D S , and hence an increase in settling time can be traded-off for a higher C L . Knowing that T D S is widely varying based on the required application, as seen in Fig. 1(a), one can define a range of C L 's that corresponds to a range of different settling time values by searching on the step response of the closed-loop amplifier beginning with C L,min . This can be simply done by increasing C L , starting from C L,min , until the desired settling time is reached, as long as C L ≤ C L,max . At this point, the desired C L (C L,desired ) can be identified. Here, V in can be driven with a step input whose magnitude can be in the small or large-signal range. There are no constraints on the input condition.
Increasing C L , starting from C L,min , will result in different closed-loop responses based on the P-Z pair's positions, as can be seen on the right-hand side of Fig. 7. Therefore, Fig. 8 builds on these different cases for positioning the P-Z pairs and indicates the relationship between settling time and C L . Here one sees three curves of settling time T S vs. C L Fig. 8. Relationship between settling time and C L , showing the different cases that will be created based on the proposed FCT. Note: the nonlinear shape of curves is only for illustrative purposes.
for different P-Z pairs' positions and maximum C L conditions. It should be noted here that curves of T S vs. C L are nonlinear.
For all scenarios of positioning the P-Z pairs, settling time is increasing with the increase in C L , however, when ω Z1 < ω P1 the OTA will exhibit faster closed-loop response as the region of underdamped behavior will not be entered (this is shown in the solid-blue line in Fig. 7 and also seen as the solid-blue line of Fig. 8). As for ω Z1 ≥ ω P1 and ω Z1 ω P1 , the closed-loop response will be partially experiencing stable-underdamped response (as seen in Fig. 7); which will result in slower settling times. Consequently, for the same T D S the case of positioning ω Z1 at low frequencies will achieve higher C L -drivability, as C L,desired will be larger (i.e., C L,desired,3 > C L,desired,2 > C L,desired,1 in Fig. 8). But, for the case when ω Z1 ω P1 (i.e., green-dotted line of Fig. 8) the OTA will not be stable between C L,2 and C L,1 as the PM might drop to values below 10 • (the green-shaded area of Fig. 7). Clearly, the benefit of adding zeros at LFs is to boost ω t and PM. This will also allow increasing C L while still achieving sufficient GBW. However, it is the GBW that will define the speed of the proposed OTAs and not necessarily the boosted ω t .
If the C L range between C L,min and C L,max does not meet the requirements on T D S , one can re-adjust the reference design of the OTA by optimizing the biasing voltages and the transistors' aspect ratios. Consequently, the R-C compensation circuits are to be re-designed according to the proposed FCT. If this still does not allow the proposed technique to meet the requirements on T D S , then the proposed OTA is not suited for the given application.

VI. VERIFICATION OF THE PROPOSED DESIGN TECHNIQUE
Following the steps in Eqs. (4) and (5), and the detailed procedure of section IV and V, the OTA of Fig. 3 has been designed to achieve a scalable DC gain while driving a wide range of C L s. The standard TSMC 65 nm CMOS process has been used to design this OTA with a supply voltage (V DD ) of 1 V. Lower V DD values can still be used to drive the proposed OTAs while still achieving sufficent open-loop and closed-loop performances. However, since the goal here is to verifiy the proposed design technique, a nominal V DD value of 1 V will be used. Also, Cadence CAD tools have been used for all simulation investigations. Despite being applicable to N-stage OTAs, the proposed FCT will be verified using 2-, 3-, 4-and 5-stage OTAs.
First, each gain stage has been designed to achieve a DC gain of about 25 dB, thus, the 2-, 3-, 4-and 5-stage OTAs of Fig. 3 are providing a post-layout A DC of 51.18 dB, 77.2 dB, 92 dB, and 110 dB, respectively. To achieve this, the gain stages have been biased with gate voltages at about 0.5 V (i.e, V D D 2) and the CS gain stages are designed  Fig. 3. Also, the current source transistors For the 2-and 3-stage OTA, the CMFB circuit of Fig. 4(a) has been used, while the CMFB circuit of Fig. 4(b) has also been added for the 4-stage OTAs with I BIAS_1 ≈ 3 μA, while V BIAS_2 has been connected to V B I AS to reduce the number of pins once fabricating the chip. As for the 5-stage OTA, an extra CMFB circuit has been added with I BIAS_1 ≈ 3 μA, and V BIAS_2 ≈ 0.37 V. Due to the loading effect of the CMFB circuit of Fig. 4(b), the 4-stage OTA has achieved an A DC,4 of 92 dB instead of values around 100 dB. The same can be said for the 5-stage OTA. The A DC values for all stages are shown in Fig. 9(a).
After designing the OTA for the required DC gain, the focus will now be on verifying the proposed FCT by designing the compensation circuits according to Step (1) and (2) (i.e., Eqn. (4) and (5)), so that ω t is enhanced to a nearoptimum value to allow the OTA to drive a wide C L range.

A. Verification of Step (1): Increase ω t Under C L = 0.5 pF
The proposed FCT starts by designing the 2-stage OTA's R-C compensation circuit (according to Step (1)) having C L,min = 0.5 pF. Therefore, the value of C C1,(2−stage) has been selected to be almost 5 times the value of the parasitic capacitance given by the technology (i.e. C C1 = 50 fF). For R C1,(2−stage) , the value has been swept starting from 1 k, and increased till R C1,(2−stage) reached a value of 21 k. Thus, f t becomes 293.2 MHz. This value of f t is near optimum as PM = 70.9 • , which is a reasonable value to indicate stability.
The frequency positions of the P-Z pair after designing the 2-stage OTA's R-C circuit according to Step (1) are: f Z1 = 166 MHz and f P1 = 180.5 MHz. Clearly, these values satisfy Eqn. (6) and the parasitic pole constraint at 787 MHz, which is twice the value of f t .
Following the scalable technique given by Eqs. (15)-to-(18), the R-C compensation circuits of the 3-, 4-, and 5-stage OTAs are designed as shown in Table I. Based on these values, Eqn. (6) is not satisfied as some P-Z pairs have poles frequencies ω Pi that are less than the zero frequencies ω Zi . However, this is not a concern. For example, in the 3- the PM has reached values around 60 • . Also, ω t is at high frequencies and ω Ppar are still higher than ω t . Fig. 9 summarizes all schematic and post-layout results for open-loop and closed-loop configurations after implementing Step (1) of the proposed FCT under C L = 0.5 pF. A summary of the most important metrics that can be drawn from these simulations are shown on the right-bottom corner of Fig. 9.
Clearly, all stages are achieving the required DC gain while exhibiting a stable response. However, the 4-stage post-layout magnitude response is affected by the parasitics after extraction, and its gain roll-off at ω t is less than -20 dB/dec. As a result, the 4-stage OTA step response (under V in = 100 mV) is showing some ringing, which is translated as an increase in its settling time compared to other stages.
Also, one can notice a dip in the 4-and 5-stage phase responses. Therefore, for further tests of stability, the output swing of the proposed 5-stage OTA has been simulated for different peak-to-peak input voltages as can be seen in Fig. 9(e). The results indicate no unforeseen stability issues. Also, the proposed OTAs have been tested having a closed-loop gain of 10 dB and the results exhibit a stable response as well.
Also, as can be seen in Fig. 9's summary of results, the Average Slew Rate (Avg. SR) is decreasing as the number of gain stages is increasing, where the Avg. SR of the proposed OTAs can be approximated by where I M,4_AVG , I M6,2_AVG , …, I M6,N_AVG are the average currents (i.e., average of the rising and falling edges) flowing at the output node of each gain stage, while C C,1_eq , C C,2_eq , …, C C,N_eq are the equivalent compensation capacitances which are seen at these output nodes. For instance, (C C,1_eq ≈ C C1 ), The simulations are showing that I M,4_AVG is 7.1 μA, while I M6,N_AVG (for N = 2 to 5) is 358.5 μA. Since I M,4_AVG I M6,N_AVG , the output node of the 1 st stage is dominating the SR behavior of the proposed OTAs given that the OTAs are driving pF-range C L . Thus, since C C1 is the capacitance seen at the output node of 1 st -stage, and according to the proposed FCT, C C1 is increasing as the number of stages is increasing; hence, the Avg. SR is decreasing as the number of stages is increasing. If a very large C L is required (i.e., in the nF-range), the dependency of the SR will be transferred to the output node of the last gain-stage. Consequently, one can increase the value of I M6,N to keep the SR within sufficient values. However, by designing the OTA to have a high I M6,N , the power consumption will increase. This will become a trade-off between C L , SR, and power consumption. Interestingly, some designs in the literature have adapted alternative class AB implementations that preserve SR with lower power consumption as in [31]. However, adding such class AB output stage might affect the proposed poles/zeros arrangement, which might require further optimization. The post-layout power consumption in the proposed designs is 106 μW, 180.1 μW, 276.7 μW, and 387 μW, for the 2-, 3-, 4-, and 5-stage OTAs, respectively. Also, one should consider that this value is for a fully differential-ended topology.
Even though many resistors are being used in the proposed OTAs, the noise has not been affected that much, because the resistors mainly affect the noise of the output stage, while the 1 st stage noise is the dominant noise. Therefore, the postlayout input referred noise at 10 kHz is 82.2 nV/ √ Hz for the 2-and 3-stage OTAs and 78.1 nV/ √ Hz, for the 4-stage OTA.

B. Verification of
Step (2): Maximize C L for a Desired T S After designing the proposed OTAs to properly drive C L,min of 0.5 pF, the goal now is to define the range of C L under which the 2-, 3-, 4-and 5-stage OTAs' closed-loop responses are stable, and to find the corresponding settling time for this Fig. 10. Impact of maximizing C L according to Step (2) of the proposed FCT on PM, GM, and settling time: (a) the relationship between PM and C L as described in Fig. 7 for the proposed OTA, (b) the relationship between GM and C L for the proposed OTAs, (c) the relationship between PM and C L when designing the proposed OTAs with a conventional FCT that depends on C L only, and (d) the relationship between settling time and C L as described in Fig. 8. range of C L . Therefore, similar steps of creating Fig. 7 and Fig. 8 (i.e., investigating the PM and the settling time variations vs. the increase in C L ) are being followed here.
Consequently, Fig. 10(a) shows the simulation results of PM vs. C L . Apparently, the proposed 2-stage OTA (solid-blue line with circles) is stable with PM ≥ 45 • , for all values of C L , except between 10 pF to 100 pF where it goes slightly below 45 • . Therefore, it mainly follows Case (1) of Fig. 7, which is the expected response since ω Z1 < ω P1 . To define C L,max , one can observe the C L value of Fig. 10(a) at which the PM becomes 90 • . Clearly, C L,max is 10 nF; thus, C L -drivability ratio according to Eqn. (19) is 20,000×.
As for the proposed 3-stage OTA, the closed-loop response is always stable as the PM doesn't reach the instability region (i.e., green-shaded area of Fig. 10(a)) with the increase in C L . Clearly, the PM follows Case (2) of Fig. 7, which is an expected response since ω Z1 > ω P1 of the 1 st P-Z pair as mentioned earlier. Interestingly, with C L,max of 10 μF, C Ldrivability ratio of the proposed 3-stage OTA is 20,000,000x.
As for the proposed 4-stage OTA, the PM behavior follows Case (3) of Fig. 7, where it goes below 10 • in between C L,1 = 40 pF and C L,2 = 100 nF. Again, this is an expected behavior due to the 1 st and 2 nd P-Z pairs' arrangement, where ω Z1 ω P1 . Nonetheless, the proposed 4-stage OTA is operating properly under all other values and exhibiting a C L -drivability ratio of 80,000x. The same can be said for the proposed 5-stage OTA" where the PM goes below 10 • in between C L,1 = 5 pF and C L,2 = 10 μF, exhibiting a C L -drivability ratio of 5000x, with C L,max = 5 mF.
Since the PM might not always reflect the actual closedloop step response, and since the open-loop AC response of Fig. 9(a) shows a dip in the phase response below ω t for the 4and 5-stage OTAs, one can use the GM test to ensure its full agreement with the PM and there will be no multiple phase crossover points with −180 • . Fig. 10(b) shows the simulation results of GM vs. C L . Clearly, the GM is ≥ 0 dB in the stability regions which have been defined by the PM in Fig. 10(a).
To clearly measure the improvement that has been done by the proposed FCT on C L -drivability of CMOS OTAs, one can compensate the proposed OTAs with the conventional FCT (i.e., which relies on C L only to compensate the OTA) and compare the results. Fig. 10(c) shows the PM behavior once conventional techniques are used to compensate for the proposed 2-, 3-, 4-and 5-stage OTAs. Clearly, the conventional technique might only work for 2-stage OTA, but it cannot be scaled for higher number of stages (i.e., it is not suitable for scaled-down CMOS technologies) unless large C L s are only required, which is not the case in most applications as depicted in Fig. 1(a).
The results in Fig. 10(a)-(c) pave the way to verify the unity-gain closed-loop step-response of the proposed OTAs to find the relationship between settling time and C L . Since the settling time is expected to vary based on the different cases of positioning the open-loop P-Z pairs as stated in Fig. 8, the 2-stage OTA is expected to have the fastest response as it mostly follows Case (1). Fig. 10(d) verifies this for all C L values above 100 pF. However, although the 3-stage OTA is following Case (2), it exhibits faster response for C L values below 100 pF. The reason for this can be indicated from Fig. 10(a), where the 3-stage OTA is having higher PM values than the 2-stage OTA in between 1 pF to 100 pF.
All other open-loop and closed-loop parameters are being considered as the value of C L is increasing; but for simplicity and to avoid repetition, these parameters will be shown as the proposed OTAs are being validated with measurement results in the following section.

VII. EXPERIMENTAL RESULTS AND ROBUSTNESS TESTS
The standard TSMC 65 nm CMOS process is used to fabricate the differential-ended 2-, 3-and 4-stage CMOS OTAs of Fig. 3 with the devices' sizes shown in Fig. 3, Fig. 4, and Table I. However, the proposed 5-stage OTA has not been fabricated. Fig. 11 shows the fabricated chip's microphotograph. Since a wide range of C L is required, each proposed OTA has been fabricated twice (i.e., with C L on-chip for a small C L = 1 pF and C L off-chips for higher values). To illustrate the area and the elements in fabricating the proposed differentialended 2-, 3-, and 4-stage CMOS OTAs, the layout drawing of the 2-stage OTA is embedded and enlarged in Fig. 11, where the overall dimensions is 53.9 μm × 39.7 μm, resulting in an area of 0.0021 mm 2 . As seen in the layout drawing, R C1 dominates the chip's size and occupies almost half the chip's silicon area. But, as C C1 is set just above the parasitic level, the overall silicon area remains quite small (total area = 0.0021 mm 2 ). The R C used here is the standard N-well resistor with sheet resistance 316 /square. As for the C C1 , a mimcap with the same length and width of 4.8 μm is used for a C C1 value of 50 fF. The same can be said for the 3-and 4-stage OTAs, except more silicon area is required as seen in Fig. 11.

A. Measurements' Results
This chip has been tested in a unity-gain closed-loop configuration to obtain the closed-loop and open-loop performance metrics of each OTA. Table II lists the critical OTA biasing parameters from a step response test involving a 100 mV step input. Subsequently, Fig. 12 show the output step response of the 2-, 3-, and 4-stage OTAs under different values of C L (i.e., starting from C L,min up to C L,max ) as captured by an Agilent DSA80000B oscilloscope. The closed-loop performance metrics (i.e. settling time and SR), for different values of C L , are included on each time plot shown in Fig. 12. Also, Table III    By comparing these measurement results with the schematic and post-layout simulation results we found during the verification, one can conclude that these results are in general agreement with one another. Thus, the proposed FCT is being applied properly. It should be noted, however, that the 4-stage OTA has a C L,1 and C L,2 values that is slightly different than what was predicted by simulation, i.e., 40 pF versus 100 pF for C L,1 , and 100 nF versus 10 nF for C L,2 .

B. Robustness Tests
To ensure the robustness of the proposed design, process corners and Monte-Carlo (MC) simulations have been conducted for different OTAs' parameters, under different C L 's, in open-loop and closed-loop configurations. This was conducted for both schematic-based and post-layout-based designs. Table IV shows a test for the design robustness using the schematic-based MC simulations for the 2-, 3-, 4-and 5stage CMOS OTAs. Here, the Process Variation Coefficient (PVC) [(σ D /μ) × 100%] for all 2-, 3-, and 4-stage OTAs' parameters is less than 5 %. However, PVC increases to values slightly above 10 % for the proposed 5-stage OTA's parameters, except for the DC gain, where the PVC is 4.3 %.
Moreover, to test the proposed OTAs robustness under PVT variations, the post layout-based process corners of the proposed 2-, 3-, 4-and 5-stage OTAs under C L of 1 pF are conducted. Fig. 13 reports the results of different performance metrics' behavior under these process corners. As can be seen in Fig. 13, all process corners, for all metrics, indicates no unforeseen sensitivity issues. Consequently, using the results shown in Table IV and Fig. 13, one can conclude that the proposed OTA designs are robust under PVT variations.  Clearly, the 5-stage OTA shows less robustness compared to other stages. With ft = 89.9 MHz, positioning the 5-stage OTA P-Z pairs becomes tight, which increases the sensitivity to the PVT variations. This indicates that the proposed technique will reach a limit in the number of cascaded gain-stages, which was found to be 8 stages in [12], given that each stage is achieving 25 dB per stage.

VIII. COMPARISON
To clearly highlight the achieved advancements of this work, the proposed 2-, 3-, 4-and 5-stage OTA designs have been compared with previously reported OTA designs. For fair comparison, measurement-based works, where CMOS OTAs can drive a wide range of C L s have been reported in Table V. Therefore, op-amps, simulation-based works (including the proposed 5-stage OTA), and OTAs with a single C L driving capability have been excluded from Table V. Referring back to Fig. 1(a) where the settling time requirements vs. C L for different applications are shown, one can appreciate the need for an OTA with a wide-ranging drivability features, even if the OTA settles in seconds. Fig. 14 superimposes a load-drivability summary of the OTA results of this work with the best results found in the literature [27] and [33], as it compares with the applications reported in Fig. 1(a). As is clearly evident, the proposed OTAs cover more applications than any other reported work.
In addition to the simplicity of the proposed design which uses conventional gain stages with multi-Miller R-C compensation circuits across gain stages, the proposed FCT is applicable to 2-, 3-, 4-and 5-stage OTAs. This is a feature that is not available in any of the previously published works. This offers wider design choices for DC gain and power consumption for different applications.
To set the comparison in a conventional way, the following well-established figures of merit (FOMs) have been used [27]:    V   PERFORMANCE COMPARISON WITH THE STATE-OF-THE-ART MEASUREMENT-BASED OTAS THAT DRIVE A WIDE RANGE OF C L S OTA. Also, the proposed OTAs outperform all other reported works in SIFOM L , where the highest values is reported for the proposed 4-stage OTA (at C L = 100 pF), followed by the proposed 3-stage OTA and then comes the proposed 2stage OTA. However, the proposed 4-stage OTA has a low SIFOM L at C L,max = 100 μF due to the long settling time of such large C L . Also, looking at the OTAs' metrics individually, one can see that the proposed 4-stage OTA has the highest C L,max of 100 μF. Moreover, the proposed 4-and 3-stage OTAs have the maximum C L drivability of 1,000,000x, followed by the proposed 2-stage OTA with a C L -drivability of 10,000x. Moreover, the proposed differential-ended 2-stage OTA occupies the smallest silicon area of 0.0021 mm 2 . Finally, despite using the smallest CMOS technology node of 65 nm and achieving a slightly lower DC gain than other reported works in Table V, the proposed technique can be scaled for higher number of stages and achieve higher DC gain as shown in the post-layout results of the proposed 5-stage OTA with a DC gain of ∼ 110 dB.

IX. CONCLUSION
A new frequency compensation technique that allows cascading multi-stage CMOS OTAs and driving a very wide range of C L (i.e., pF-to μF-range) was introduced. The proposed technique involves positioning the OTA's zeros at low frequencies to increase ω t of the OTA. The additional increase in ω t can be traded off for higher C L by transferring the dependency of the dominant pole to C L . To achieve this, the OTA was designed using multi-Miller R-C compensation circuits across the OTA's gain-stages. Also, the proposed technique was shown to be unconstrained by the OTA's circuit topology. Hence, conventional gain-stages (i.e., differential pair and common source transistors) were used to design fully-differential 2-, 3-, 4-, and 5-stage CMOS OTAs with a C L -drivability of 10,000×, 1,000,000x, 1,000,000x, and 5,000x, respectively. This is 10-to-1000-time improvement in the state-of-the-art. Accordingly, the proposed OTAs can cover a wider range of applications than any other reported works. The proposed 2-, 3-, and 4-stage OTA designs have been fabricated in the standard TSMC 65 nm CMOS process and the measurement results validate the claims made in this work.