A Gm-Boosting Technique for Millimeter-Wave Low-Noise Amplifiers in 28-nm Triple-Well Bulk CMOS Using Floating Resistor in Body Biasing

This paper presents a simple yet effective $G_{m}$ -boosting technique for improving gain and noise performance of millimeter-wave (mm-wave) low-noise amplifiers (LNAs) comprising triple-well transistors typically found in the modern bulk CMOS processes. The proposed technique uses a resistor that connects the p-well and deep n-well terminals of the triple-well transistor, leaving the terminals floating instead of conventionally connecting them to the ground and supply voltage. This arrangement exploits a leakage current through a diode formed between the drain/source and p-well of each transistor, thus autonomously setting its bulk potential for increased transconductance, while ensuring its robustness to the process variation. The improved isolation between the p-well and the substrate further improves the gain and noise performance. We provide a theoretical analysis of this floating resistor-based body biasing method and support it with simulation results. For experimental validation, a two-stage cascode LNA was designed and fabricated in 28-nm bulk CMOS. The measurement results show that 3.3–4dB noise figure (NF) and 19.1–16.1dB gain are achieved at 24.7–29.5GHz. To ensure a fair comparison, another identical LNA with the normally expected triple-well biasing was also fabricated. The proposed method reveals a 0.6dB improvement in minimum NF and an additional ~3.5dB gain without any significant linearity degradation.


I. INTRODUCTION
T O meet the demand for higher data rates and larger system capacities of wireless communications, the fifth generation (5G) systems are moving towards millimeter-wave (mm-wave) frequencies [1]. As carrier frequencies increase, it becomes more difficult to maintain the noise performance Manuscript  of a low noise amplifier (LNA), which is the key receiver block, as the minimum noise figure (NF) of a single MOS device is proportional to its operating frequency [2]. Different noise cancellation techniques have been proposed in the literature to reduce NF. Among them, the differential topology has been widely adopted as it can eliminate the effects of common-mode noise sources and provide better isolation to the noise coupling from the supply [3], [4], [5]. However, that approach requires a balun to convert a single-ended signal to a differential signal, but baluns tend to occupy a considerably large area compared to active devices. Yet another technique is based on boosting the equivalent transconductance of the circuit (G m ) [6], [7], [8], [9], [10]. G m -boosting can be achieved by using three different schemes. First, an auxiliary amplifier is inserted between the source and gate of the common-gate transistor to apply a negative voltage gain to the gate. However, the auxiliary amplifier causes additional dc power and noise, especially at mm-wave frequencies. Therefore, instead of using an auxiliary amplifier, passive devices, such as capacitors or transformers, can be adopted [6]. Using a pair of cross-coupled capacitors is another option but it is only possible in a differential topology [9]. The third scheme is based on magnetic coupling using a transformer [10]. Just as baluns, however, transformers are also area-inefficient. Alongside the conventional approaches, some new noise canceling techniques have also been proposed [11], [12]. While these technique can be very effective at RF frequencies, their performance is limited by the degraded quality factor of the lumped components at mm-wave.
Recently, there has been a growing interest in exploiting triple-well transistor structures of bulk CMOS for performance improvements in a variety of applications. For instance, a selfbiasing arrangement was introduced in [13], where the p-well is connected to the transistor's gate to increase the capacitance density of the pumping capacitor with the beneficial use of the parasitic capacitance for a dc-dc converter. Furthermore, [14] employs a dynamic body biasing to improve performance of a power amplifier. In [15] and [16], a large resistor was added between the bulk and substrate (ground) nodes to improve the This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ isolation. That method aimed to increase the maximum gain of the transistor at high frequencies without boosting G m .
In this paper, we propose a new G m -boosting technique for a mm-wave cascode LNA, leveraging characteristics of triple-well bulk transistors by introducing a resistor between the p-well and deep n-well (DNW) terminals and leaving them floating instead of customarily tying them to ground or supply. Compared to other classical body-biasing approaches [14], [17], [18], this technique provides an autonomous body biasing with the leakage diode current between drain/source and the p-well, resulting in an improved G m . In addition, it offers a large impedance between the p-well and the substrate, which improves the isolation across the chip. In this regard, [15] and [16] also aim particularly to have high isolation between these two nodes, however, these works do not include G m -boosting for further performance improvement. Moreover, unlike the conventional methods discussed in [3], [4], [5], [6], [7], [8], [9], and [10], the proposed technique does not require an additional chip area. Furthermore, contrary to the solutions in [11] and [12], it is not affected by the degraded quality factor of the lumped components at mm-wave. In fact, even better gain and noise performance can be achieved with increasing frequency. As a proof-of-concept, a two-stage cascode LNA using the proposed technique and another LNA with the same structure but using the conventional triple-well biasing were implemented in TSMC 28-nm LP CMOS technology for fair comparison. The measurement results show that the proposed technique achieves a 0.6 dB improvement in the minimum NF and approximately 3.5 dB additional gain at an extra cost of ∼5 mW in power consumption, from 20.3 mW to 25.5 mW, while maintaining its linearity performance between 24.7-29.5 GHz.
The rest of the paper is organized as follows. In Section II, the analysis of the proposed floating resistor technique is applied in a cascode structure to compare its effectiveness for G m -boosting. Section III details the circuit implementation and optimization techniques for mm-wave amplifiers. The measurement results are shown in Section IV and conclusions are drawn in Section V.

II. PROPOSED G m -BOOSTING TECHNIQUE USING A FLOATING RESISTOR
This section presents a detailed explanation of the concept of G m -boosting using a floating resistor in the body biasing. First, it will be shown how this method leads to an increase in transconductance of a single transistor. Then, the application of this technique in a cascode structure will be explored by providing the gain and noise analysis of both the conventional biasing of triple-well bulk CMOS transistors and the proposed scheme using a floating resistor.

A. G m Boosting With Floating Resistor
Transconductance g m of a single transistor can be represented as [19]: where μ n denotes the electron mobility, and C ox represents the gate oxide capacitance per unit area. W and L are the width and length of the transistor, respectively. Threshold voltage V th can be calculated from φ MS + 2φ F + Q dep /C ox , where φ MS defines the difference between the work functions of polysilicon gate and silicon substrate, while φ F and Q dep represent the substrate doping effect and the charge in the depletion region, respectively. As governed by (1), g m can only be readily controlled at run-time by V gs or V th . Fig. 1(a) and (b) show the cross-section diagrams of a triple-well NMOS transistor structure with the conventional and proposed biasing techniques. Conventionally, the p-well is connected to ground (V B = 0) so as to avoid the body effect, i.e. the back-gate effect, as shown in Fig. 1(a). Fig. 2 indicates the effect of the back-gate biasing on the transistor's V th and on its leakage diode current between the source and p-well (i SB ). Here, the back gate voltage V B is applied to node B, while DNW is connected to V DD . Normally, a non-positive V B should be used to prevent the diode from  turning on and thus a possible device break-down. However, in some applications, positive V B up to the diode's turn-on voltage can also be applied [14]. As an alternative approach, in the proposed technique shown in Fig. 1(b), the p-well and DNW are connected via a high-valued resistor R float and left floating rather than connected to ground or voltage source. This configuration can effectively increase the voltage at the two nodes due to diode leakage, resulting in a reduction of φ MS and hence a decrease in V th . Consequently, g m of the transistor will be increased.
Compared to other conventional body biasing approaches in [17], [18], and [14], our proposed technique, that take advantage of the leakage diode currents between the drain/source and the p-well, provides a dynamic body biasing to the transistors by autonomously establishing V B as 0.2 V without any additional chip area or control circuitry. Furthermore, the fact that the p-well and DNW are connected through R float , it ensures that the diode between these two wells is always OFF since the voltage at DNW also settles at 0.2 V. It is worth mentioning that to achieve the same performance with the conventional back-gate biasing, approximately 0.5 V must be applied to node B. That is not practical, since it is very close to the diode turn-on voltage.  conventional biasing, while the structure of the proposed floating resistor biasing is shown in Fig. 3 Fig. 4 presents a small-signal equivalent circuit for the cascode structure, including the noise sources, where Z eq represents the equivalent impedance seen at the drain of the CS transistor including all parasitics, and Z eq2 = Z eq ||C gd is at the drain of the CG transistor. The derivation of Z eq can be found in Appendix. To analyze the voltage gain of the cascode amplifier for the cases with the proposed floating resistor ("float") and the conventional biasing ("conv"), the voltage noise source in Fig. 4 can be short-circuited whereas the current noise sources can be open-circuited while applying the Kirchoff's Current Law (KCL) to the simplified circuit. For the sake of simplicity, it is assumed that lim R float →∞ , g m r o 1, (g m + g mb ) r o 1, C db ≈ C sb and C gd ≈ C gs . The derived voltage gain equations include all the parasitics; hence, they are too long. By further simplification, the following equations can be obtained for the voltage gain of the two cases:

B. Analysis of Cascode Transistor Case
where   (2) and (4), they do not reflect well the parasitics at lower frequencies that are of less interest in this work.
To verify these simplified equations, Fig. 5 compares them with circuit-level simulations. As evident, the proposed technique provides a slightly lower gain than in the conventional case at lower carrier frequencies, but at higher frequencies it consistently offers a significant improvement. This analysis confirms that the gain advantage becomes more distinct at frequencies beyond 20 GHz. To evaluate the maximum available gain advantage, the ratio between the voltage gain equation of the case with the floating resistor, A v,float , and that of the reference case with the conventional biasing, A v,conv , is investigated as (lim ω→∞ ): where In case where there is no G m -boosting, i.e. g m,float =g m,conv and g mb,float =g mb,conv , (6) can be simplified to where G = 3 (R n + R sub ) 2C gd +C db +C db R n R sub g mb,conv .
As seen from (8), in the absence of G m -boosting, the proposed technique still provides a gain improvement due to the improved isolation between the p-well and the substrate. However, the increased G m introduced by the proposed method further increases the available gain.
To examine the noise of the cascode under a narrow-band condition, the noise factor with respect to R s for the simplified circuit shown in Fig. 4 can be derived as where s,n describes the source-resistance noise, while I 2 d,n is the channel thermal noise and Z 1 denotes the impedance seen at the upper terminal of the noise source of I 2 d1,n shown in Fig. 4. Note that the impact of the cascode transistor on the noise factor is ignored, since the noise power contribution of the cascode transistor should be divided by the square of the voltage gain of the input transistor, which eventually becomes negligible in deep-submicron CMOS [20]. Similar to the gain analysis, separate equations for noise factor of both cases that include all parasitics can be derived and further simplified by assuming that lim R float →∞ , g m r o 1, (g m + g mb ) r o 1, C db ≈ C sb and C gd ≈ C gs as follows   (11) and (13), they do not reflect well the parasitics at lower frequencies that are of less interest in this work.
Likewise, to validate the simplified noise equations, Fig. 6 compares the simulated and calculated NFs of the cascode amplifier for the two biasing cases. As revealed in Fig. 6, both have similar NFs at lower frequencies. However, at mmwave frequencies, the proposed technique consistently offers a greater advantage in noise performance.

III. CIRCUIT DESCRIPTION
In this section, the circuit implementation of the LNA is discussed in detail. Apart from the impedance matching networks, there are mainly three important parameters that need to be carefully set for this design: the transistor size, its multiplier setting, and the value of the floating resistor R float between the DNW and p-well.

A. Device Size Selection
To find the optimal transistor size, a suite of simulations were conducted in Cadence for a triple-well transistor. Fig. 7(a) shows the schematic and the expected minimum NF for different transistor sizes across the frequency. Likewise, subplot (b) depicts the available gain, G A , for different transistor sizes. As expected, G A increases with the transistor width. However, this is not the case for the minimum NF. Even for the same transistor width, different combinations of finger width and number of fingers can lead to a different minimum NF. This is mainly due to the parasitic capacitors, the effects of which are more pronounced at higher frequencies. The minimum NF of a single-stage transistor in the common-source configuration should be as follows [21]: where, ω T = g m /(C gs +C gd ) defines the unity-gain frequency, γ is a bias-dependent factor and δ denotes the induced gate noise coefficient, while c represents the correlation coefficient between the gate noise and drain noise. Even though the overall transistor width can be identically constrained for different finger widths and the number of finger pairs, it may result in different C gs and C gd due to the additional parasitic capacitors. As implied by (15), the variance in C gs or C gd can directly  affect the minimum NF. According to the simulation results in Fig. 7, W = 20.8 μm (0.8μm×26) provides the lowest NF min with an acceptable available gain. However, if the transistor width is increased to 38.4 μm (1.2μm×32), the available gain can be increased significantly with a slight increase in the minimum NF. As a result, W = 38.4 μm (1.2μm×32) was chosen in this design.  between the unit transistors. In this regard, [22] states that more multi-finger devices connected in parallel would provide a lower noise level up to 30 GHz than would a single device. However, as seen in Fig. 8, this improvement in NF cannot be firmly observed after 30 GHz when the multiplier is increased from 2 to 3. This slight improvement will disappear altogether when the additional parasitics from the layout are taken into consideration. Furthermore, at higher frequencies, the available gains for the multiplier values of 2 and 3 are nearly the same. Thus, the multiplier of each transistor was set to 2 in this design. The layout of one of the transistor sets used in the design is presented in Fig. 9. For the connection of the DNW and p-well terminals of the transistors, the lowest available metals were used to provide the additional resistance, since the conductivity of the lower level metals is very small.

C. Resistor Value Selection
As stated earlier, the proposed technique in this paper introduces a resistor, R float , connected between the p-well and the DNW terminals of a triple-well transistor, leaving them floating instead of conventionally connecting them to the ground and V DD , respectively. To find the optimum resistance of R float , the NF and the available gain of the designed cascode, including the layout related parasitics, at 28 GHz were simulated across R float , as shown in Fig. 10. At this point, it should be clarified that R float = 0 in Fig. 10 does not refer to the conventional biasing method where there is no R float resistor at all. This particular configuration of R float = 0 defines a short circuit between the p-well and the DNW. The simulations reveal that both the gain and noise performance do not change much after the resistance value exceeds 10 k . A higher resistance can be beneficial for an ESD protection, but considering the area limitation, R float was set to 18 k .

D. Complete LNA Design
After determining the optimal values of the transistor widths and R float , the cascode design was completed. The LNA with the proposed biasing technique consists of 2 consecutive cascode designs as discussed earlier. Different from the second stage, the first stage has an additional inductor connected to the source of the cascode structure to improve the linearity of the design. The two stages are connected via a decoupling capacitor, which also functions as a part of the  inter-stage matching network. In the final cascode design, an additional capacitor is connected to the gate of the CG transistor rather than providing a RF short to allow for a voltage swing on the gate proportional to the swing of the corresponding source. Fig. 11 illustrates the detailed schematic of the proposed two-stage cascode amplifier. An almost identical copy was also fabricated as a reference, but with the conventional biasing of the p-well and DNW instead of the floating resistor R float between them, as contrasted in Fig. 1(a) and Fig. 1(b).

E. Process Variation Effect
To investigate the effect of process variation on noise and gain performance of the proposed LNA, simulations were  performed at different process corners. Fig. 12 shows the simulated |S 21 | and NF at 28 GHz for the cases with the floating resistor and the conventional well biasing at different process corners. As evident, the proposed design exhibits a much better robustness to process variations, in addition to improved noise and gain performance, thanks to the autonomous body biasing that changes the bulk voltage with the process variation, as can be seen in Table II.

IV. MEASUREMENT RESULTS
The proposed mm-wave LNA was fabricated in TSMC 28-nm LP CMOS process. Its chip micrograph is shown in Fig. 13. The reference case with the conventional well biasing was also fabricated for fair assessment of the performance improvements. The chips were measured using a Cascade Microtech Summit 9000 Analytical Probe Station and MPI T40A GSG-100 wafer probes. The design with the floating resistor consumes 25.5 mW power from a 1.2 V voltage supply, whereas the reference chip consumes 20.3 mW from the same voltage supply.

A. Small-Signal Measurement
S-parameters were measured with Agilent E8361A PNA, which was directly connected to the probes. On-wafer calibration was done with a AC-2 calibration substrate. Fig. 14 and Fig. 15 present a comparison between the measured and simulated S-parameters, while Fig. 16 compares the measured S 21 . Based on these results, the LNA with the floating resistor can achieve a 19.1 dB maximum gain at 26.5 GHz while the reference LNA with the conventional well biasing can merely achieve a 15.5 dB maximum gain at the same frequency, thus offering a ∼3.5 dB improvement in the maximum gain. Furthermore, the advantage in the gain becomes greater as the frequency increases. Moreover, the 3 dB bandwidth of the case with the floating resistor is 24.7-29.5 GHz while for the conventional biasing case it is 24.3-29.7 GHz.  Regarding the return loss, the floating-resistor biasing and the conventional biasing outperform 10 dB between 24.4-28.55 GHz and 24.3-28.45 GHz, respectively. Consequently, the use of the proposed method does not significantly affect the 3-dB and matching bandwidths.

B. Noise Measurement
The NF of the fabricated chips were measured with a Y-factor method using R&S FSW50 spectrum analyzer and Keysight 346CK01 noise source. To reduce the measurement error, an additional LNA (HMC1040LP3CE) was used as a pre-amplifier before the spectrum analyzer. The measured and simulated NF can be found in Fig. 17. The minimum noise figure is 3.3 dB at 25.4 GHz and 3.9 dB at 25.3 GHz for the case with the floating resistor and the conventional biasing case, respectively. Thus, the proposed technique improves the NF by ∼0.6 dB.

C. Linearity Measurement
For the input-referred 1-dB compression point (iP 1dB ), the measurements were performed with the power sweep function of the Agilent E8361A PNA at 28 GHz. Fig. 18 shows the measured output power level and gain of the cases with the floating resistor and the conventional biasing at different input power levels. As plotted in this figure, at 28 GHz, iP 1dB was measured at −8.7 dBm and −9.2 dBm for LNA with the floating resistor and the reference LNA, respectively.
To characterize the LNA linearity, the input-referred thirdorder intercept point (IIP 3 ) was measured by applying two-tone signals with 100 MHz spacing at 28 GHz center frequency. The measured IIP 3 is −14.7 dBm for the implemented LNA with the floating resistor, whereas it is −14.2 dBm for the reference LNA with conventional biasing. The measurement results show that iP 1dB and IIP 3 exhibit a similar trend for both chips. Thus, it can be observed that the proposed technique does not affect the linearity of the design. Table III summarizes the performance of the proposed and reference LNAs and compares them with state-of-theart publications. The proposed technique offers approximately 3.5 dB improvement in the maximum gain. Although [18], [24], and [28] can offer a higher gain than the proposed design, they are in FDSOI CMOS and in III-V semiconductor technologies, which inherently yield better gain and noise performance compared to those in bulk CMOS. Similar reasoning applies to [24] and [18] for the NF performance. Thanks to the 0.6 dB improvement in the minimum NF, the proposed design achieves the lowest NF among the single-ended, 2-stage cascode LNAs in bulk CMOS, though the power consumption is increased by 5.2 mW, from 20.3 mW to 25.5 mW, which is due to the increase of the transconductance, G m . Furthermore, it should be noted that the techniques introduced in [21], [24], [28], and [31] can be applied to the proposed design for bandwidth extension.

V. CONCLUSION
In this paper, a new G m -boosting technique is presented for improving the noise and gain performance of a mm-wave  III   PERFORMANCE COMPARISON OF THE FABRICATED LNAS WITH THE STATE-OF-THE-ART LNA. It introduces a dynamic body biasing of transistors in the triple-well device structures in bulk CMOS. To prove the efficacy, two nearly identical LNAs, one with the proposed floating resistor and the other with the conventional biasing, were designed and fabricated in TSMC 28-nm LP CMOS. The proposed LNA is more robust to process variation than the reference LNA, thanks to autonomous body-biasing which changes the bulk voltage with the process variation. The comparison of the measurement results, supported by the simulations and derived equations, indicates that the proposed technique provides an improvement in minimum NF and additional gain without obvious change in linearity.

APPENDIX THE EQUIVALENT IMPEDANCE
The equivalent impedances, Z eq , for the cases with the floating resistor (float) and with the conventional biasing (conv) can be derived as: where ⎧ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎨ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎩ X = j ωC db − ω 2 C sub C db R eq + R sub − ω 2 C n−well C db R eq − j ω 3 C n−well C sub C db R eq R sub Y = j ω (C sub + C sb ) − ω 2 C sb C sub R eq + R sub − ω 2 C n−well C sb R eq − ω 2 C n−well C sub R eq − j ω 3 C n−well C sb C sub R eq R sub (A.17) and ⎧ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎨ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎩ Q = j ωC db − ω 2 C sub C db (R n−well + R sub ) − ω 2 C n−well C db R n−well − j ω 3 C n−well C sub C db R n−well R sub Z = j ω (C sub + C sb ) − ω 2 C sb C sub (R n−well + R sub ) − ω 2 C n−well C sub (R n−well + R sub ) − ω 2 C n−well C sb R n−well − j ω 3 C n−well C sb C sub R n−well R sub R eq = R float + R n−well (A. 18)