A High Step-Up Cost Effective DC-to-DC Topology Based on Three-Winding Coupled-Inductor

Owing to the low voltage level that renewable energy sources like solar panels frequently provide, and limited capability of simple boost converter, need for high gain step-up dc-to-dc converters are increased. In this article a single switch high step-up dc-to-dc topology with high efficiency is developed. To obtain high voltage gain, the described step-up dc-to-dc topology employs three windings coupled inductor and voltage multiplier cell method. To get the high voltage gain, this innovative converter does not require to work at a high duty cycle state by increasing the turns ratio of the coupled inductor. The suggested converter's working modes and theoretical model are investigated, and finally, a prototype setup is used to verify the theoretical and simulation analyses' correctness.


I. INTRODUCTION
P HOTOVOLTAIC (PV) based renewable energy generation share is quickly growing, with an annual growth rate of approximately 55 GW predicted in 2018 [1]. In the creation of microgrids, and optimal utilization of electricity supplied by series linked PV modules, need for a voltage boost of up to 320-400 V for the dc microgrid level interfaces is crucial [2]. As stated in [3] and [4], this degree of voltage boost is accomplished by connecting boost converters in a cascading configuration. For low duty ratio operating of main switches, two cascade-connected topologies produce quadratic boost with such a gain restriction. Numerous switching devices can also add to the complexity of the converter's design and control. Chen et al. [5] proposed a single-MOSFET quadratic boost converter with two-stage amplifying capabilities to decrease the number of transistors. Likewise, Habibi et al. [6] proposed a quadratic boost topology with a single resonant network and soft-switching capabilities. Divya Navamani et al. [7]  gain factor changes due to duty ratios operating and switching network combinations. Hu et al. [8] described a thorough design of a cascaded dc-dc topology for PV applications, including efficiency optimization. Abbasian et al. [9] presented a singleswitch high-gain dc-dc converter based on a voltage multiplier cell (VMC) with the additional benefit of low voltage stresses on components. A series of high-gain boost converters that employ a clamped mode coupled inductor (CI) for high gain and efficiencies is introduced in [10]. Switched capacitor-based boost topologies are another versatile class of high gain dc-to-dc converters [11], [12]. This method can increase voltage gain at a moderate duty cycle without employing magnetic elements. The downsides of this approach include inrush current at startup and capacitor susceptibility to equivalent series resistance (ESR). A new topology with switched capacitor circuits is presented in [11] to raise the voltage level up to 10 times based on the conventional configuration.
Compared to the typical boost converter, switched inductorbased boost converters are also another effective approach for achieving high voltage gain [13]. The minimal input current rippling is one of the benefits of this class of converters. Furthermore, Zhang et al. [26], Hasanpour et al. [27], and Farsijani et al. [28] introduced different kinds of single-MOSFET step-up topologies with regeneration passive clamp circuit. The primary power MOSFET in such converters is operated under ZCS conditions and low voltage stress. Furthermore, the CI's leakage inductor aids in the resolution of the diode's reverse recovery issue. But, the topologies stated cannot provide a broad range of voltage gain are expensive due to the huge number of components used.
Under ZCS conditions, the power switches in [24] and [25] turn ON. In addition, the reverse recovery issue with power diodes has been solved. To produce high voltage-gain, these designs use a mix of CI and VMCs. But such converters have an excessive number of components, as well as a significant cost and complexity. Furthermore, the leakage inductances of the CIs and high-frequency transformers create spike turn-OFF losses in such configurations. The power MOSFETs in [29] are soft-switched ON and the diodes are operated with zero currents, that avoids the reverse recovery concerns. The amount of power MOSFETs and voltage stresses across the voltage multiplier capacitors were noted to be excessive in [28].
A new development for a cost effective nonisolated high step-up dc-to-dc topology based on the voltage multiplier cell This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ method and CI is given in this article. The main advantages of this converter are as follows.
1) The power MOSFET and diodes operate in ZCS condition. So, the reverse recovery of the diodes is resolved. 2) Using the three degrees of freedom, the voltage gain can be adjusted. (N 2 , N 3 , and D). 3) Low voltage stress on main switch and output diode. 4) Despite the small number of converter parts, the voltage gain of the prototype converter is equal to 10.5 when duty cycle value is around 0.5. 5) Due to the low voltage stress of the power switch, we can use a low price low R DS switch. 6) Considering the number of converter parts and voltage stress on the semiconductors, this converter can be found to be optimal in terms of total price. This kind of high gain dc-dc converter is essential in several emerging applications such as: Dc microgrid application, LED lightning, automobile headlight, robotics and PV systems.
The high gain dc-dc converters are of interest specially in renewable energy systems (RES) integration since these emerging technologies are crucial to address recent energy crises in EU and worldwide. In this regard, PV systems are one the most extensively utilized RES type. The dc input of a PV cell, modules, strings, or array, varies from sub-1 V to 1500 V, must be converted to an intermediate dc voltage by a dc-dc converter(s) for providing stable dc power for grid integration in a PV system. As a result, the dc-dc conversion plays important role in the overall operation of the PV system, including efficiency and reliability, among other elements.
The rest of this article is organized as follows. Section II evaluates the proposed structure operation concept as well as steady-state analyses in continuous conduction mode (CCM). The suggested converter's design principles and voltage stress of components are provided in Section III. In Section IV, the presented converter is compared to different similar designs. The experimental measurement outcomes of a laboratory prototype of the suggested topology are shown in Section V. Finally, Section VI concludes this article.

II. CONVERTER: OPERATION PRINCIPLES
The equivalent power circuit of the described high step-up voltage gain single MOSFET dc-to-dc topology based on CI and VMC with low input current ripple is shown in Fig. 1.
As seen in Fig. 1, an active power switch S, one three-windings CI, three capacitors C 1 -C 3 , three diodes D 1 -D 3 , an output filter capacitor C O , and an output diode D O are included in the proposed construction. One power switch is a benefit for the converter in the suggested topology's construction. The CI's turns ratio n 2 is equivalent to N 2 /N 1 , and n 3 is equivalent to N 3 /N 1 , wherein N 1 , N 2 , and N 3 are the inductor's winding turns. Fig. 2 depicts the various modes of operation. Fig. 3 shows the steady-state waveform of the proposed converter operated in CCM.

A. Mode 1
At t 0 , the active power MOSFETS is turned ON throughout this period. All of diodes stayed on their pervious mode due to the leakage inductance (L lk ). In this mode, the active power MOSFET turns ON very softly and has a soft switching operation due to the presence of leakage inductance. Fig. 2(a) depicts the current flow direction. By using Kirchhoff's voltage law in this mode, the following equations can be obtained: B. Mode 2 The active power switch S is still turned ON during this time period. The energy of leakage inductance (L lk ) is getting empty and D 1 and D 3 are forward biased diodes, whereas D 2 and D o are reverse biased diodes. Fig. 2(b) depicts the current flow direction of this mode. The magnetizing inductor L m and the leakage inductor L lk continue to charge from the power supply V in , and the currents through all these inductors increase linearly. In this mode, the capacitor C 3 is charging and reaching its final voltage. In this mode, because the D 1 and the second winding are placed in series, the diode turns ON softly. By using Kirchhoff's voltage law in this mode, the voltage of capacitors C 1 , C 3 and voltage of secondary and tertiary windings can be obtained

C. Mode 3
This time interval starts at t 2 when the MOSFET is turned OFF. The stored energy in CI's charges capacitor C 2 via diode D 2 . This mode ends when diode D 2 is reverse biased. By using Kirchhoff's voltage law in this interval, the voltage of magnetizing inductance and voltage of secondary and tertiary windings can be obtained D. Mode 4 The active power switch S is still turned off during this time interval. All diodes are reverse biased, whereas D o is forward biased diode. when the MOSFET is OFF, all parts of capacitors C 1 , C 3 and first, tertiary windings are placed in series together, increasing the output voltage gain. The voltage of output capacitor C O can be calculated as follows:

A. Voltage Gain Calculation
By substituting (1) in (5) and (6) these equations are obtained By substituting (11) into (3) V C1 can be obtained By utilizing the volt-second equilibrium axiom for magnetic inductor (L m ) ((1) and (7)) and by according to (13) V C2 is found as By substituting (12), (13), and (14) into (4) According to (13) and (14) in (7) V D Lm can be calculated By substituting (1) in (8) and (9) these equations are obtained By substituting (14), (15), and (18) into (10) the nominal gain of suggested topology can be found As just a result, if the CI leakage inductance is ignored, the coupling parameter k is close to unity and the recommended converter ideal voltage gain is as follows: Fig. 4 depicts a curve of voltage gain M vs turns ratio and duty ratio D. This demonstrates that the turns ratio has a considerable effect on step-up voltage gain. Furthermore, the high voltage gain would be obtained in the suggested topology without the use of an excessive duty ratio or a large turns ratio. It should be noted that in this image, some parameters have been omitted due to their small size and effects, such as winding resistance. The voltage drop due to the coupled-inductor in this topology is extremely low due to the resistance and current flowing through it. By considering these parameters in practice, the voltage gain will be slightly reduced, an example of which will be shown in Section V (see Fig. 13).

B. Voltage Stress of Semiconductors
The voltage stress of the power MOSFET and diodes for the recommended 3Windings CI design must be evaluated in order to make the appropriate selection. The voltage stress on diode D 2 is equal to the power MOSFETs, and the voltage stress on diode D O is equal to diode D 1 . A 3Windings CI converter's voltage stresses are computed, as shown in (21)- (23). By using (13), (14) the voltage stress on the MOSFET and diode D 2 can be obtained By using (20), (14) the voltage stress on the diodes D 3 , D O and by using (14), (16), (17) the voltage stress on the diode D 1 can be obtained It is observed that (21)-(23) are dependent on the turn ratios of CI. Therefore, we can choose the parts cheaper with lower voltage stress based on the turn ratios of the CI.

C. Current Stress of the Components
The incredibly small-time intervals are disregarded to ease the process. As the magnetizing inductor L M is sufficiently large, the magnetizing current is considered as a fixed. So, by using the Kirchhoff's current law, the following equations can be obtained:

D. Efficiency Estimation
To correctly judge the converter's effectiveness, it is preferable to study the converter losses by computing the converter efficiency around its nominal power (at 200 W). In general, the converter losses can be divided into four groups.
1) Switch Losses: Switch losses are classified as switching losses and ohmic losses. Because the converter switches softly when the switch is turned ON, its switching losses only comprise losses when the MOSFET is switched OFF. The following equation is required to compute ohmic losses and switching losses: 2) Diode Losses: For the scenario of diodes, the ohmic losses and reverse recovery losses of the diodes are ignored in this topology due to use Schottky diodes, and the major losses of the diodes are due to the voltage drops of the diodes in their average currents. As a result, the relevant equation can also be assumed Due to small amount of r D , it is not considered.

3) Capacitor Ohmic Loss:
In order to obtain the internal resistance loss of capacitors, the following equation can be considered: The rest of capacitors have a small ESR due to their material (MKT).

4) Coupled Inductor Losses:
The core loss of the CI (P loss(core) ) can be calculated using the datasheet parameters. Moreover, the CI's other loss can be obtained as follows: P total core = P loss (core) + P loss(ohmic).
The efficiency of topology can be derived using the equation of losses from past parts as follows: Under full load, the converter's efficiency can theoretically reach 97.44%.

1) Capacitors Design:
The following equations are used to calculate the size of capacitors by assuming 4% voltage ripple for C 1 , C 2 , C 3, and 0.1% voltage ripple for C O assumed capacitors average current equal to I O The peak-to-peak ripple of the output capacitor (and other capacitors in the converter circuit) is suggested to be kept under 5% [27]. In this article, we have tried to design the converter by compromising the performance and cost factors.
2) Coupled Inductor Magnetizing Inductance Design (L m ): By assuming 50% current ripple, the amount of the magnetic inductance is obtained from the following equation: Voltage gain, normalized voltage stress of the main MOSFET and output diode are showed in Fig. 5(a)-(c), respectively.

B. Comparison With Two-Windings Converters
In this section, in order to compare the proposed converter with two-windings converters, three comparisons have been made. In these comparisons, it is assumed that the proposed converter has a ratio of (1:0:2, n 2 ≈ 0 (The windings of secondary is very, very low, and negligible), n 3 = 2), and the turns ratio of the two windings converters is 1:2. Fig. 7(a) displays voltage gain comparison outcomes of recommended topology and topologies described in [19], [20], [21], [22], and [23]. The voltage gain of suggested converter is high and appropriate especially in lower duty cycle values. As shown in Fig. 7(b), the normalized voltage stress across the MOSFET in the given topology is smaller than in the other two windings topologies for most values of duty amount. As shown in Fig. 7(c), the normalized voltage stress over the output diode in the suggested topology is smaller than configurations [23], [19], [20], [21].

V. EXPERIMENTAL RESULTS
The laboratory prototype has been designed and implemented in order to verify the performance and practicality of the dc-dc converter combination that have been discussed in this article. Fig. 8(a) shows a picture of the experimental setup and the power circuit that was constructed and Table II shows the details of its components. In all experimental results, the output power of the converter is 200 W, and the LA200-P current sensor is used to measure the current.
Experimental waveforms of the elements illustrated in Fig. 9. The gate pulse with 50% duty cycle is depicted in Fig. 9(a). Fig. 9(b) shows the voltage and current waveforms of the main power MOSFETs. It is important to note that the turning-ON loss of the MOSFET is very low due to its ZCS operation.
The voltage across the power MOSFETs is measured to be 40 V, which confirms (21). The voltage and current waveform of diode D 1 is shown in Fig. 9(c). The voltage across the diode is measured to be 80 V, confirming (22). The voltage and current  (21) and (23).
The diodes have a ZCS operation. Fig. 9(g) and (h) indicates the current and voltage from the tertiary side and primary inductance of the CI, accordingly. Fig. 9(i) depicts the experimental waveforms of output load acquired from the prototype suggested topology working at full load.
The distribution of different losses resulting in the proposed high-gain topology under nominal-load conditions is depicted in Fig. 10(a). The efficiency values achieved while calculating and testing with the prototype at different output power range are shown in Fig. 10(b). The calculated results are quite near to the practical ones. It is important to note that the output voltage of these converters is not equal to each other and is equal to its values in Table I.
Furthermore, the purpose of Fig. 10(b) is to show that the proposed converter with the used components (power switches, coupled-inductors, and diodes) has an appropriate efficiency compared to the topologies available in the state of art with their special components. Moreover, by using newest components such as using SiC switches with lower R DS , we may expect better efficiency from the proposed converter which needs to be investigated.
In order to have a more detailed look at the soft switching operation in this converter, the conducting current and breaking voltage on switch S is presented in Fig. 11. It can be seen that the active power MOSFET turns ON very softly due to the presence of leakage inductance (see the Mode 1 of converter operation) It is important to note that, by using the snubber correctly in the proposed converter, the maximum amplitude voltage on components (switch or diodes) can be reduced. Fig. 12(a) and (b) shows the voltage and current of the switch and the voltage and current of the diode, respectively, after applying the snubber.
To evaluate the correctness of the generated ideal voltage-gain and compare it to actual voltage gain, nominal, and experimental prototype output voltages are shown in Fig. 13.   [14], [15], [16], [17], [18]. (Note: This figure is case sensitive and based on the results presented in the referred research papers knowing that the components used in those converters are not the same. Therefore, considering the same components in the practical structure, some curves may be slightly different).

VI. CONCLUSION
A design based on a CI with three windings for a nonisolated, high gain, single switch dc-to-dc converter was presented in this article. High voltage gain is accomplished in the proposed design by utilizing a 3Windings CI and voltage multiplier cell. By increasing the CI turn ratio, the voltage conversion ratio of the given topology is enhanced. Because the voltage stress on the main MOSFET is minimal, a power MOSFET with a lower ONstate resistance could be chosen. The behavior of the converter and steady-state evaluation in CCM were explicitly explained. As a final demonstration of the converters' abilities to operate, experimental measurement results were provided. It should be noted that the performance of this converter is preferred in CCM and if it needs to be used in discontinuous mode, the voltage gain and some other equations will be different.
The main advantages of the proposed structure over the conventional boost converter are as follows.
1) Soft switching operation for main switch and diodes.
2) Higher voltage gains especially in lower duty cycle values.
3) Greater degree of freedom to design and increase voltage gain (turn ratios n 2 , n 3 and duty cycle). 4) Lower normalized voltage stress on the main switch. This topology can find its application in several emerging technologies such as in Solar Home Systems for rural/urban environments or to supply high intensity discharge lamp used in automobile head lamps or dc microgrid application or traffic lights or other low-cost systems. If the output power has a significant drop (lower than %15 of nominal output power), the soft switching performance of the converter will be compromised and the efficiency will decrease from our desired level.