A Closed-Form Mathematical Model and Method for Fast Fault Location on a Low Voltage DC Feeder Using Single-Ended Measurements

Fault location on a dc microgrid feeder needs to be extremely fast to protect the circuit breaker and converter-source components. This paper develops a seminal theoretical foundation for fast fault location on a dc feeder that uses only single-ended local measurements in time domain. The theory provides a closed-form deterministic solution for fault location, making the resulting fault location method agnostic to system-topology and immune to fault resistance. The theory is developed with ideal dc voltage sources, and extended to practical converter-sources. The performance of the resulting method is demonstrated by simulating a dc feeder with converters connected at both ends, modeled in PSCAD.

A S penetration of solar-photovoltaic (PV) and storage grows in distribution systems, the concept of dc microgrids is gaining traction due to lower conversion losses and the inherent ease of operation of dc systems [1]. However, for safe operation of any system, a faulted feeder must be quickly and selectively isolated, without having to shut down the whole system. This requires an accurate fault detection and location technique. For dc feeders the speed of fault location becomes critical, typically 10's of microseconds, due to the following reasons. 1) In response to a fault, current in dc circuits rises in a matter of tens of microseconds [2], without having a natural current zero. If the fault current crosses the breaking limit of the controlling circuit breaker, it can not be interrupted. 2) A dc microgrid is fed by dc-dc converters that interface renewable sources and ac-dc converters that connect the microgrid with the ac grid. These converters are made of power electronic devices such as diodes and IGBTs, and have capacitors connected at their dc side, known as dc link capacitors. When a fault occurs in a dc microgrid, current from these capacitors dominates at first. After the capacitor voltage drops to a critical value, a high fault current starts to flow through the power electronic devices [3], [4], exposing them to damage.
Due to the speed constraints a fault location scheme that avoids communication from the other end of the feeder to locate fault could be very useful. However, the biggest hurdle in locating fault on a feeder using only single-ended measurements is the presence of unknown fault resistance. As the literature survey presented now shows, a single-ended fault location method for a dc feeder fed from both ends that is immune to fault resistance has yet to be developed.
In [5], [6], the faulted section is isolated, but the location of fault on that section is not determined. Schemes in [3], [4] use iterative methods for determining fault location, but the VOLUME 9, 2022 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ execution time increased with increasing distance to the fault point and increasing value of fault resistance. In [7], a local measurement based fault location method is used for bolted faults only; for any other fault involving a resistance, authors had to use communication. An inductance based fault location method was proposed in [8], [9], but the method can only be applied if the system is radial, and the fault current is being sourced from one end only. However, a dc microgrid will certainly have multiple sources, and therefore a fault will be fed from both ends of the faulted feeder.
Some offline methods were also proposed for fault location to avoid communication, using a power probe unit (PPU) [10], [11] and a portable current injection kit (CIK) [12]. However, these offline techniques can be used only after the faulted section is isolated by some other means. Also, as PPU or CIK are only used in locating the fault, which adds extra cost to the system.
Traveling wave based methods were used in a number of papers for locating faults in HVDC systems [13]. However, a traveling wave based method is not practical for dc microgrids. Due to the complex topology of the distribution system, a large number of reflections take place, compromising the accuracy of the method [14]. Additionally, very short feederlengths, characteristic of dc microgrids, hamper the process of isolating traveling waves.
Machine learning (ML) based approaches are also tried for fault location in dc microgrid. For example, two different Artificial Neural Networks(ANNs) were used for fault location and fault detection in a 4 bus ring type dc microgrid in [15]. This method is system dependent, as any change in the network will require a new set of simulations to train the ANN again with new circuit parameters. It is also practically impossible to show the method performs well for every fault at any distance with any fault resistance. Moreover, lack of field data compromises the validity of such ML based approaches.
To overcome these drawbacks this paper develops a deterministic closed-form mathematical formulation that forms the foundation of a single-ended fault location method for a feeder fed from both ends that is immune to fault resistance. It can be implemented in both radial and meshed networks. The only constraint is that the data should be sampled at a high enough frequency for the current derivative to be calculated accurately. By properly adjusting the sampling frequency, high-resistance faults can also be located by this method. The fault is detected and located using only three fault-samples, which means that for a sampling frequency of 1 MHz (assumed in this paper), the time taken is just 3 µs. Since commercially available relays already use this sampling frequency [16], and oscilloscopes support even higher sampling frequencies [17], this assumption is reasonable. Since the formulation uses the total resistance and inductance of only the protected feeder, the resulting method becomes system-independent, i.e., any change in the operating parameters of the system or any topological change in the network will not impact the detection or location of fault by this method.
The rest of the paper is organized as follows. Section II presents the theoretical proof that forms the foundation of the proposed method with ideal dc voltage sources, Section III validates the theory with simulated data, Section IV shows how the method is applicable to a practical test feeder fed by converter-based sources, Section V shows how the method can be adapted for any value of fault resistance, Section VI includes sensitivity analysis of this method with respect to various parameters, and Section VII concludes the paper and describes future work. Fig. 1(a) shows a two-bus dc system with a dc feeder connected between Bus 1 and Bus 2. Two voltage sources with steady state values V 1 and V 2 are feeding the line from the two buses. At a distance x from Bus 1, a fault with a fault resistance R f is assumed. Current I 0 is flowing from Bus 1 to Bus 2 before the fault. Due to short lines in dc microgrids, line capacitance is ignored in Fig. 1, and the line is approximated with an inductance and a resistance only. Other circuit parameters used in the development of theory are as follows:

A. FAULT CURRENTS
• R 1 , L 1 = resistance and inductance, respectively, of linesection from Bus 1 to fault.
• R 2 , L 2 = resistance and inductance respectively, of linesection from Bus 2 to fault.
• R, L = total resistance and inductance of line.
• r, l = resistance and inductance per unit length of the line.
• τ L = L 1 R 1 = L 2 R 2 = time constant of the line. • i 1 = Current from Bus 1 to fault. • i 2 = Current from Bus 2 to fault. Fig. 1(b) shows the s domain equivalent of the circuit of Fig. 1(a). I 1 (s) and I 2 (s) denote the s domain equivalent of currents i 1 and i 2 , respectively, and will be denoted simply as I 1 and I 2 during derivation. Applying KVL to the circuit in Fig. 1 If (1) and (2) are solved for I 1 (s), I 2 (s) and subsequent inverse Laplace transforms are performed to get i 1 (t) and i 2 (t), the following expressions are obtained: where, Step-wise derivation is provided in Appendix A submitted with this paper.
If the instantaneous fault voltage during the fault is v f (t), with corresponding source voltage at the sending end in Fig. 1 Using the expression of i 2 (t) from (8) in (9) and reorganizing terms, (10) can be obtained.
If v 1 , i 1 , di 1 dt can be measured at two different times t 1 and t 2 , (11) and (12) can be formed.
From (11) and (12), the location of fault, x, can be expressed as: Notice that (13) provides a closed-form solution for fault location that does not include the fault resistance term R f . Samples of voltage and current at time t 1 and t 2 can be measured, and if the sampling rate is high enough (1 MHz assumed in this paper), current derivative di 1 /dt can also be accurately calculated. Thus, (13) can be used to find fault location x, regardless of the unknown fault resistance. This theoretical formulation is claimed to be the seminal contribution of this work. Three consecutive readings are needed, as two samples are needed to calculate di 1 /dt. This translates to a solution time of just 3µs.
When the fault current will start to settle down, i.e., . In that case, both equations will have the same information, and the solution will have the zero-determinant problem. So, it is important to use values during the transient state after a fault.

III. VALIDATION OF THE PROPOSED THEORY
To validate the theory developed in section II, the circuit depicted in Fig. 1(a) is simulated in PSCAD with a sampling frequency of 1 MHz, meaning the sampled values are 1 µs apart. Rated system voltage is chosen to be 400 V, as it has been used in a number of papers for dc microgrids [18]- [21]. A 100 m long Yorkshire conductor [22] is chosen for the feeder. Circuit parameters are: Fault resistance is taken as R f = 0.01 (low resistance) for this validation. Section V will show how the method can be extended to high-resistance faults.
Two faults are simulated at x (1) = 80 m and x (2) = 40 m distance from Bus 1. The fault inception time was set at t 0 = 0.1 s for both the cases. Currents from Bus 1 to fault (iBus1 sim ) for both cases are plotted in Fig. 2.
For x (1) = 80 m case, L However, since the fault in the circuit was simulated at t 0 = 0.1 s, i The calculated current using (14) is plotted in Fig. 2(a) as iBus1 calc . It is superimposed on the simulated current. Similarly, simulated and calculated currents for fault at x (2) = 40 m are plotted in Fig. 2(b), which are also superimposed. This validates the theory of Section II-A.
To validate the method for fault location, measurements of three consecutive samples at three instances during the transient period after the fault initiation were made, and the fault distance was calculated using (11) and (12) for each set of samples. In each case, the current derivative at a specific timeinstant (say, t 2 ) was calculated using measurement at that time instant and the previous measurement, i.e.,  through (11) and (12) is R f (m + 1), which is of no interest to fault location. This result validates the closed-form deterministic theoretical formulation developed in Section II-B.

IV. PERFORMANCE OF THE METHOD WITH NON-IDEAL SOURCES
When a fault occurs on a feeder-section in a dc microgrid, the current contributions from the dc link capacitors associated with converters dominate the fault current first [6], [23].
As capacitors resist rapid change in voltage, for a short period of time after fault the capacitor will act like a constant voltage dc source. Thus, measurements from this initial period can be used to determine the fault location modeled by (11) and (12). This section describes the converter models, and fault detection and location on a feeder fed by converters. Fig. 3 shows a two-bus dc feeder with dc-dc boost converters connected to the end-buses instead of ideal voltage sources. Parameters of this test system are listed in Table 2. Feeder parameters are taken from [24] to match the ampacity of the 100 kW converter. As LVdc feeders are likely to be short in length, feeder capacitance was not considered in Section II-A while developing the theory. But in practical cases, every cable is associated with some capacitance. So the performance of the proposed method was verified with cable capacitance included in the simulation. Equivalent capacitance for the 100 m long cable was divided equally into two parts (C cab in Fig. 3), which were connected on each end of the feeder to form a pi-section. A commonly used unipolar microgrid topology with T(earth)N(neutral) grounding scheme [25] is chosen, where the grid is unipolar and the neutral is solidly grounded [19], [26]. The fault location device based on the proposed theory is placed on the positive pole [19]. The dc-dc boost converter model is taken from [27]. Converter parameters are chosen using typical values for a 100 kW converter, and verified through a number of resources [7], [20]. It is assumed that the converter has an ideal dc voltage source at its low voltage side, representing a PV panel or a battery. This is justified, since the inductor at the input side of the converter (L cnv ) shown in Fig. 3, which  is placed to filter out the ripple in the input dc current [28], [29], will oppose any sudden change in current. Within the time frame of a few microseconds after fault inception when the method is applied, any rapid change in the input current is restricted by this inductor, and the voltage across the input source therefore remains constant. This was tested by replacing the ideal dc input source in Fig. 3 with a practical input source comprising of a battery in parallel with an input capacitor and the hypothesis was validated. The duty cycle is kept fixed, since the initial period after fault is governed by the natural response of an RLC circuit [6], [18], [23], and the converter control would not activate during that time. Load current is 247 A, representing almost the full load in the system. Fig. 4 shows currents through diode (iBus1 cnv−d ), through capacitor (iBus1 cnv−c ), the summation of the two (total current iBus1 cnv ), and the output voltage of the converter (vBus1) for the converter connected to Bus 1 in Fig. 3. It can be seen that the output current and voltage are practically constant throughout the time. The capacitor current and the diode current change depending on the switching of the IGBT.

B. CURRENTS UNDER NORMAL LOADING AND FAULT CONDITIONS IN CONVERTER INTERFACED FEEDERS
A fault was simulated in the dc feeder of Fig. 3 at 0.1 s with a fault resistance of R f = 0.01 at a distance x = 80 m from Bus 1. The simulation was run for 0.2 s. Fig. 5 shows the currents through different components under this fault condition-current through diode iBus1 cnv−d , current  through capacitor iBus1 cnv−c , total current from Bus 1 to fault iBus1 cnv .
The same circuit then was simulated replacing the converters on the two buses with ideal dc sources. The voltages of the dc sources were set at the prefault voltages of Bus 1 and Bus 2 of the dc feeder with converters. The current from Bus 1 to fault from the circuit with the ideal dc source was plotted in Fig. 5 in green (iBus1 vs ). Notice that total currents from Bus 1 to fault in both cases are practically equal to each other for much longer than 3 µs (equivalent to 3 samples here) after the fault initiation. Thus, (11) and (12) can also be applied to dc feeders fed by converters.

C. FAULT DETECTION AND FAULT LOCATION
Detecting a fault is necessary before applying the proposed method to locate it. This Section shows how (13) can be used for fault detection as well.
If voltage drop per unit length of line is denoted as v u (t), i.e., v u (t) = l * di 1 (t) dt + r * i 1 (t), so (13) becomes Under normal loading condition, as seen in Fig. 4, the converter output voltage and current remain practically constant, i.e., v 1 (t 1 ) ≈ v 1 (t 2 ). Voltage drop across the unit length of VOLUME 9, 2022 line can also be assumed constant, i.e., v u (t 1 ) ≈ v u (t 2 ). So, But v 1 (t) = L line * v u (t) + v 2 (t), where L line is the length of the line. So, Equation (17) implies that under normal operation the calculated length of fault point from Bus 1 will be larger than the line length. In case of Bus 2, the current in the line is flowing towards the bus. As a result, from the perspective of Bus 2, both, the measured current i 2 (t) and the voltage drop per unit length of line, v u (t), are negative. So, from (16), x becomes a negative number under normal operating condition. Thus, under un-faulted condition, the distance measured will be either greater than the line length or negative. This can be used to distinguish prefault condition from fault condition, and hence detect a fault. Note that the prefault current has to be used with care in this approach. Since the load current can change over time, the prefault current should be updated with every new sample if no fault is detected. But, once a fault is detected, the prefault current should be fixed at its latest updated value during the fault location process. Fig. 6 shows the flowchart of the proposed fault detection and location.

D. RESULTS
To evaluate the performance of the algorithm developed in Section IV-C, data were generated from the fault simulation described in Section IV-B with sampling frequency of 1 MHz. To implement the flowchart of Fig. 6, a moving window consisting of three samples was run through the accumulated data from the simulation to calculate the fault distance before and after the fault initiation. Fig. 7 shows the calculated distance of fault from Bus 1 (dist Bus1 ) and Bus 2 (dist Bus2 ) from 10 µs before fault inception to 10 µs after fault inception. Clearly, before fault inception the distance from Bus 1 is much larger than the line length, and distance from Bus 2 is negative, as discussed in Section IV-C. Within 3 samples after the fault inception (at t 0 = 0.1 s), calculated distances become almost equal to the actual distances of the fault point on the line. Thus, both detection and location of fault are correctly and accurately performed simultaneously in 3 µs after inception of fault.
The accumulated data spanned from 40 µs before the fault inception to 80 µs after. From the 3 rd sample after the fault inception time to the end of accumulated data, the calculated distances from Bus 1 varied from 79.8 m to 81.4 m. So, the proposed method provides accurate fault location over an extended range of data points after fault.

E. A SPECIAL CASE
Clearly, the derivation of theory assumes dc sources present at both ends of the feeder. Since most of the dc loads and all nonideal sources connect through converters, this is a reasonable assumption. A dc bus with only purely resistive load is therefore a rare case. However, it should be mentioned that under this unlikely scenario, one of the sources in Fig. 1 (a), say, V 2 , will be replaced by a load resistance. This will drastically alter the nature of the current i 2 (t) during fault, and the value of m in (8) will no longer be constant. This means the two foundational equations (11) & (12) that require m to be a constant will no longer be valid, and the method will therefore fail.
It is important to mention here that the dc feeder analyzed here would typically be a part of a dc microgrid. This special case can occur only if such microgrid is single-sourced and there is no converter based load in the microgrid. This is contrary to the vary nature of microgrids, and therefore this special case would be rare in practice.

V. USING THE METHOD FOR HIGH RESISTANCE FAULTS
In order to use the method for high resistance faults, the impact of higher fault resistance on the fault-induced transient needs to be understood. From (3), fault current in a feeder fed by an ideal source is   where, τ T is the equivalent time constant, and Also, τ L = L/R = time constant of line, and τ f = From (19), τ T is smaller than both τ L and τ f . The smaller the value of τ T , shorter the time the transient will last. Therefore, as the value of R f increases, the transient period will be shorter. Fig. 8 shows simulated currents from the circuit of Fig. 1(a), with varying fault resistances to verify this argument. In addition, the shorter transient also gets steeper, increasing the chances of erroneous calculation of di/dt. Therefore, to accurately determine location with high resistance faults, sampling frequency needs to be increased, so the required samples with adequate sampling rate for accurate calculation of di/dt can be obtained before the transient subsides.
According to the IEEE Power System Relaying Committee report [30], a fault is considered a high impedance fault (HIF) if it results in currents comparable to load currents, not detectable by traditional overcurrent relays or fuses. Based on the converter rating of 400 V, 100 kW, the corresponding load current and load resistance are 250 A and 1.6 , respectively. Therefore, any fault with resistance 1.6 or higher is considered a high resistance fault for this system. A fault is simulated in the system described in Section IV-A with R f = 2 , at fault inception time t 0 = 0.1 s, at a distance of 80 m from Bus 1. From the manufacturer's data-sheet of the chosen 185 sqmm conductor [24], τ L ≈ 2955.6 µs and τ f ≈ 2.3432 µs. According to (19), τ T ≈ 2.34 µs. According to [31], the transient will settle down approximately within 5τ T ≈ 11.71 µs after the fault inception. Current plot in Fig. 9(a) from the simulation supports the argument.
Observe from the voltage plot of Fig. 9(b) that the change in the capacitor voltage before the current settles to steady state is less than 0.82% of the initial voltage. This phenomenon is characteristic of high resistance faults. Because of low fault currents and fast transients, capacitors do not loose much charge, and voltage remains practically constant. Thus, the proposed theory, developed with ideal voltage sources, can be used to determine fault location for high resistance faults. Fig. 9(c) shows the plot of the calculated distance to the fault point from Bus 1 for this high resistance fault simulated at 1 MHz sampling rate. With this sampling rate, it is expected that the method will provide fault location for up to approximately 10 samples after fault inception. Fig. 9(c) shows that the method provides rational (though incorrect) answers for approximately 15 µs after fault inception. Then, the calculations are affected due to the determinant in (13) getting close to zero in steady state.
Clearly, there is a significant error in fault location. This is because errors are introduced in the calculation of di/dt due to the much steeper exponential transient. To minimize this error, a higher sampling frequency is required. Table 4 confirms this rationale. Conversely, it can be argued that lower sampling rates would suffice for faults with low fault resistances. In the fault simulation case with R f = 0.01 in Section IV-B, data were sampled at 1 MHz frequency. The same circuit was simulated and sampled at lower frequencies and the proposed algorithm was implemented for the same amount of time to check the performance of this method at lower frequencies. Table 5 shows the results. Data points from lower sampling frequency cases result in higher error, but even with 100 kHz sampling frequency, the error is less than 5%.
To further investigate the performance of the method for high resistance faults, faults with resistances ranging from 0.01 to 100 were simulated. Table 3 lists the sampling frequencies required to get the fault location error within ±1.5%. These results illustrate that as long as the sampling frequency is adequate, the proposed method provides accurate results, regardless of fault resistance. The state-of-the-art oscilloscopes have probes that can sample up to 100 GHz [17], which would enable the method to work for higher fault resistance values as well.
It should be mentioned that all the faults considered in this paper were purely resistive. In ac distribution systems, HIF has a complex model with non-linear elements like diodes and variable resistors, to capture the results obtained by staged faults [32]. This model represents the arcing that almost always accompanies such faults, which, depending on the ground-surface in the fault path, changes significantly, producing different amounts of heat, making the fault resistance change randomly. Such models have not been developed for faults on low voltage dc circuits, and hence out of scope of this paper.

A. FAULT DISTANCE
Rf , the less L 1 or L 2 will be, the less L p will become, which will eventually result in lower τ f . So,  if the fault is very close to or very far from the bus, τ f will be smaller, and according to the trend seen in Section V, errors will be higher, potentially requiring higher sampling frequency. To examine the sensitivity of the method to faultdistance, several simulations were performed with varying fault distances and R f = 0.01 in the system of Fig. 3. Then sampling frequency was varied to examine the impact on the location error. Results are tabulated in Table 6. The results support the argument. Notice that with 1 MHz sampling frequency the error is quite low for all fault locations, showing low sensitivity to fault distance. So, there may not be any need to change the assumed sampling frequency.

B. DC LINK CAPACITOR SIZE
The proposed fault location method is accurate because the dc link capacitor behaves like an ideal dc source for a short duration after the initiation of a fault. But the time duration for which the response of the capacitor can be treated as the response of an ideal dc source is dependent on the size of the capacitor. Given the fault resistance, line parameters, and fault distance is fixed, this duration gets larger if the capacitor size (in Farad) gets larger. With the advancement in power electronics and high-speed switching devices, the 530 VOLUME 9, 2022 capacitor size used at the output of converters is getting reduced, since the high speed switching devices can support higher switching frequency. So, it is important to check how the method performs with lower values of dc link capacitance.
A general approach to calculating the size of the output capacitor of a dc-dc boost converter is to use the concept of charge balance. According to this concept, during steady state the average change of the stored charge and hence the average change in the capacitor voltage will be zero over a switching period. From (20), which can be derived from [29], the minimum capacitance C required to restrict the ripple at the converter output within v max can be obtained.
Here, 2 v max = ripple voltage (peak-to-peak), I = average inductor current, C = dc-link capacitor value, and T s = switching-period.
Several simulations were performed in the circuit of Fig. 3, adjusting the dc-link capacitor size and the switching frequency according to (20). Location error was calculated for R f = 0.01 and R f = 0.1 . Table 7 shows the results. It can be seen that even with a very low capacitor size (associated with very high switching frequency), the method performs well.

VII. CONCLUSION
This paper develops a deterministic closed-form mathematical model based on the time-domain physical model of a faulted dc feeder, fed from both ends. It is shown that as long as the sampling frequency is high enough to enable accurate calculation of the current derivative (di/dt), the single-ended fault detection and location method derived from this model is immune to fault resistance. This overcomes a well-known hurdle encountered in all single-ended fault location methods proposed in literature. The method is shown to work even when the feeder is fed by converterbased practical dc sources. The detection and location happens simultaneously in 3 samples after inception of fault, which translates to 3 µs for a sampling rate of 1 MHz. This assures the safety of circuit breakers as well as converters. The method works well even for high resistance faults, if the sampling frequency can be increased, a condition that is not unreasonable with the technology available today.

VIII. POTENTIAL FOR FURTHER RESEARCH
This paper reports the discovery of the mathematical foundations and implementation of a fast fault location method for a dc feeder that is independent of the topology of the system built around the feeder. This opens the doors for a communication-free topology-independent protection scheme for an entire dc microgrid. Such a scheme could use the method as a time-domain distance relay, placed on each side of every feeder of a dc microgrid. However, the backup protection in such a scheme requires further research. Another avenue of research would be investigating and adapting the performance of the method for different grounding schemes in a dc microgrid. Research can be performed to include feeder capacitance in the formulation to adapt the method for HVDC lines fed by voltage source converters (VSCs). An arcing model for HIF faults is another worthy research pursuit.

APPENDIX A Detailed Proof of Fault Current Expression in DC Microgrids With Ideal Voltage Sources
Applying KVL in loop 1 of Fig. 1b, the following can be obtained Similarly in loop 2, From (1) and (2) we can get where, and, and, Putting the values of 1 and in (A.1), I 1 can be expressed as Let's say the denominator of (A.5) is (L 1 L 2 ) * s(as 2 + bs + c) where Roots of as 2 + bs + c = 0 are where, 1/L p = 1/L 1 + 1/L 2 , parallel equivalent inductance of L 1 ,L 2 . But, Now, roots from (A.7) If (A.5) is expanded through partial fraction expansion and subsequent inverse Laplace transform is done on that, the current expressions will get the following forms. and, It can be shown that, in (A.14) the coefficient K 2 = 0. The coefficient K 2 will be Numerator of (A.15) can be reorganized as follows From the prefault circuit I 0 = (V 1 − V 2 )/R, so the numerator comes = s 2 L 1 L 2 ( When evaluated at s = −λ L , the numerator becomes = (−λ L ) 2 L 1 L 2 ( But from line parameter, R 2 /L 2 = R/L, i.e., R 2 = RL 2 /L. So the numerator becomes This means coefficient K 2 = 0 and eventually current i 1 (t) reduces to So the current i 1 (t) can be represented through one exponent. In a similar fashion, expression for i 2 (t) can be derived and written as i 2 (t) = K 1 + K 3 * e −(λ L +λ f )t (4) VOLUME 9, 2022

APPENDIX B CALCULATION OF COEFFICIENTS
In this section, coefficients K 1 and K 3 are calculated for section III using the relevant data. From (A.13) Similarly