A Temperature-Aware Framework on gm/ID-Based Methodology Using 180 nm SOI From −40 °C to 200 °C

The advent of the Internet-of-Things brings new challenges in circuit design. The presence of circuits and sensors in harsh environments brought the need for methodologies that account for them. Since the beginning of the transistors, the temperature is known for having a significant impact on performance, and even though very low temperature sensitivity circuits have been proposed, no general methodology for designing them exists. This paper proposes a gm over Id technique for designing temperature-aware circuits that can be used either on measurement data, analytically, or based on simulation models. This model is validated using measurements up to 200°C of X-FAB XT018 transistors and later with a circuit design example.


I. INTRODUCTION
W ITH the challenge of connecting people and circuits, Internet-of-Things (IoT) introduces new power decisions in autonomous electronics in consumer products. The challenge of connecting people with different objects has been extremely rapid in recent years. Today, electric vehicles represent new investments in sensors and integrated circuits that, between 2017 and 2019, accounted for a 1.3 billion dollars worldwide investment with projections of growth in the next coming years. [1]. Vehicles' IoT circuits must efficiently sense and communicate with other nearby devices, considering the working environment [2]. For obvious reasons, the design and the specification of vehicles' IoT circuits are regulated by many strict security and safety standards. The temperature range is arguably the most demanding environmental challenge for electronics in the automotive industry [3].
Circuit design for harsh environments places new constraints on system design, representing a challenge for low-cost, reliable devices [4]. Even though in a late 90s report, the U.S. National Research Council pointed out the possibility of Si materials to operate up to 300 • C [5], the usual approach for designing small temperature sensitivity circuits relies on the use of wide bandgap semiconductor materials such as GaN [6] or SiC [7]. Even though those materials present intrinsically smaller parameters degradation over temperature [6], [7], they come with a higher production cost, not enabling the integration of digital circuits on-chip, an essential feature of smart sensing.
Being a standard in high-end automotive applications, the SOI 180 nm process technology from the X-FAB Silicon Foundries is ideal for electronics to operate near-combustion engine compartments or electric engine housings with a temperature range from −40 • C up to 175 • C [8], lowpower digital applications in communications, consumers, and industrial markets [9]. Silicon-based SOI technologies, as X-FAB, are indispensable for high temperature operations due to the reduced current leakage and have dominated the consumer market, having affordable production costs.
Literature has presented design solutions to address temperature-aware circuits in Si technologies. In [10], a current reference is proposed by combining a beta-multiplier current source with an altered version of a Nagata current mirror and a high-temperature coefficient resistor to design a circuit with a 200 ppm/ • C temperature coefficient. Toledo et al. [11] have proposed a zero temperature coefficient bias point (ZTC) for the gate transconductance based on the UICM model and explored this point to design a 34 ppm/ • C single-ended Gm closed-loop resistor. Another approach showed in [12], where a closed-loop digital controller is proposed to control the non-linearity error of a temperature sensor.
Even though recent papers presented very low temperature sensitivity, the presented methods are mostly dependent on the ZTC operation point of a unique transistor or additional control circuitry. This design choice intrinsically increases consumption and production cost which could be prohibitive in new low-power IoT devices. With the increasing need for temperature-aware designs, it is indispensable to have a common framework for developing temperature-aware circuits.
This work proposes a temperature analysis using the g m /I D methodology. By introducing the concept of temperature normalized g m /I D parameters. The presented ZTC bias points have no significant influence on mobility temperature dependency and are still compatible with the g m /I D methodology. The analytical development is done using the UICM model and validated by simulations on BSIM v4.6, factory-validated from −40 • C to 175 • C, and measurement data for higher temperatures up to 200 • C. Moreover, a global framework in temperature-aware methodology and a design example are presented.
The paper is organized as follows: Section II explores the state-of-the-art ZTC points and discusses their trade-offs. In Section III, the temperature normalized g m /I D method is presented and validated with simulations and measurement data. An example circuit is presented in Section IV. Finally, Section V concludes and summarizes this brief.

A. TEMPERATURE EFFECTS ON MOS TRANSISTORS
Most temperature-aware circuit designs rely on ZTC bias conditions, i.e., points where the value of a given parameter remains almost independent of temperature. The known ZTC bias conditions are based on the threshold voltage and mobility temperature dependency [11], [13]. For this reason, they are dependent on the temperature modeling of those quantities, which are not necessarily accurate in the circuit working conditions [14].

1) THRESHOLD VOLTAGE TEMPERATURE EFFECTS
Even though the threshold voltage (V th ) has a ratter blurry definition at the latest MOSFET models [15], [16], it is a key parameter for circuit design. In this paper, the V th definition will be taken as the gate voltage that equalizes drift and diffusion current components [17]. The threshold voltage has a well-defined temperature dependency based on the materials and transistor properties given by [18]: where k b is the Boltzmann's constant; q the elementary charge; N c , N v are respectively the effective density of states on the conduction band and valence band; N a the acceptors doping density; n 0 = 1 + γ /(2 √ 2φ F ); γ the body factor; φ F the bulk quasi-Fermi level of the major carriers. Though α th is not constant over temperature, their variation in extensive temperature ranges still negligible [16].

2) MOBILITY TEMPERATURE DEPENDENCY
Usual mobility temperature dependency modeling considers an exponential temperature dependency. This model is valid under the assumption that one of Si's significant scattering events is predominant. The primary approach to combine different scattering effects is Matthiessen's rule: where μ eff is the total effective mobility and μ i the contribution of each scattering event. However, as pointed out in [19], Matthiesen's rule is only valid using the Time Relaxation Approximation, assuming Boltzmann statistics, and, more importantly, if the characteristic scattering exponents are the same for the different scattering mechanisms. These assumptions are hardly valid for Si-based transistors in their working environment. Typical process design kit, transistor models combine surface phonon scattering and surface roughness using Matthiessen's rule expressed as: where E eff is the effective electric field; θ ph , θ sr are empirical parameters related to phonon scattering and surface roughness; μ 0 is the carrier mobility limited by ionized impurity scattering and acoustic phonon scattering; ν is an empirical parameter that accounts for a statistical averaging of the relaxation times [20]; β μ is the strong inversion temperature coefficient [16]. This claim can hold either in a short temperature range or at a specific inversion level where a scattering mechanism is dominant. Sub-micron MOS technologies require a deeper understanding of semi-classical and quantum transport. As pointed out by [21], ballistic transport begins to overcome the classic drift-diffusion regime. Therefore, it represents a new challenge for the already difficult task of modeling mobility. Since mobility temperature modeling is a complex task for semiconductor physics, it is even more challenging for the designer to consider it. For this reason, most of the model modifications to better account for temperature changes are empirical or semi-empirical expressions for mobility temperature dependency [22], [23].

3) ZTC BIAS
MOSFET ZTC bias are well known since the beginning of MOS technology, notably the drain to source current ZTC (I DS ZTC ) [24] and, more recently, the gate transconductance ZTC [11] (g m ZTC ). The I DS ZTC is illustrated in Fig. 1(a) for an NMOS transistor from XT018 technology; the ZTC condition is given in [24] as: V th is the extrapolated strong inversion threshold voltage; φ B the bulk potential; n i the intrinsic carrier concentration and μ the average channel mobility. One may conclude that the I DS ZTC is found for a V GS between 0.6V to 0.8V. More recently, the gate transconductance ZTC (g m ZTC ) was proposed by [11], using the UICM model described as: η is the threshold slope and i fgz the inversion coefficient at the I DS ZTC point. Even though those ZTC points exist, their bias condition relies on mobility temperature dependency, which depends on several scattering effects including ballistic ones in new technologies [25]. For this reason, modeling the temperature dependency is a challenging task. Besides, Fig. 1(a) and 1(b) highlight a required V GS close to V th from this technology and, therefore, in the moderate inversion region. In opposition to the strong and weak inversion, the moderate inversion does not present a straightforward current model [13]. Furthermore, some critical parameters for analog and digital design, i.e., g DS , are already proven to do not have a ZTC point, as pointed out in [9].
To propose a common framework for temperature-aware design, one may approach it using a design methodology such as g m /I D . Proposed by Silveira et al. [26] is a powerful transconductance to drain current method to help designers size up transistors quickly. The so-called "g m /I D design" was initially developed to calculate parameters such as small-signal gain and bandwidth, later extended to distortion analysis [27], age-dependent degradation effects [28], and short channel effects [29].

III. TEMPERATURE ANALYSIS OF G M /I D PARAMETERS
The g m /I D methodology introduces width-independent parameters allowing the designer to choose the transistor W to accommodate other circuit prerequisites such as power consumption, occupied active surface, and operation region. The main parameters analyzed in this paper are the gate transconductance ratio (g m /I D ) and the transistor self-gain (g m /g ds ). The mathematical model to analyze those parameters will be based on the UICM model, introduced by Galup and Schneider [30], a charge-based model that accounts for accurate, but straightforward g m /I D parameters expressions, even quasi-ballistic nanometer-sized transistors [31]. The validation is done using the factory temperature validated BSIM model from −40 • C to 175 • C and measurement data from 27 • C to 200 • C.

A. GATE TRANSCONDUCTANCE RATIO
The g m /I D parameter for a long-channel transistor, neglecting specific current gate voltage dependency, is defined in the UICM model as: where φ T is the usual thermal voltage and q is , q id are the inversion charge on the source side and the drain side normalized by the inversion charge at pinch-off. Fig. 1(c) illustrates the g m /I D parameter obtained from electrical simulation using XT018 process design kit for a 10 × 0.22μm 2 low V th NMOS transistor for three different temperatures, one may notice the absence of ZTC bias. From a design point of view, it is helpful to analyze the bias dependency of the given parameter, analyzing (8), the only term that is not bias dependent is φ T . In order to evaluate the bias effect on g m /I D one may define the temperature normalized gate transconductance ratio (G g ) as: The sensitivity is defined in [32] as the normalized vari- The temperature normalized gate transconductance G g is a function of η, q IS and q ID , and can be expressed as: As reported in [31], the weak inversion slope factor η is sufficient to represent the g m /I D characteristics even in quasi-ballistic transistors; therefore, one may define η by ignoring the inversion charge as: by definition, the η sensitivity can be calculated as: the flat-band voltage temperature behavior depends on the materials used for the transistor gate contact and bulk. In the node sizes addressed in this paper, the gate contacts are highly doped poly-Silicon with bulk-Si. The poly-Silicon is considered doped enough, so it's Fermi level is pinned to the conduction band. By considering a low enough doping on the bulk and that Boltzmann statistics apply, one may write: For Silicon, the extrapolated bandgap at 0 K (E G (T = 0)/q) is 1.12 eV; for normal doping levels, the Fermi level is not very apart from the middle gap (E G (T = 0)/2 · q) making the flat-band voltage (V FB ) temperature derivative very low and, by consequence S η T negligible. Some approximations were made for the development of the η sensitivity. Fig. 2 evaluates the relative error of those approximations when calculating the Fermi Level. The gray area's top represents the limit where Boltzmann statistics and incomplete dopant ionization give a relative error smaller than 1%. The bottom border of the gray area is caused by neglecting minority carriers on the Fermi level calculation. Since the usual doping of Silicon starts to rise with scaling, some factors to account for Fermi-Dirac statistics and incomplete ionization may be added for smaller technologies.
The normalized inversion charges (q is , q id ) sensitivity can be obtained from the so-called universal MOSFET characteristics of the UICM model: by taking the temperature sensitivity of both sides of (15) one may find It is essential to point out that unlike the ZTC bias pointed out on Section II-A3 the bias voltages are considered temperature-dependent. The importance of considering the temperature dependency of the bias voltages is that even though on the test benches often used for to extract the ZTC points, the bias point is constant, in a more complex circuitry, transistor nodes not connected at voltage sources can suffer from bias drift with temperature. For an extended temperature range, the use of Silicon on Insulator (SOI) is essential to minimize gate currents. Considering a MOSFET with source and bulk connected V S = 0 and that in moderate inversion (1 < q is(d) < 100) q is ≈ q id =q one may find: Since q id , q is , G g , η, and φ T are always greater than 0, one may find that the ZTC condition is taking the usual approximation of V p ≈ (V GB −V th ) /η and the threshold temperature dependency from (1). One may find that the nil condition of (17) is At the vicinity of the ZTC point, V p ≈ 0; q is ≈ q id ≈ 1 [30] the sensitivity can be approximated as: by replacing (18) in (15) ones may find thatq it is independent of V D and equal to a temperature invariant constant (ν): Since for modern node sizes α th tends to get smaller due to the channel doping increase [13], and η lies between 1 and 3, the right-hand side of (18), is very close to zero and a weak temperature function. Fig. 3 shows the sensitivity of the G g parameter for a 10 × 10 μm 2 low V th transistor obtained from BSIM simulations using the factory validated PDK from −40 • C to 175 • C. It is important to point out that in our simulations, the same ZTC point was found in small length transistors, which is expected since g m /I D is known to have little channel length dependency [31].
To extend the temperature range, factory measurements were made and are here presented on Fig. 4. The same ZTC bias point can be seen in measurement data obtained from the same transistor up to 200 • C. Fig. 4 shows the G g parameter extracted from measurement data at 27, 75, 125, 175, 200 • C of a long and a short channel Low V th NMOS transistor with the estimated V GS ZTC . The gate transconductance was obtained using Euler's method, and the threshold voltage was obtained at the different temperatures by the linear extrapolated method with the correction proposed in [33] following the threshold definition. The extracted V th at different temperatures was later fitted using least squares to obtain α th and V th0 estimation. The η parameter was obtained from the linear interpolation of the log current in weak inversion.

B. SELF GAIN
Another critical parameter on the g m /I D methodology is the self-gain (g m /g DS ). This parameter's modeling needs to be handled with little more attention since the selfgain is very sensitive to short channel effects compared to the g m /I D parameter. According to [34], the significant short channel effects controlling the drain to source transconductance are velocity saturation, drain induced barrier lowering (DIBL), and channel length modulation (CLM). Those effects will be first evaluated, and then a g m /g DS expression will be presented for temperature behavior evaluation.

1) DIBL
The DIBL is a 2D effect that includes the variation of carriers barrier on the source to drain axis caused by the V D variation. In a long channel MOSFET, the threshold voltage can be extrapolated from the classical MOS capacitor 1D analysis, since most of the channel has similar behavior. However, this approximation does not hold in short channels since the transverse field and drain/source junctions can no longer be neglected. In the short channel case, the V D increase causes a reduction of the PN barrier between source and gate, usually modeled as a linear relationship between the threshold voltage and V D [13].
Since the definition of DIBL naturally depends on the transistor length, many works have proposed different σ (L) relations. However, most experiments show a power relation with L [13]. One may express this relation in general as: Fig . 5 shows the DIBL effect from measurement data. V th was extracted using the method explained in [17]. Even though the work [26] points out a linear increase of σ with temperature, as illustrated in Fig. 6, the 99.7% confidence bars of the extracted σ value exceeds the presented temperature variation, and therefore was considered negligible. Since the available measurement data only contains two different channel lengths, the σ parameter was extracted from Spectre simulations from the foundry PDK. Even though BSIM 4v6 (suitable for the node size) models σ (L) having an exponential relation, [13] points out that the model shown in (22) fits better with experimental results. For this reason the latest BSIM version uses (22) model [16]. Fig. 7 shows the comparison of both models presenting overall similar behavior.

2) VELOCITY SATURATION
With the decrease of channel length, the electric fields hugely increase, giving carriers more energy and increasing the probability of scattering events [19]. This increase of scattering events, limits the maximum electric field on the channel to a value E sat . This saturation makes the transition between the linear and saturated regimes occurs earlier than the classical limit V D sat = V GS − V th . In [34], the V D sat is considered constant (≈ L · E sat ) because the channel length is smaller than 200 nm, which is not the case for all transistors on the working technology. Jepers et al. [35] define V D sat as 2/g m that, in contrast to [34] is highly dependent of  V GS , a proposition considering both effects in V D sat is given in [36] as: To validate (23), V D sat was extracted using [37], the E sat value was calculated from the measured g m /I D for L = 10μm and then reused for L = 0.18 μm. The obtained V D sat can be shown in Fig. 8. The obtained E sat = 1.396 · 10 4 V/cm value is in accordance with literature values.

3) CHANNEL LENGTH MODULATION
When the drain to source voltage exceeds V D sat , the pinchoff region starts to grow towards the source, making the effective channel length smaller with the increase of V DS . In [34] the CLM effect is modeled as: the α coefficient is a length-dependent coefficient responsible for the CLM strength and V 0 a constant model parameter.
It is important to point out that, even though no temperature studies were made concerning the α and V 0 parameters, they showed no temperature dependency on our experiments. Fig. 9 shows the results from the extraction of CLM parameters using [34] for different channel lengths and temperatures, α and V 0 were kept constant trough different temperatures while E sat modeled with a surface roughness scattering predominant model [13]. The obtained values where V 0 = 0.433 V and the α parameter modeled in [38] as: It is important to point out that the temperature variation observed in Fig. 9(a) is due to E sat variation following the dependency of the limiting scattering effect. Contrary to mobility temperature dependency, the scattering mechanism is known and unique (surface roughness scattering on Silicon). Since only one scattering mechanism is responsible for the field saturation, the exponential temperature behavior can be taken with no approximation. Fig. 9(b) validates (25) by showing the extracted value of α and the polynomial relation with the channel length.

4) G M /G DS MODEL
The latest subsections explained the principal effects that affect the self-gain, with those effects modeled and extracted based on [35] definition, one may write g m /g ds as a function of the temperature normalized gate transconductance  ration G g : Fig. 10 shows the g ds /I D × g m /I D plot for one transistor with two different channel lengths. The the decreasing part of the curve is dominated by CLM, represented by the second term in (27). The increasing portion is the DIBL dominated g ds /I d (G g ) relation. Fig. 11 shows the temperature variation of the g ds /I D parameter using 4 · L min , a very common rule of thumb length for analog design, V DS = 0.6V at different temperatures −40 • C, 27 • C and 175 • C. Even though the different curves cross in an area close to G g = 0.1 the difference on the bias of those crossing points are very different and therefore unusable for large temperature variations. For low-power devices, weak and moderate inversion bias is preferable, the transistor's bias point will rather lie on the DIBL dominated region. As in the g m /I D characteristics, a factor 1/φ t is present on this region. Thus, one may define a temperature normalized quantity (G d ) for the g ds /I D similarly to what was done for g m /I D as Since most of the analog expressions for circuits are written in terms of g m /I D and g m /g ds , it is essential to highlight the expression of the latter as a function of the temperature normalized g m /I D parameters. Fig. 12 shows the relation of both temperature normalized parameters for different channel lengths. Fig. 12 shows the two proposed temperature normalized g m /I D parameters (G g , G d ) for two different channel lengths, extracted using (27) and the previous extracted values. At first glance, it is noticeable that a ZTC point occurs in the DIBL dominated portion of G d in small channel sizes.

5) TEMPERATURE ANALYSIS
In order to evaluate the G d temperature sensitivity, one may write (27) as a function of G g , for this matter, G d will be divided into two parts, responsible for DIBL and CLM effects: (30) By separating G d on those factors, the total sensitivity can be written as:  temperature dependency of the multiplicative factor. One may suppose that the ZTC points occur when: using the approximations developed for the ZTC vicinity of G g Fig. 12(b) shows the G d sensitivity, as described by (33). The linear relation with G g makes the overall shape pretty similar. However, minimum point position is now dependent on V DS , L, and V p in opposition to the S G g T that mainly depended on V p . It is important to point out that (33) implies that there is a maximum channel length that the ZTC occurs, this relation depends on the dependency of σ and α to L better developed as: where C 1 = 8 · η · π · t ox , C 2 = σ 0 + σ 1 · V SB , and V p the left-hand side of (33). Since L m is a monotonic function and α a quadratic polynomial, if (33) occurs then it must cross twice defining a region where the ZTC condition is fulfilled. Fig . 13 shows the pinch-off voltage G d ZTC obtained from BSIM 4v6 simulations. The lines lie inside the limit defined in (34). The short channel ZTC point comes in contrast with usual analog design practices that maximize L to increase linearity performance, with the trade-off of decreasing speed performance.
Another way of seeing this deduction is given that when L gets bigger, the DIBL effect gets smaller and CLM dominates on (30) , which has no ZTC bias point. Both sensitivities for long and small channels are illustrated in Fig. 14.

IV. CIRCUIT DESIGN EXAMPLE
To better illustrate how the temperature normalized g m /I D parameters can be used in a temperature-aware design, one may take as an example a simple PMOS differential pair OTA with active load, as illustrated in Fig. 15. This example is often used in design methodology studies as an standard testing circuit [26], [39]. The voltage gain and its temperature sensitivity can be written in terms of the temperature normalized parameters as: By imposing M 2A,B and M 1A,B to be at the vicinity of G g ZTC developed in (20), (36) simplifies to: Therefore to have a ZTC, A v we must have either V p2 = V p ZTC (η 2 − 1) = 0.08 V or make σ 1 = η 1 η 2 = 1.0123. Since it is not possible in the technology XT018 to have such a big DIBL coefficient, M 2A,B is biased at V p = 0.08 V. In order to compensate the (18) temperature dependency, the current-source temperature coefficient was chosen such as the temperature coefficient of V D M2,A being α th η . The biasing  transistors sizes were chosen so they are biased in I DS ZTC point.
The obtained voltage gain is illustrated in Fig. 16 at the typical corner and the worst corner boundary defined by FS and SF corners. It is essential to point out that the temperature coefficient of the bias current is negative, the  temperature-aware solution does not come with a power consumption (9.2 μW at 27 • C) increase. This is an essential feature for novel, temperature-aware, low-power IoT circuits.
To compare the novel technique with the conventional g m /I D methodology, one may take the methodology given in [35] for the same topology. All transistors' lengths were made 3 · L min for linearity improvement. The g m /I D of the active load, the differential pair, and the current mirrors were chosen to be 4 to decrease the gain loss compared to the common source amplifier and maintain the V Dsat small enough for M 1,2,3 being saturated. The electrical simulations result from the classically designed circuit can be seen in Fig. 17.
In order to evaluate circuit temperature performance the temperature coefficient (TC) is usually used as a figure of merit. However the usual definition considers 27 • C as a reference temperature. Since the goal of the method is to allow for a wide temperature working range, in contrast to a circuit that will work around ambient temperature, another approach is taken in this work. To this end, one may define a modified TC figure of merit as: T C eqq (A v ) = (max(A v ) − min(A v ))/(A v (mean(T))(T max − T min )).
Using the proposed definition, the obtained value of T C eqq on typical corner for the proposed circuit is 107.33 ppm/ • C, compared with the traditional design that got roughly a 22 times bigger T C eqq of 2364.46 ppm/ • C. The different sizing and performance figures of the two designs are presented on Table 1. One may notice the more significant power consumption for the more traditional circuit since the transistors are classically biased in strong inversion.
The different corners on the optimized circuit still presented the same gain temperature regulation with different T C eqq , showing that the technique still works even with process variations.
Since the mean gain depends on g mPMOS /g dsNMOS parameter, it is expected, as seen in Fig. 16 that the SF and FS corners present a higher variation on the mean gain. However, this variation on the mean gain does not affect the small temperature sensitivity of A v presenting 260 ppm/ • C and 82.42 ppm/ • C FS and SF corners, respectively.

V. CONCLUSION
An extension of the g m /I D method was proposed to allow for temperature-aware circuits' design by introducing temperature normalized g m /I D parameters. Those modified parameters allow the use of ZTC points in the early design stages. Those ZTC points were developed using the UICM model; however, they also allow a table-lookup design paradigm from g m /I D methodology. The limits of the temperature sensitivities of the weak inversion η parameter and the effective mobility (highly model dependent) were explored and ended up not being relevant for the ZTC analysis.
A circuit design was presented using the proposed methodology having an equivalent temperature coefficient of 107.3ppm/K for its gain performance having a 22 times improvement to the traditional g m /I D methodology. The novel temperature stabilization methodology is shown to hold even with process variability. This is the first demonstration of a temperatureindependent gain for an extended temperature range suitable for smart vehicles to the best of our knowledge. The use of a g m /Id methodology proves to be a very general design methodology that allows the designer to consider temperature effects using the novel technique proposed in this paper. ACKNOWLEDGMENT J. R. R. O. Martins and P. M. Ferreira would like to pay a tribute to Prof. A. C. M. Queiroz, who has left them after a long battle against cancer. As his former students, they would like to thank him for all his lessons, that without it they would never achieve the results presented in this work. JÉROME JUILLARD (Member, IEEE) was born in Nice, France, in 1973.