Analysis of GAA Junction Less NS FET Towards Analog and RF Applications at 30 nm Regime

This research focuses on a quantum model created using an entirely novel nanosheet FET. The standard model describes the performance of a Gate-all-around (GAA) Junction-less (JL) nanosheet device with a gate dielectric of SiO 2 and HfO 2 , each having a thickness of 1 nm. The performance of both the classical and quantum models of the GAA nanosheet device is evaluated using the visual TCAD tool, which measures the I ON , I OFF , I ON / I OFF , threshold voltage, DIBL, gain parameters (g m , g d , A v ), gate capacitance, and cut-off frequency ( f T ). The device is suited for applications needing rapid switching since it has a low gate capacitance of the order of 10 –18 , according to the simulation results. A transconductance (g m ) value of 21 µ S and an impressive cut-off frequency of 9.03 GHz are displayed during device analysis. A detailed investigation has also been done into the P-type device response for the same device. Finally, the proposed GAA nanosheet device is used in the inverter model. The NSFET-based inverter, although having higher gate capacitance, has the shortest propagation latency.


I. INTRODUCTION
Due to its strong channel gate control and ability to scale to the 7 nm technology node, FinFET emerged as the architecture to watch at sub-22 nm nodes.Additionally, the FinFET made a significant contribution to high-performance (HP) applications.
According to the foundry papers (N7) [1], [2], FinFETs are still employed, albeit more often, at the 7 nm technological node.However, it is demonstrated that the FinFET cannot be further scaled down since it became difficult to maintain the device's electrostatic control in next technological nodes.A narrower fin is required for preserving good electrostatics.However, this results in decreased carrier mobility and fluctuating threshold voltage (V th ) [3], [4], [5].To boost performance, the nanowire (NW) and nanosheet (NS) architectures emerged as promising contenders for sub-5 nm nodes [6], [7], [8], [9], [10], [11].Therefore, it is crucial to evaluate the performance of these devices using physics-based 3D simulations.At nodes smaller than 5 nm, the GAA nanowire FET demonstrates greater electrostatic integrity.
The drive current in NWFETs is constrained by the smaller channel area, which limits their use in HP applications.
The building of stacked NSFETs, which performed better than FinFETs and stacked NWFETs, was proposed by IBM in 2017 [12].NSFETs may have lower parasitic capacitance for a given active width, improving the effective capacitance-current (C eff -I eff ) relationship.NSFET became a strong contender for scaling sub-5 nm technology nodes as a result [12].Si NSFET has been developed in the meantime to enhance effective channel widths (W eff ) for greater current drivability while assuring ideal electrostatics through gate-allaround (GAA) design.Additionally, NSFETs regulate drive current by altering NS width, enabling designs that are compatible with CMOS layouts [3].
A key consideration for the semiconductor industry is transistor size reduction since it directly improves the speed of integrated circuits.The prime objective of design engineers in the chip industry is to design a smaller transistor with low power consumption and operating at high frequency.By redesigning the fin shapes to provide the desired performance, a device can be made smaller [13].With drain expansion and the imposition of the dual-k dielectrics with underlap criterion for FinFET devices, performance characteristics in RF and analog have improved [14].Utilizing high-k materials will reduce leakage current [15].Because they can be scaled up with the same device area and still attain comparable device efficiency, stacked Nano sheet devices are preferable to Fin-FET and Nanowire devices [16].The channel must undergo quantum adjustment due to its extreme quantum mechanical confinement, which significantly lowers the saturation current [17].GAA Nanosheets and Nanowires provide enhanced and flexible performance optimization, and the device settings can be changed by the designer [18].For quick transition and high I ON upon I OFF ratio, tri-gate junctionless FETs are made for digital circuits [19].NSFETs with various thresholds can be employed in a variety of exceptionally well and ultra-powerful applications [20].By offering a selective deposition strategy, RC latency was further improved [21].The hetero gate dielectric oxide with GAA nanowire (GAANW) displays an improved I ON upon I OFF ratio, higher g m , reduced DIBL, and perfect SS in comparison to DM devices [22].The RC delay and the DC/AC performance are improved by adopting the process-induced variation [23].It is possible to obtain the parameters for an RF-MOSFET with a small-signal model [24].For drain overlap zones, vertical construction and surface treatment are used to reduce the detrimental effect of SCE impacts [25].Surface roughness needs to be kept to a minimum for the device to function properly [26].The thickness, channel orientation, and surface orientation of the silicon are all crucial parameters in FinFETs [27].Improved shortchannel effects and even better performance in both DC and AC studies are shown by multi-gate FET performance studies, proving it is suited for low-power applications [28], [29], [30], [31], [33], [34], [35], [36], [37].With the aid of the review, the traditional tri-gate model is created using the same parameters [19] and implemented using a simulation platform to match the drain current.In addition, to improve performance, a fourth gate is added to the bottom of the tri-gate model to  create a gate that surrounds the device (Quad gate model).One further feature-the effects of the quantum model on the classical model-has also been added to the device to make it suitable for use in analog and RF applications.To see the flexibility in the circuit environment, the 3D inverter model is designed using both the classical and quantum models.The Visual TCAD professional platform is used for the entire procedure.

II. PROPOSED DEVICE STRUCTURE AND SIMULATION METHODOLOGY
Fig. 1 depicts the quad gate containing multilayer gate oxide and a junction-free Nano-sheet device in three dimensions.We take into account the parameters using [19], [24], and [32].To finish the changes by constructing gate all the way around, a gate is also built at the bottom.In addition, SiO 2 and HfO 2 gate oxides are stacked with the same gate oxide thickness to prevent gate leakage.Table 1 lists all the additional improvement parameters and shows their geometric properties.Uniform doping with an acceptor concentration of 1×10 19 cm −3 is maintained throughout the channel region.The dielectric constants are set to be 3.9 (low-k) and 22 (high-k).The operating voltage V DD of 0.1 V and 1 V are considered during linear and saturation mode of operation respectively.Topological architecture for both classical and quantum components is shown in Table 1.The work function of N-type polysilicon and operating temperature are chosen as 5.2 eV and 300 K, respectively.
The carrier temperature, electric field, and voltage each affect the current across the proposed GAA device.By resolving several density-gradient drift-diffusion equations, a detailed simulation of a 3D quantum mechanically corrected device is performed.The Auger model is used to take carriers' lifetime and current density into account.Shockley-Read-Hall models are included to take into account generation and recombination effects.Schenk's model and Caughey-Thomas model are used to account for bandgap narrowing effects brought on by high doping as well as velocity saturation effects.The nonequilibrium Greens function approach is used to initially validate all of the device parameters.The thin-layer mobility model is used to take interface mobility degradation phenomena into account.The quantum drift-diffusion model (QDDM) from Visual TCAD is also used in the simulation, and it takes into account the quantum effects at lower nodes.The structure and their corresponding parameters are considered, as mentioned in Table 1, during simulation.

III. RESULTS & DISCUSSION
The GAA structure is designed and calibrated with experimentally fabricated device characteristics to validate the considered models during simulation [19].The calibration shows that the simulated drain current (I D ) and experimental data have a reasonable degree of agreement, as shown in Fig. 2.
The same geometric characteristics as the fabricated device structure are used to generate a quad gate junctionless FET (QGJLFET) using a 3D visual TCAD device simulator.The DC transfer characteristics are obtained by obtaining drain current at a gate voltage range of 0 V to 1.2 V by keeping V DS constant at 0.1 V.The findings of the overlapped QGJLFET

A. EFFECT OF QUANTUM MECHANICS FOR PROPOSED DEVICE
As the proposed device's channel length is 30 nm, the initial classical model is simulated using the same design parameters as those in [19] in a visual TCAD platform environment with gate voltage variations between 0 and 1.2 V at a constant VDS of 0.1 V in linear and 0.75 V in the saturation region.The quantum mechanical implications of the same model have also been considered and implemented under the same voltage conditions.In Fig. 3, the impact of both models' outcomes is examined and highlighted.The obtained threshold voltage by utilizing the quantum model is 0.067 V less than the classical drift-diffusion model.When the quantum correction model is employed during simulation, the off-state leakage current soars and the on-state current is also decreased.Tables 2 and 3 present the comparison results for the linear and saturation results for OFF current, ON current, and I ON /IOFF current for the classical and quantum models.
The I ON of 8.692× 10 −8 A is obtained while operating the device in linear mode for the classical drain current

B. DEVICE PERFORMANCE AT RF
This section describes in detail the analog performance measurements used in the investigation.During simulation, physical models such as band-to-band tunneling (BBT), Lombardi mobility, drift-diffusion, and the carrier recombination mechanism have been considered.The Poisson-Schrodinger equation has not been solved as the density gradient model is used to deal with quantum confinement effects.
Transconductance (g m ) effectively converts voltage into current and is a measure of device amplification.It is the change in drain current towards fluctuation of voltage at gate (VGS) by keeping V DS constant as per (1).
Fig. 4 depicts the corresponding g m plot with V GS in the range 0 V to 1 V for the quantum and classical models at a constant V DS of 0.1 V.The plot displays a peak g m of 21 μS at V GS of 0.8 V with the classical drain current model and a peak gm of 20 μS at VGS of 0.9 V with the quantum drain current model.Compared to QDDM, the classical model exhibits better g m and ensures better gain and amplifying capabilities.
Output conductance (g d ) effectively converts voltage into current and is used to measure device efficiency.It is assessed as a change in the ratio of source voltage to a change in drain current at a specific value of V g .It is written as in (2).
The variation of g d with V DS for the quantum and conventional models is demonstrated in Fig. 5.The saturation zone has undergone a thorough AC investigation with a drain to source voltage (V DS ) set to 1 V.For analog applications, a low g d value is desired since it enables better DIBL and channel length modulation by increasing the device's inherent gain.The outcome demonstrates that the quantum model's output conductance exhibits a better lower g d value of 5E-07 than the classical model, which exhibits a higher g d of 6.5E-07.The intrinsic voltage gain of a device is the maximum possible voltage gain of the device.Calculating intrinsic gain (Av) is the ratio of g m and gd.Fig. 6 shows the variation in intrinsic gain with respect to gate voltage (V GS ), as seen in ( 3), with the drain bias held at saturation 1 V.
In contrast to the classical model's gain value of 14, the quantum model's intrinsic gain displays a higher gain value of 27.The intrinsic gain is noticed almost double for the QDDM  model, which clearly shows the efficiency of the proposed model.For both the quantum and classical models, the intrinsic gain plot is shown in Fig. 6.The intrinsic gain and early voltage (V e ) of analog circuits should be high, as given by ( 4), whereas the g d should be low.
The early voltage of the quantum model shows the higher voltage of 17 V than the classical model of 15.9 V with fixed VDS of 1 V and varying V GS 0 V to 1.2 V. Fig. 7 displays the variation of Ve for the quantum and classical models.

C. POTENTIAL DISTRIBUTION IN CLASSICAL AND QUANTUM DEVICE
To ensure consistent charge carriers throughout the channel and prevent channel leakage current, it is crucial to forecast potential distributions over the channel and core.The potential  distribution over a Quad gate quantum effect with gate oxide stack is illustrated in the following 3D view of both models.The Nano-sheet device structure is assessed by contrasting the quantum and classical results.
Figs. 8 and 9 display the potential distribution inside the channel for conventional quad gate nanosheets and QDDM quad gate oxide stacking nanosheets, respectively.Over the channel's surface and in the center, the potential is constant.Because of its link to vacuum potential, the potential redistribution in the channel has a negative value.

D. GATE CAPACITANCE (C GG )
The total gate intrinsic capacitance (C intr ) is the sum of the gate to source capacitance (C gs ) and gate to drain capacitance (C gd ).The C gd is miller capacitance or parasitic capacitance.The C gg = (C intr + C para ) and C gd values are low for FinFET compared to Nanowire FET and NSFETs.Delay in switching results from a high capacitance value.A low value of C gg is crucial for improved RF performance and a faster switch.The total gate capacitance is obtained during AC simulations with  1MHz input frequency.According to Fig. 10, the C gg value is shown to be in the range of 10 −18 F.

D. CUT-OFF FREQUENCY (F T )
The unity gain cutoff frequency, a critical RF design parameter based on transconductance and total gate capacitance, can be represented using (5).
Higher peak frequencies and greater susceptibility to highfrequency impulses characterize devices that are well suited for frequency-switching circuitry.The analysis showed a maximum f T of 9.03 GHz at V GS = 0.8 V for the QDDM model, which is double that of the classical model, as shown in Fig. 11.The higher cut-off frequency helps the device to work in high-frequency device applications.
HfO 2 is now added to the gate oxide stack as a high-k material to emulate a quad gate using a gate oxide stack junction-less Nano-sheet P-type device.The thickness of HfO 2 and SiO 2 are both 1 nm, while all other oxides have a thickness of 2 nm.For the effective oxide thickness (EOT), it is 1.156 nm.The transfer characteristics for both N-type and P-type devices with gate oxide stack Nano-sheets are displayed in Fig. 12 and matched with the precise origin and node.Using a gate oxide stack Nano-sheet, the output characteristics for N-type and P-type quad gates are simulated over a range of VGS, including 0.8 V, 0.9 V, and 1 V, and presented in Fig. 13.
Both N-type and P-type Gate stack Junction-less FETs are arranged as shown in Fig. 14 to be operated as a complimentary logic to test for inverter application.The inverter's structure and transient response have been examined using a logic pulse delivered to maintain V DS at 1 volt.

FIGURE 2 .
FIGURE 2. TCAD device calibration using experimental data at V DS = 0.1 V.

FIGURE 3 .TABLE 2 .
FIGURE 3. Transfer characteristic of the device at V DS = 0.1 V for quantum and classical models.TABLE 2. Comparison of Performance Parameters of Both the Models

TABLE 3 .
DC Analysis Parameters for Classical and Quantum Analysis model, while I ON is slightly smaller with the quantum model.Moreover, the linear model shows better I ON compared to the quantum model due to better electron mobility.Whereas while device operating in saturation mode shows exactly the inverse.The I OFF of 2.791×10 −20 Amp and 1.795×10 −19 amp are obtained while the device is operating in linear mode and saturation mode, respectively, for the classical drain current model.Similarly, I OFF of 1.654×10 −21 Amp and 2.378×10 −19 amp are noticed while operating the device in linear mode and saturation mode, respectively, for the tum drain current model.Hence, the highest I ON /I OFF ratio of 4.11×10 13 is obtained for the quantum model during the linear operating mode of the device.

FIGURE 4 .FIGURE 5 .
FIGURE 4. Transconductance plot for both the models at V DS = 0.1 V.

FIGURE 6 .
FIGURE 6. Intrinsic Gain plot for both the models.

FIGURE 7 .
FIGURE 7. Early voltage comparison among both the models.

FIGURE 8 .
FIGURE 8. Potential distribution of the classical structure over the core and surface.

FIGURE 9 .
FIGURE 9. Distribution of quantum structure's potential over the core and surface.

FIGURE 11 .
FIGURE 11.Variation of f T with V GS .

FIGURE 12 .FIGURE 13 .
FIGURE 12. Transfer characteristics for classical and quantum N and P type devices at V DS = 0.1 V.
Fig. 15 displays the transient response of the classical Quad gate and QDDM Quad gate.During circuit simulation, the inclusion