Metallic CNT Tolerant Field Effect Transistor Using Dielectrophoresis

The performance of silicon-based transistors is reaching its limit, and new materials like carbon nanotubes (CNTs) have started emerging to replace them in electronic products. However, the precise manipulation of CNTs requires complicated techniques, which increases process variation. These variations can lead to a decrease in the overall yield of the field-effect transistor (FET). This study shows how a low-frequency signal may regulate the number of CNTs on electrodes with a nanometer scale. We also demonstrate using an interdigitated electrode to reduce the shorts caused by metallic CNTs. The fabricated CNFETs were characterized using SEM, AFM, and I-V measurements. The study also demonstrates how the duration and amplitude of the applied signal impact the density of CNTs on the electrodes. Finally, finite element analysis was used to evaluate the electric field parameters during DEP. This technique will lead to precise CNTs per unit area, which can help fabricate transistors, sensors, and other electronic components.


I. INTRODUCTION
Fast approaching limitation for scaling silicon-based fieldeffect transistors (FET) for applications such as the internet of things (IoT) has begun an expedition beyond siliconbased materials. The exceptional mechanical and electronic properties of quasi-one-directional carbon nanotubes (CNTs) prove to be a frontrunner in advanced nanoelectronics. Its use in hybrid CNT-silicon applications [1] ranges from small sensors [2] to microprocessors [3]. However, CNT-based fabrication faces an obstacle of deposition and alignment. Additionally, building high yielding and promising nanoelectronics fabrication process is dependent on high-quality, clean, and defect-free CNTs. CNTs can be grown directly on substrate wafers using catalysts like iron, nickel, etc. [4], which can be either dispersed catalysts or pattern catalysts, followed by growth under high temperature; this technique is based on chemical vapor deposition (CVD). CVD processes have been developed and used to fabricate FET. Still, a high-temperature requirement, around 900°C, provides a stumbling block as it is not compatible with contemporary metal-oxide-semiconductor (MOS) technology [5].
Therefore, an attractive alternative to CVD is a post-CNT synthesis-based fabrication process that can be performed at room temperature [6] and is compatible with the existing MOS fabrication process. However, most work is directed toward using polymers that can degrade the intrinsic properties of CNTs essential in the nanoelectronics [7]. In this work, we implemented a layout design approach of interdigitated electrodes to reduce variation in the fabrication process. The article has been divided into four sections: the first section discusses the metallic CNT tolerant FET structure; the second section discusses dielectrophoresis and ideal simulation of the process; the third section mentions the fabrication process which is used in this work and the final section mentions the result and analysis of this article.

II. METALLIC TOLERANT CNFET
The concept of a carbon CNFET is similar to that of a metal oxide semiconductor field-effect transistor (MOSFET). Analogous to MOSFET technology, CNFET also contains two terminals: source and drain, where the flow of electrons occurs. This carrier flow is controlled by a third terminal attached to the voltage, also known as a gate; applying a vertical electric field, the gate terminal changes the current flow between the source and the drain. A gate can be configured into two forms: back gate (BG) and top gate (TG); in this work, we have used BG-configured CNFET.
The current in CNFETs is formed by the tunneling of charge through the intersection of the Schottky barrier created between the CNT and source/drain metal. The Schottky barrier height is essential in determining the tunneling of carriers, which depends on the work function of the metal and CNT Fermi level. Since the CNT with a diameter of 1.4 nm (CNTs used in this work) has a fermi level energy close to 4.5 eV, we have chosen Palladium (Pd) as a source and drain metal. It has a work function of 5.2 eV between the bands of the CNTs. Nevertheless, it is high enough to form a thinner barrier for easy tunneling. Gold (Au) and Pd have similar work functions. But, the metal carbide bonding between the CNT and Au is not as good as that of CNT and Pd [8], which can result in dispersion at the contact region. The difference can be seen in supplementary data. Hence Pd was chosen over Au. The generation of CNTs is a stochastic process and involves the separation of metallic CNTs (m-CNT) and semiconducting CNTs (s-CNTs). The electrode design is based on increasing the probability of s-CNT landing on the electrode. Since the CNFET is dependent only on s-CNTs [9], therefore the probability of the CNFET (P CNFET ) is equal to the number of s-CNTs in a batch of CNTs (n), P CNFET = P semi_cnt n (1) where P CNFET is the probability of fabricating CNFET, P Semi_cnt is the probability of t s-CNT, and n is the number of CNTs per CNFET.
The electrode design is conceptualized on the interdigitated resistor and relays [10], shown in Fig. 1. The x-direction (row) increases the probability of combating shorts, so it ensures that there is at least one semiconducting CNT in the series. Therefore, the probability of finding a semiconducting CN-FET is given by: where x is the number of CNFET in a row, and P row is the formation of CNFET in a row. Row connection increases the probability of placing a semiconducting CNT within the electrode. However, it decreases the current drive. Consequently, a network of parallel CNTs is required to increase the current drive. Therefore, it becomes crucial to strategically employ correlated and uncorrelated redundancies so that the CNFET is more m-CNT tolerant and gives a high current drive [9].
Since the bundle of CNT is a mixture of metallic and semiconducting CNTs, therefore the mean of the current is given by where μ s and μ m are the mean of current flowing through semiconducting and metallic CNTs from source to drain, respectively; I m and I s is current in metallic and semiconducting CNTs; f sd is the Fermi-Dirac function of semiconducting CNTs, and f md is the Fermi-Dirac function of metallic CNTs [11]. So, in a transistor, if there is a mixture of metallic and semiconducting CNTs, then the mean current of the transistor can be expressed as where p s and p m are the average fractions of semiconducting and metallic CNTs. Therefore, if the fraction of m-CNTs is higher, the characteristic curve will be more linear, whereas if the s-CNTs' count is higher, a saturation region will be achieved.

III. DIELECTROPHORESIS
Dielectrophoresis (DEP) is one of the methods [2], [12] which provides a promising solution for placing and aligning the nanomaterials at the desired location. The principle of DEP is based on manipulating the nanomaterial in a liquid medium by applying a non-uniform electric field that leads to the polarization of the nanomaterial and its immersion solution.
Due to the formation of the dipole on the object and the non-uniformity of an applied electric field, the forces exerted do not compensate for each other, which makes a translational movement of the object. DEP approach offers the advance of processing CNFET at ambient temperature. The process can be performed by applying an electric field generated from low voltages, using the electrodes separated by a few nanometres. In addition, several parameters, such as the duration of an alternating field, frequency, and amplitude, can be adjusted to optimize the number of aligned CNTs. The Dielectrophoresis force acting on the CNT length is expressed using [13]: where F DEP is dielectrophoresis force, l is CNT's length, r is CNT's radius, E is the electric field between the electrode, and f cm is the Clausius-Mossoti factor, which represents the complex permittivity of particle and medium. Therefore, this process depends on the medium's conductivity and voltage frequency. According to alternating current electro-osmotic (ACEO), charge flow during DEP increases the conductivity across the CNTs and the solution in which it is dispersed. So, for better manipulation, we can decrease the signal frequency, as it increases the polarizability of the CNT and reduces any electrochemical reaction. During the process, force is influenced by the electro-thermal effect [14] and the van der Waals [15] forces. The electro-thermal force is the summation of the force of attraction due to Coulomb force and dielectric medium (suspension liquid strength), which is given by the combination of both forces: where ς is the relaxation time of particles and ω is the frequency of the pulse. Though Electro-thermal force is the summation of Coulomb force and dielectric force, Coulomb force dominates at a low frequency, whereas dielectric force dominates at a higher frequency.
The dielectrophoresis circuit used in this work is shown in Fig. 2. It is based on the capacitive coupling of the electrode, which helps in self-limiting single-nanotube assembly. The circuit connection was chosen to provide capacitive coupling to the adjacent electrode to provide a less intense electric field. This circuit for DEP depends on the thickness of the oxide and the distance between the electrodes, as a low-frequency signal is applied across the substrate. As a result, DEP provides advantages over other methods like spin-casting and chemical vapor deposition by providing more control over the position of a higher-quality carbon nanotube. This alignment method is also a cheaper and time-efficient option for fabrication compared to CVD.
To find a suitable frequency, we performed finite element analysis (FEA) of the electrode design using HFSS shown in Fig. 3. It was noted that as we increased the frequency of DEP, electric field intensity around the sample augmented, especially around the corners of the nanoelectrodes, where it increased significantly. Fig. 3(a) shows DEP simulation at 50kHz; at this frequency, the stray electric field intensity is minimum, and a uniform field is observed between the electrode, where the CNTs are present. Thus, helping in the CNTs' orientation. However, in Fig. 3(b), when the frequency increases from 50 kHz to 150 kHz, the electric field simulation becomes non-uniform, mainly due to the parasitic electric field. This parasitic electric field is high around the corners of the nanoelectrode, which can be seen in the simulation. Fig. 4(a) shows the SEM images of DEP performed at 50 kHz and 150 kHz on 300 nm SiO 2 , which reflects results from the simulated FEA. Table 1 shows the parameter used to model CNTs within the HFSS. During the simulation, we didn't consider the Brownian motion, which can lead to particular unsolicited CNTs. In addition, the signal duration wasn't considered in the simulation. Still, as signal time increases, the dipole across the CNTs increases, and more CNTs are attracted. Therefore, for experimental verification, time was

TABLE 1. Parameters Used for Simulating CNT in DEP
kept as a parameter. We did iterations to find an appropriate time for the duration of the signal. We kept the evaporation time of NMP to be constant, after which we transferred samples to a hot plate as the solution had a very long evaporation time. The Brownian motion could have made the result more variable. We observed that as the signal increased, proportionally CNTs got attracted to nanoelectrode. Fig. 5 illustrates the process flow used for fabricating nanoelectrodes and CNT deposition, which is explained in detail in the following sections. Before starting the fabrication process, the silicon wafer was cleaned using a buffer oxide etching (BOE) procedure, after which 300 nm of silicon dioxide (SiO 2 ) was grown on the wafer. To remove oxide formation from the backside of the wafer, BOE was again performed, while the top side was covered with photoresist. Next, electrode patterning was done using the overlay method on Raith's electron beam lithography (EBL). The first step was to expose a big pattern followed by developing in Methyl Isobutyl Ketone (MIBK): Isopropyl Alcohol (IPA) 1:3 solution at 20°C for 3 minutes. Then, exposure to small patterns (nanoelectrodes) is followed using the same developing process. This was done to speed up pattering time. Finally, the bi-layer resist was used to provide a good undercut layer and make the lift-off procedure easier and cleaner.

IV. FABRICATION AND CHARACTERIZATION
The metal deposition was done using the Angstrom Engineering evaporator. Palladium (Pd) has a low adhesion with the oxide surface due to a low noble metal-oxygen binding energy [19]. Since Pd had to be deposited on silicon oxide, an adhesion layer was used between silicon dioxide and palladium to have a better adhesion between the two interlayers. For better adhesion, two metals were tested: Chromium (Cr) and Titanium (Ti). After a series of deposition and scotch tape tests, Ti was a better option than Cr.
In this work, we used Raymore Nanointegris's SuperPure CNTs industries' CNT film, which had bundled CNTs because separating individual CNTs without functionalizing them is difficult. In this work, we used different solutions to disperse the CNTs to keep CNTs pristine. Based on the best CNT dispersion of CNTs in a solution, we have used NMP (Nmethyl-2-pyrrolidone) after trying other organic solvents like chloroform, 12-dichloroethane, and IPA. The only observed disadvantage of NMP is the high vaporization temperature which makes the deposition more variable due to the Brownian motion of the CNTs. To prepare the solution, an ultrasonic bath (Elmasonic P-sonic bath) was chilled using the ice pack until it reached 11°C.
This was done to mitigate the exothermic nature of the process, which can cause the water temperature to rise to 40°C. After dispersing CNTs in NMP solution, DEP was performed at 50 kHz for 7 seconds, after which the solution evaporated for 5 minutes. Following that, to decrease the processing time, the substrate was heated at 100°C.
The characterization setup, shown in Fig. 6, is made using the Everbeing Probe station, having a titanium probe with 5 μm connected to a system for monitoring the position of the probes. Keysight B2900A was used for measuring, and a constant DC supply (Korad 3005D) supplied the gate voltage. The designed electrode displays good results and exhibited a good Schottky and ohmic contact transistor with reproducibility on 8 wafers out of 10. Fig. 7(a) shows the I d -V d characteristic of the transistor and displays a good ohmic region with low output current.
The sample was annealed to increase the characteristic current by forming a stronger connection with the electrode. The annealing process was an essential step in enhancing the performance of the CNT transistor, but determining the optimum temperature is critical. If the temperature is above 800°C, the metal for the contact becomes too soft and deforms or seeps into the silicon. On the other hand, if it's low, the metal-carbide bond is not formed, and the contact resistance between CNT and metal is not reduced because of the wetting effect [20]. Therefore, after iterations, rapid annealing was done at 350°C in this work.
The fabricated transistor can only work above the threshold voltage of the CNFET, that is, where it enters the linear region. This is because the current flowing through the Schottky Barrier in the linear region is not mainly affected at the source end while varying the gate voltage. Instead, the tunneling in the barrier is controlled by the drain side of the transistor.
Therefore as the source to drain voltage increases, the drain Schottky barrier decreases in width, and there is a linear increase in the current. As shown in Fig. 7(a) and (b), we can notice that as we increase the gate voltage, the slope of the I d v/s V ds curves increases linearly in the linear region. The slope is proportional to the current change rate over the drain to the source voltage. When no barrier exists, CNFET transitions to saturation region. Fig. 7(b) shows saturation current for 10 V gate voltage is 4nA, after which the current remains relatively constant. Furthermore, we can notice that p-CNFETs show a better saturation region n-CNFETs because of the oxygen charge trapping, which under the ambient atmosphere makes an electron [21].
To improve the design, oxide thickness could be reduced from 300nm. Consequently, the gate voltage would significantly control the Schottky tunneling compared to a thicker gate oxide [22]. Additionally, the drain to source voltage needs to be highest to have a large output swing; however, the CNTs burn off in that case. Therefore, these regions depend on the gate-source and drain-source voltage. An increase in the drain voltage beyond leads to the heating of the CNTs, which burns off between 4.5-5 V. This is also known as the electrical annealing [22], but it also damages the semiconducting CNTs. Fig. 8 compares the performance of produced devices to the parametric Stanford device model currently in use [23], [24]. Due to a mixture of m-CNTs and s-CNTs, the output characteristics still don't exhibit a good saturation area, but they do show a good overlap in the linear regime. In addition, the probability of the current passing through the s-CNT was boosted by the interdigitated electrode design for CNFETs. The results can be improved by changing the array of fingers in interdigitate electrode based on (2) and the purity of CNTs produced.

V. CONCLUSION
This article presented a process flow for fabricating a back gate CNFET using dielectrophoresis which can be innovative for VLSI applications based on CNTs. The presented CN-FET, which displayed a triode regime, was fabricated using electron-beam lithography on a bi-layer resist followed by metal deposition and characterized using two probe methods, AFM and SEM. Subsequently, CNTs were deposited between the interdigitated electrode using the DEP by a low-frequency AC signal. The frequency for DEP was derived from finite element analysis using ANSYS HFSS, so the parasitic electric field is minimized around the electrode, which helps in the alignment of CNTs. As a result, the fabricated CNFET electrode had a reproducibility of 80% (wafer to wafer). Moreover, the interdigitated electrode design helped make devices tolerant of metallic CNTs while having a good current drive. A significant change in the IV characteristics was also observed after the annealing at 350°C. Advancing the process mentioned in this article can produce VLSI-based circuits or sensors at a lower cost.