High-Speed and High-Performance Continuous-Time ADCs for Automotive Receivers

This article presents an overview of high-speed and high-performance continuous-time (CT) ADCs with a special attention to the application field of automotive receivers for broadcast radio and radar. An overview of the CT ADC architectural space is presented and the key design challenges related to high linearity and broadband signal conversion are described. Insights are given in the architectural and design choices to accomplish high-end performance points. A selection of case studies is presented that achieve state-of-the-art performance metrics with respect to linearity, bandwidth, and power efficiency.


I. INTRODUCTION
T HE RATIONALE behind the choice for a continuous- time (CT) ADC is related to its features and the application requirements.The key aspect of a CT ADC is that it does not have an input sample-and-hold circuit.Instead, the input is usually a resistor or a high-ohmic gate.A resistive input can be made highly linear and commonly does not require a high-power driving circuit.A CT pipeline ADC does have a sample-and-hold circuit connected to the input, but it is outside the signal path and can have a very small capacitance as the noise and linearity (and aliasing) contributions are canceled in the digital domain.Essentially, all CT ADC topologies provide inherent anti-alias suppression by filtering or cancellation.
Second, the combination of oversampling and noiseshaping results in very small in-band quantization errors without the need for a high-resolution quantizer.Also, thanks to the oversampling and low-resolution quantization, static and dynamic calibration as well as dynamic element matching (DEM) techniques can be effectively employed to achieve very high linearity.This has been demonstrated in many excellent audio ADC designs [1], [2] and recently <−100 total harmonic distortion (THD) has been shown feasible in CT ADCs with bandwidths exceeding 100 MHz [3].If the quantization errors are sufficiently randomized by the delta-sigma modulator (with optional dithering), exceptionally good spurious performance can be realized.
Moreover, as a CT delta-sigma modulator employs a lowresolution oversampled quantizer and DAC in a high-gain feedback loop, it only has few critical components, that do not require slow complex calibration loops.
All features described above are essential for automotive receivers that must meet the extremely demanding requirements for "analog broadcast" applications, such as AM/FM radio and FMCW radar sensors.Modern wideband AM/FM radio receivers digitize the complete AM or FM bands that contain many narrowband channels that can have 100 dB difference in dynamic range.Therefore, the ADC needs to provide <−100-dB THD in over 100-MHz bandwidth so that harmonic or intermodulation tones do not noticeably interfere with weak wanted channels.For FMCW radar receivers, a similar SFDR requirement of >100 dB applies to ensure that tones are low enough not to be detected as a false target.
This article presents the designs of state-of-the-art highspeed and high-performance CT ADCs for automotive receiver applications.In Section II, an overview of the different CT ADC architectures is given.In Sections III and IV, the main design aspects related to high precision and high speed are described in more detail.In Section V,

II. CONTINUOUS-TIME ADC ARCHITECTURES
The main design parameters of a CT ADC are: the number of bits b, the oversampling ratio OSR or sampling frequency Fs, the number of stages m, and the order of the system n.Fig. 1 shows an overview of the chosen parameters of CT ADC designs from ISSCC 1997-2022 in the bandwidth range from ∼10 MHz to 1 GHz.Roughly three architectural regions can be identified.For bandwidths up to ∼150 MHz, mostly 3rdor 4th-order single-loop (1-stage) delta-sigma modulators are used (and a few 6th-order bandpass modulators) and different tradeoffs have been made by designers between the number of bits and sampling frequency.In the frequency range from 150 MHz to ∼500 MHz, multistage CT multistage noiseshaping (MASH) architectures [4] are used with 2 or 3 stages and a (maximum) order per stage of 1 or 2. For the highest bandwidth designs in the 800 MHz-1 GHz range, the order has reduced to 0 which are CT pipeline architectures [5].With the increase of the number of quantization stages, the number of bits scales up accordingly, up to 20 bits for the 1-GHz design in [6].
In the following, the different CT ADC architectures are briefly introduced, and the most important design aspects are identified.

A. SINGLE-LOOP DELTA-SIGMA MODULATOR
Fig. 2(a) shows a simple block diagram of a single-loop CT delta-sigma modulator that consists of a CT loop filter H(s), an ADC, and a feedback DAC.The output of the DAC is subtracted from the input signal X and the error signal E is fed to a loop filter.The output signal of the loop filter is digitized by the ADC that is oversampled.The digital output Y of the delta-sigma modulator contains the input signal X and the quantization error Q that are filtered by the signal transfer function (STF) and noise transfer function (NTF), respectively where the STF magnitude in the signal band of interest is approximately 1, and the NTF magnitude is approximately inversely proportional to the loop filter transfer.
The key design parameters that determine the in-band quantization noise are the total number of ADC bits b, the loop filter order n, the maximum out-of-band (OOB) NTF gain NTF max , and the oversampling ratio OSR.
An important constraint for the design freedoms is the stability requirement of the feedback loop.At increasing clock rates, the (signal-dependent) latency of the core ADC will increase the probability of metastability events and eventually the loop will become unstable.Unlike digital signal applications, for analog AM/FM radio, a metastability error can lead to an audible signal and therefore their occurrences need to be minimized by design.Excess loop delay (ELD) compensation [7] is a technique to improve loop stability in the presence of such extra delay or phase shift.Fig. 2(b) shows an example of a delta-sigma modulator with an ELD compensation loop around the ADC to maintain loop stability in case of 1 clock period (z −1 ) latency of the ADC.
The design of the NTF is also constrained by stability requirements.A higher NTF max leads to improve quantization noise suppression at lower frequencies as shown in the example of Fig. 3.However, a higher NTF max also results in higher OOB quantization noise power and therefore a lower maximum stable input amplitude (MSA) level of the modulator.A too high NTF max can lead to instability of the modulator even without an input signal.
When increasing the number of bits b, for a given NTF, the MSA that can be handled by the delta-sigma modulator will become larger, as the quantization error becomes smaller.This increase of MSA can be tradeoff for better in-band quantization noise suppression by increasing the NTF max (Fig. 3).
Another design freedom is the order of the NTF.Increasing the loop filter order n will lead to a steeper quantization noise slope and lower noise at low frequencies as shown in Fig. 4. At the same time, for increased n, the cutoff frequency f c  will shift to lower frequencies due to the stability requirement of the feedback loop.In case f c moves too close to the signal bandwidth, the in-band quantization noise will severely degrade.

B. MULTISTAGE NOISE-SHAPING
The stability constraints of the NTF design can be alleviated by employing a cascaded configuration of multiple single-loop delta-sigma modulator stages in a pipelined MASH architecture as shown in Fig. 5.In a MASH ADC, the higher-order stage processes the quantization noise of the previous stage.A replica of the quantization noise Q1 is generated by feeding the digital output Y1 of ADC1 to an interstage DAC (iDAC1) and subtracting it from the ADC1 input signal.The replica Q1 is fed to a next stage via an (optional) interstage gain G.In the 2-stage example of Fig. 5, the output data streams Y1 and Y2 equal (2) Both output streams contain quantization error Q1 but with different filter functions.The filter transfers can be equalized by filtering Y1 with STF2 and Y2 with NTF1/G, respectively.After equalization the data streams are subtracted and Q1 will be canceled.The final data stream Y equals where the input signal X is filtered by the STFs of both stages and the quantization error Q2 is filtered with both NTFs.In general, in an ideal m-stage MASH ADC, the input signal X will be filtered by the STFs of all m stages, while the quantization errors of the first m − 1 stages will be canceled and the quantization noise of the final mth stage will be filtered by all m NTFs.The precision of the quantization noise cancellation is limited by the (frequency-dependent) mismatch between the analog and digital filters [8].
In Fig. 6, the NTFs of a single-loop 4th-order delta-sigma modulator and a 2-2 MASH with two 2nd-order stages are compared.Both NTFs have 4th-order noise shaping, while the NTF of the MASH demonstrates much deeper suppression of the quantization noise.The reason for this difference is that the MASH architecture is based on the NTFs of two 2nd-order modulators that can be designed with a higher f c compared to the 4th-order NTF of the single-loop modulator.As the total order of noise shaping and the order of the stages and the associated stability requirements can be chosen independently, a MASH ADC can achieve higher bandwidths than a single-loop architecture.

C. CONTINUOUS-TIME PIPELINE ADC
Even though a high-order MASH architecture can be constructed with low-order loops, the stability requirements, although relaxed, still apply and are a limit for the maximum sampling speed of the modulators.To eliminate the stability constraint, the MASH architecture can be modified by removing the feedback loops and loop filters, leaving the CT pipeline architecture as in Fig. 7. Conceptually, it is similar as a MASH ADC where the quantization noise of all stages, except the last one, are canceled in the digital domain.What remains is the quantization noise contribution of the last stage that, as the noise-shaping loops have disappeared, is only suppressed by the interstage gains and oversampling ratio Without the concern of stability, the achievable bandwidth of a CT pipeline ADC can be higher than a MASH ADC.
It is noted here that a "hybrid" implementation of a CT pipeline ADC can combine different front-and back-end ADC topologies, like for example a 0-X MASH [9], [36] or a VCO-based CT pipeline ADC [5].
To maximize the interstage gain G, the signal content in the residue signal Q1 should be suppressed below the quantization error.This is very challenging to realize for broadband (GHz) bandwidth conversion and will be discussed in more detail in Section IV.

III. HIGH-LINEARITY DAC DESIGN
In this section, we will focus on the challenges associated with the design of a high-linearity DAC in CT ADC architectures.Fig. 8(a) shows a simple block diagram of a CT delta-sigma modulator, including a loop filter, an ADC, and a feedback DAC embedding a decoder.Typically, the DAC output lands on a virtual ground node of the loop filter.The accuracy of a CT ADC is ultimately defined by its feedback  DAC.The main design parameters of a DAC are the number of bits b, the sampling frequency Fs, and the coding scheme unary/binary/segmented.However, the main design parameters often overlook the challenges associated with designing a high-linearity DAC.This is because achieving accurate digital to analog conversion over a wide frequency range (0 to Fs) necessitates a thorough understanding of errors sources.Irrespective of the number of bits, DAC error sources can be listed as: thermal noise, static and timing mismatches, intersymbol interference (ISI), output impedance, clock jitter, clock spurs, metastability, referencerelated artifacts (supply rejection, reverse isolation, reference output impedance, supply, and ground isolation, package impedances), and artifacts caused by data-dependent switching activity (i.e., depends on decoder and/or DEM coding scheme.For example, a 1st-order data-weighted averaging (DWA) generates more data-dependent artifacts than random DEM and thermometer-coded DAC schemes [10]).Fig. 8(b) illustrates a high-linearity DAC architecture where requirements on each sub-block increase as we go from the decoder to the output stage.For example, a 1-bit DAC is (theoretically) linear and does not need a DEM block.However, to realize <−100-dB THD in 25 MHz techniques, such as reference side switching resistive DAC, integrated series-shunt LDO with low output impedance, pass-gate-based returnto-open retimer with embedded low jitter clock buffers, and low-ripple DAC driver have been implemented [38] as shown in Fig. 9.
For a multibit implementation, static and timing mismatches need to be corrected to achieve a high linearity.Table 1 lists the coding schemes applicable to a multibit DAC implementation.The unary coding scheme is often used for designs with less than 4-5 bits.DAC mismatch errors can be corrected by employing analog calibration, digital correction, or DEM techniques.In case of 5 bits or more the complexity of the (α 2 N − 1 ) and the latency introduced by decoders required by DEM limit their use cases, especially for wide bandwidth applications.To circumvent these limitations, the binary coding scheme can be utilized, however, the redundancy present in a unary coding scheme is not available anymore, and therefore DEM techniques cannot be implemented.Analog calibration or digital correction techniques can be used to improve the linearity of the modulator but require an auxiliary circuitry to estimate mismatch errors.Furthermore, an SAR-based (binary coded) ADC can be implemented to simplify ADC to DAC interface.
An interesting direction is employing a segmented DAC architecture where the number of bits can be increased beyond 5 bits where the MSBs of the DAC are implemented using the unary coding scheme and the LSBs of the DAC are implemented by using a binary scheme.This implementation choice makes it possible to utilize DEM techniques to MSB branch and mismatch error shaping techniques to LSBs [26], [27].
Fig. 10 presents the -THD of CT ADC designs, covering the period from ISSCC 1997 to 2022 and JSSC 2012 to 2023.The analysis focuses on resistive 1-bit, resistive multibit, and current steering multibit DAC architectures and examines static and dynamic linearization techniques.
In Fig. 10(a), three distinct regions can be observed regarding DAC architecture.For designs targeting BW<1 MHz, most designs employ resistive DACs, with their THD dependent on the output impedance of their references.Achieving lower output impedance is relatively easier for low-frequency applications.In the BW range of 1-120 MHz, both resistive and current steering DACs are utilized.Notably, the current steering DAC with the highest reported THD implements techniques to reduce data-dependent artifacts inherent to the current steering DAC architecture.This includes employing reduced switching rate data-weighted averaging and low ripple DFF designs, achieving a THD of −104 dBc at a frequency of 2.2 MHz [13].On the other hand, reference-side switching resistive DACs achieve significantly better THD over wide frequency ranges since their output impedance is independent of the input data [3].However, for signal BW larger than 120 MHz, current steering DACs are preferred.It is important to note that the differential output impedance of a current steering DAC depends on its input data due to the presence of switches at its output, which limits the maximum achievable THD.The choice of the DAC architecture aligns with the research work published for stand-alone high-speed DACs, which typically require a large number of bits.The trendlines depicted in Fig. 10(a) suggest that resistive DACs have the potential to achieve superior THD compared to current-steering DACs for BW exceeding 100 MHz.
To provide a comprehensive understanding of linearization techniques, it is crucial to classify the underlying error sources.Static errors arise from device mismatch within each DAC unit element, while dynamic errors are intricately linked to the input signal frequency, encompassing phenomena, such as ISI, timing mismatch, and data-dependent supply ripple.By recognizing and categorizing these error sources, we can effectively address them through appropriate linearization methods.
In Fig. 10(b), DAC linearization techniques are classified into three domains: 1) designs employing no linearization; 2) static linearization techniques; and 3) dynamic linearization techniques.Designs without any linearization are multibit designs where each DAC unit is scaled to achieve the desired matching.However, reporting single measurement results for these designs does not capture the statistical variation of static and dynamic error sources.Nonetheless, these designs help establish a trendline that illustrates a 10-dB/dec THD performance line.Below this line, the maximum achievable THD is limited by static error sources, while above it, dynamic error sources become dominant as well.
Static linearization techniques involve the calibration of DAC static errors, either in the analog or digital domain.These techniques include DEM methods, such as random DEM, DWA, and clock-level-averaging (CLA) for VCObased designs [20] and [23].Additionally, the choices of 1-bit and FIRDAC designs are also classified as techniques to reduce static errors.Interestingly, designs employing static linearization techniques closely align with those employing no linearization techniques (pure scaling).Employing static linearization techniques enables the use of smaller devices, resulting in slightly better reported THD over the Nyquist frequency.

IV. HIGH-SPEED RESIDUE GENERATION
In this section, we will focus on high-bandwidth residue generation that is a key challenge in high-speed multistage CT ADC architectures.In order to effectively utilize the range of the backend stages, the input signal component should be suppressed below the quantization level with an attenuation factor G ATT [31] where b is the number of bits of the substage.The residue can be generated by subtracting the quantizer output with its input [Fig.11(a)].Although the two-path residue generation seems straightforward, it brings severe challenges in wideband applications.Due to the processing delay of the quantizer and the ZOH transfer of the iDAC, the signal passing through the quantizer and iDAC experiences a phase shift relative to the quantizer input.As the signal bandwidth increases, the extra phase shift eventually leads to excessive signal leakage to the next stage.The red line in Fig. 12 shows the STF after the two-path connection of Fig. 11(b), for a quantizer delay TD of 1 clock  period.The horizontal dashed line indicates the required attenuation that is needed in case of 4 quantizer bits [31], that is only met in a narrow (3/1000 Fs) bandwidth.
In order to compensate for the phase shift between the two subtraction paths, an analog delay can be inserted at the loop filter output, as shown in Fig. 11(c).By properly selecting the delay of the delay element, the phase shifts of the two paths can be equalized, yielding a much-reduced signal residue.The analog delay element can be implemented with an all-pass filter [32].The blue and green lines in Fig. 12 show the improved STFs when using a 1stand 2nd-order APF, respectively, where <−30-dB attenuation is achieved beyond Fs/10.For higher OOB frequencies >Fs/10, the suppression is limited by the ZOH transfer of the DAC which can be attenuated by a (first-order) lowpass filter in front of the ADC.
Although both CT MASH and CT pipeline architectures require delay matching, there is an important difference regarding the functional implementation of the residue generation paths.In the MASH topology (Fig. 5), the unshaped quantization error Q1 is present at the input (v1) of ADC1 due to the feedback loop operation of the delta-sigma modulator.Therefore, v1 is used to replicate the quantization error and the interstage DAC (iDAC) is to cancel the signal component from v1.In contrast, in the CT pipeline topology (Fig. 7), the quantization error Q1 is present at the output Y1 of ADC1.Therefore, DAC1 is to replicate Q1 while the direct signal path (from X to Q1) is to cancel the signal component.In the following, we will describe the residue generation circuits in a CT MASH and CT pipeline ADC architecture in more detail.

A. CT MASH RESIDUE GENERATION
An important bottleneck in the implementation of the residue generation concept of Fig. 11(a) is the iDAC.Besides its ZOH transfer function, the iDAC also loads a speed-critical node of the feedback loop.Moreover, in case of a low OSR, the gain provided by the frontend loop filter is usually limited.Therefore, the noise and mismatch errors of the iDAC are only marginally suppressed.To tackle all these issues, extra noise budgeting, proper device sizing, and analog/digital correction have to be introduced at the cost of power efficiency and design complexity [33].
It was mentioned in the previous section that the iDAC is not needed for replication of the quantization error but for signal cancellation.An alternative approach is to feed the input signal to the quantizer input to suppress the signal swing at the loop filter output [34].Fig. 13(a) shows an example of a first-order modulator with the signal feed-in path to the quantizer input.However, due to the quantizer ELD in the main feedback loop, a wideband signal attenuation is not achieved.To address this issue, a loop delay matching technique [35] can be used that is shown in Fig. 13(b).The feedforward path is split into two parts, one providing the direct input to the quantizer and the other providing the delayed input to cancel the 1Ts delay signal returned from the ELD path.Similarly, the direct input path also needs to be delayed to cancel the signal returned from the main feedback path.Considering the 1Ts main loop delay and half-Ts DAC waveform delay, the delay element should have a delay of 1.5Ts.This way, broadband signal attenuation can be realized.

B. CT PIPELINE RESIDUE GENERATION
Due to the absence of noise shaping in a CT pipeline frontend stage, the substage ADCs often have more bits than in a MASH ADC.Therefore, a more precise delay matching is required to sufficiently suppress the signal component below the quantization level and maximize the interstage gain.As mentioned before, the substage DACs do not only  introduce extra delay but also shape the data with a ZOH transfer function.To have broadband signal attenuation, a good matching of both phase and magnitude of the two paths is needed.In [36], an analog filter with two poles and one zero is implemented in the delayed path.Other broadband delay compensation techniques have been demonstrated based on an LC line [6], RC lattice [37], and RLC lattice [31] (Table 2).

V. DESIGNS AND MEASUREMENT RESULTS
In this section, we present four CT ADCs with specific state-of-the-art performance metrics.The first two designs demonstrate <−100-dB THD in 25 and 120-MHz bandwidth based on a 1-bit and multibit architecture, respectively.The last two designs are architectural explorations of the CT ADC toward larger bandwidth and ultrahigh power efficiency.

A. 25-MHZ BW CT ADC WITH −102-DB THD
The first example is a single-loop CT delta-sigma ADC that has been designed for 25-MHz bandwidth and <−100-dB THD [38].The block diagram of the ADC is shown in Fig. 14 and comprises a 4th-order loop filter, 2.2-GHz 1-b quantizer (ADC), and 1-b feedback DACs (DAC1, DAC2, and DAC3).The strategy to meet the linearity requirements is the use of a 1-bit DAC with return-to-open switching, to avoid both static and dynamic errors.Even though a 1-bit DAC is (theoretically) inherently linear, there are several aspects that can compromise the linearity.The 1-bit quantizer is highly nonlinear as the output is a square waveform with very strong odd harmonic distortion tones.The harmonic tones are suppressed by the loop filter gain and the randomization effect of the delta-sigma coding, but care must be taken that the resulting harmonics from the 1-bit quantization are sufficiently low.Also, a 1-bit modulator is known to be tonal, especially for small signal input conditions.Therefore, a dither  signal is injected at the input of the 1-bit quantizer via DAC4 to randomize all the (non)harmonic tones.Fig. 15 shows the measured output spectra of full-scale single-tone inputs at 2.5 and 7.67 MHz.The measured THD is −102 dB.Table 3A summarizes the measured results.The measured peak SNDR is 77 dB in 25-MHz bandwidth, IM3 is −114 dBc, and SFDR is >125 dB.

B. 120-MHZ BW CT ADC WITH −101-DB THD
This design targets a bandwidth of 120 MHz with similar resolution and linearity performance as the previous design.As the bandwidth is 5× higher, 1-b quantization is not sufficient to meet the required SQNR, even with a 6-GHz sampling clock.A 2-bit quantizer has been employed to achieve low enough quantization noise.Consequently, the inherent linearity of the DAC is lost, and it will be sensitive to mismatch.The DAC elements are measured and calibrated with a digital error estimation and correction (DEEC) circuit [3].The calibration convergence time is less than 1 ms.Fig. 16 shows the block diagram of the ADC with a 4 integrator loop filter (ω 1 /s−ω 4 /s), feedforward coefficients (c 1 − c 4 ) for loop stability and signal feed-in coefficients (f 1 −f 5 ) to control the STF and internal signal levels.The 2-b quantizer is clocked at 6 GHz and has an ELD compensation   3B.

C. 360-MHZ BW CT 1-1-1 MASH ADC
The next design example aims at another 3× increment in bandwidth.This could be achieved by increasing the number of bits of the previous design to 4 bit, which will be very challenging to design at a 6-GHz sampling rate.Instead, the architectural step to a multistage design has been made based on a cascade of very simple 1st-order 8-level modulators at 5 GHz (Fig. 18).The loop filter of the first modulator is an RC integrator for high linearity and the quantization error replica is directly available at the loop filter output, thanks to the signal feed-in path with the LPF and APF in the input signal path, as described in Section IV.The signal suppression is <−34 dB for in-band frequencies up to 360 MHz and a relatively low interstage gain of 3 is chosen in order not to overload the second stage in the presence  3C.

D. 3.2-MW 40-MHZ BW CT PIPELINE ADC
This design example is a hybrid CT pipeline ADC with a 5-bit SAR input stage followed by a 1-bit delta-sigma modulator back-end stage with an interstage gain of 8 (Fig. 20).
An APF is used in the signal path to track the SAR and DAC latency.In addition, an LPF is integrated with the interstage gain to filter high-frequency OOB blockers.The overall signal rejection in the residue signal is <−22 dB over the complete frequency range (Fig. 21) so the backend ADC will not be overloaded even with an interstage gain of 8.The ADC achieves 77.5-dB peak SNDR in 40 MHz.Power consumption is 3.2 mW and the Walden FOM is 6.5 fJ/cs.The measured performance is summarized in Table 3D.

VI. SUMMARY
In this article, we have presented an overview of CT ADC architectures and key design aspects for high linearity and bandwidth.A selection of case studies of state-of-the-art high-speed and high-precision CT ADCs have been shown with best-in-class performance metrics related to linearity, bandwidth, and power efficiency.For high-linearity design, a 1-bit RTO (or RTZ) DAC is theoretically inherently linear, does not need calibration, and does not suffer from dynamic errors, but requires a low-impedance LDO to mitigate supply modulation and has limited bandwidth capability.A multibit modulator can achieve higher bandwidth but does need accurate DAC calibration.For higher bandwidth conversion, multistage MASH or pipeline architectures enable bandwidths from several hundreds of MHz to multiple GHz.One of the major challenges is to realize wideband signal suppression in the residue signal that is fed to the next stage, to maximize the interstage gain.Finally, for very good power efficiency, a hybrid CT pipeline ADC with front-end SAR and back-end delta-sigma modulator has been shown with a state-of-the-art Walden FOM of 6.5 fJ/cs for a CT ADC.

FIGURE 1 .
FIGURE 1. Design parameters (the number of bits, total NTF order, max single-stage loop order, Fs, and the number of stages) of CT ADC designs from ISSCC 1997-2022 with bandwidths > 10 MHz.

FIGURE 2 .
FIGURE 2. (a) Block diagram of single-loop delta-sigma modulator and (b) with quantizer latency and ELD compensation loop.

FIGURE 7 .
FIGURE 7. Block diagram of a CT pipeline ADC.

FIGURE 8 .
FIGURE 8. (a) Block diagram of CT delta-sigma ADC.(b) Block diagram of a high-linearity DAC architecture.

FIGURE 11 .
FIGURE 11.(a) Block diagram of residue generation circuit; (b) with ADC latency TD and DAC ZOH transfer; (c) with analog delay filter.

FIGURE 12 .
FIGURE 12. STF to residue output with various delay matching filters.

FIGURE 13 .
FIGURE 13.(a) Signal attenuation with signal feed-in at input of the ADC and (b) with analog delay matching filters.

FIGURE 17 .
FIGURE 17. Measured frequency spectra of a 0-dB input signal at 38.8 MHz with calibration OFF (black) and ON (red).