A Digital Power Amplifier With Built-In AM–PM Compensation and a Single-Transformer Output Network

This article presents a digital power amplifier (DPA) with a built-in AM–PM compensation technique and a compact single-transformer footprint. The AM–PM distortion behavior of the current-mode/voltage-mode power amplifiers (PAs) is detailed and an AM–PM compensation technique for both modes is introduced. The proposed design utilizes one current-mode DPA as the main path PA and a class-G PA voltage-mode digital PA as the auxiliary path PA, combined through a single-transformer footprint. It provides enhanced linearity through built-in adaptive biasing and hybrid current-/voltage-mode Doherty-based power combining. As a proof of concept, a 1.2–2.4-GHz wideband DPA is implemented in the Globalfoundries 45-nm CMOS SOI process. The measurements show a 37.6% peak drain efficiency (DE) at 1.4 GHz, and 21.8-dBm saturated output power (Psat) and $1.2\times /1.4\times $ power back-off (PBO) efficiency enhancement, compared to the ideal class-B at 3 dB/6 dB PBO at 1.2 GHz. This proposed digital PA supports 20-MSym/s 64-QAM modulation at 14.8-dBm average output power and 22.8% average PA DE while maintaining error vector magnitude (EVM) lower than −23 dB without any phase predistortion. To the best of our knowledge, this is the first demonstration of hybrid current–voltage-mode Doherty power combining on a single-footprint transformer over a broad bandwidth (BW).


I. INTRODUCTION
M ODERN communication systems adopt spectrally efficient modulation schemes to enhance the link throughput within a given frequency bandwidth (BW) at the cost of a large peak-to-average ratio (PAPR). This poses stringent requirements on the energy efficiency of RF power amplifiers (PAs) for both peak output power and also at power back-off (PBO) to ensure efficiency under modulation. Therefore, there is an increasing interest in exploring PBO efficiency enhancement techniques to achieve high PA average efficiency under these high-PAPR modulation schemes [1], [2], [3], [4], [5]. Doherty load modulation is one of the widely used techniques to boost PA PBO efficiency. However, when the Doherty PA's main path and auxiliary (Aux) path do not cooperate well together, they have limited linearity and require a large area to support the load modulation output matching network [6], [7], [8], [9].
Analog PAs are widely used in modern wireless communication systems. However, their designs cannot be readily transferrable across process nodes, benefit from device scaling, or support direct synthesis. Thus, there is an increasing interest in digital PA (DPA) research [18], [19], [20], [21], [22], [23], [24], [25]. DPAs support the ability to implement multiple functionalities within one compact formfactor block, extensive digital reconfigurability, and performance and design tracking aggressive CMOS process scaling [26]. Such digital Pas would be a good solution for applications  such as low-cost IoT, which uses appropriate power, small size, and not too complicated modulation. In particular, in the case of low-cost PA targeting such NB-IoT, it would be reasonable to consider digital PA, which has good linearity, not require DPD that increases complexity and cost.
A DPA can be generally divided into two categories based on their power cells, the current-mode DPA such as the class-D −1 , and the voltage-mode DPA such as the switched capacitor PA (SCPA). Current-mode DPAs typically support higher output power levels for a fixed supply voltage as the output voltage swing can exceed the supply voltage, but they suffer from large signal nonlinearities due to distortion [27], [28], [29], except for some recent designs which utilize built-in analog compensation techniques, such as AM-PM linearization [30]. Voltage-mode DPAs achieve good linearity and efficiency but provide limited output power levels as their output voltage swing is lower than the supply voltage [31], [32], [33]. Recently, a hybrid technique that improves the linearity by implementing the current-mode and voltage-mode DPAs together has been demonstrated [34]. However, it sacrificed the peak drain efficiency (DE) of the current-mode DPA by tuning on only half of its total power cells and suffers from area overhead and major passive loss penalty by connecting three transformers in series as its output matching network.
While a large amount of research to increase the PBO efficiency for complex modulation communication has been conducted, the techniques applied typically deteriorate the overall linearity [35], [36], [37]. Therefore, many digital PAs inevitably use 2-D digital predistortion (2D DPD) tables or models to compensate for their linearity. However, using 2D DPD comes with various limitations. First, it is necessary to accurately characterize the PA and create an inverse function in the 2-D space. Second, it increases the system power consumption and complexity. Furthermore, it is often incapable of sufficiently canceling all the PA nonlinearity. In particular, output impedance variations may aggravate DPD performance [38]. Therefore, it is essential to ensure intrinsic PA linearity with built-in linearization.
To address the aforementioned issues, we propose a fully integrated single-footprint hybrid current-voltage-mode digital Doherty PA [39]. In our proposed DPA topology, adaptive biasing is implemented for the current-mode DPA to minimize its AM-PM nonlinearity and the voltage-mode DPA used a class-G DPA [40], which has its own AM-PM compensation characteristic. In addition, the proposed DPA used a single-footprint transformer to apply a hybrid selfcompensation technique consisting of a current-mode DPA and voltage-mode DPA. Note this reported design differs from the design in [34], in that it implements two paths as a single transformer, utilizes all cells in the currentmode DPA using the adaptive biasing scheme, and improves linearity and efficiency using characteristics of class-G DPA. This article is organized as follows. Section II introduces the proposed hybrid polar Doherty DPA architecture. Section III presents the analysis of AM-PM distortion within the current-/voltage-mode DPAs and proposes methodologies to improve the linearity of both, and measurement results are shown in Section IV. Section V concludes this article.  output network. 8-bit AM codes control both the output power and adaptive biasing. The constant envelope PM carrier signal is buffered by a comparator and a digital driver that then feed the two sub-PAs. The AM signal is digitized to an 8-bit parallel AM control code and is then fed to the PA to control the numbers of PA cells enabled. The main path (C-DPA) and Aux. path (V-DPA), which are distributed symmetrically along the output feedline, apply a fork shape configuration to minimize the phase offset and deliver PM signals evenly to the Main and Aux paths.

A. SINGLE FOOTPRINT BROADBAND LOAD MODULATION NETWORK FOR HYBRID VOLTAGE/CURRENT DPA
This design utilizes a single-footprint parallel-combining transformer to achieve the broadband Doherty power combining network [41]. The transformer occupies 430 μm × 430 μm die area. Fig. 2 shows the proposed single-footprint transformer load modulation output matching network. To achieve the desired impedance transformation ratio and enhance the quality factor, the three-coil parallel-combining transformer is implemented with nine turns, of which three turns are the two primary inductances (connected to the Main and Aux. path PAs) and the other six turns are the secondary inductance (connected to the 50-antenna load). The passive efficiency of this single-footprint transformer at the peak PA output power is shown in Fig. 3. The definition of passive efficiency can be described as the proportional power delivered to the load to the power delivered to the network, as shown in where R s and R in are the impedance of source and input, respectively, and the loaded quality factor of the network is defined as where Q loaded is the loaded quality factor of the series resonant network. Note that this proposed load modulation architecture does not need a large switch in the Aux path to provide a short, because the voltage-mode PA used in Aux path provides a low impedance when turned off, supporting a very compact formfactor. However, if a current-mode PA is used in the Aux path, when the current-mode PA is turned off, a switch is then required, because the current-mode DPA shows high impedance when turned off, which will load the PA output passive network and degrade its efficiency. To the author's knowledge, this is the first demonstration of power combining current-mode and voltage-mode DPAs in a singletransformer footprint by using a single-transformer-based parallel combining network. Note this output passive network is not designed to realize any impedance inverter properties to ensure its broadband operation, since the turning-on sequence of the voltage/current-mode PAs performs effective Doherty active load modulations. This is detailed as follows. The output voltage swing in the differential current-mode [28] and voltage-mode [26] PAs, with n out of N unit cells turned on are as follows: The impedance at the main and aux PA output for a Doherty PA can be derived as where V Main and V Aux are the Main and Aux amplifier voltages, respectively. Replacing (1) and (2) into (3) and (4), the impedance presented to each PA can be derived as where M is total number of bits for VDPA, and m and n are the number of "ON" power cells of VDD mode and 2VDD mode in VDPA, respectively. Thus, depending on the AM turn-on sequence, each PA experiences proper active load modulation, achieving deep PBO efficiency enhancement.

B. OVERALL OPERATION OF PROPOSED DPA ARCHITECTURE
The proposed hybrid single-footprint transformer digital PA combines one main path C-DPA and one Aux path V-DPA, Class-G DPA, to achieve built-in AM-PM compensation and PBO efficiency enhancement. In the low-power region, as the output power increases, current DPA cells sequentially turn on until 5.2-dB PBO. At this time, if the output voltage of Main and Aux. path is equal, it would be 6-dB PBO after all the cells of Main path are turned on like conventional Doherty structure, however, the proposed architecture has different output voltages and impedances between main path and Aux path as shown in (1) and (4), thus when all the cells of Main path are turned on, theoretically, it achieves an efficiency peak at 5.2-dB PBO due to Doherty load modulation. After all the cells of the main path are turned on, the unit cells of the Aux path are gradually turned on in VDD mode. When the Aux path is fully turned on to VDD mode, the overall PA achieves an additional efficiency peak by class-G operation at 2.2-dB PBO, and then the Aux PA cells are gradually turned on to 2VDD mode as well. Fig. 4 (a) (b) (c) illustrates the efficiency, load impedance, and overall turn-on sequence of each PA operation.

III. THEORY OF AM-PM DISTORTION OF DIGITAL PA
There are two main sources of linearity distortion for PAs, AM-AM and AM-PM [42]. Since AM-AM distortion can be compensated through proper selection of the AM control code [30], we will focus on AM-PM distortion. The principles for the occurrence of AM-PM distortion and the methods to improve/compensate for it regarding the currentmode DPA and the voltage-mode DPA, respectively, are described below.

A. CURRENT-MODE AM-PM COMPENSATION
We will first review the behavior of conventional current mode, class-D −1 PA, and its main causes of AM-PM distortion [27], [30]. Fig. 5 shows the schematic for class-D −1 PA composed of N-bit segment binary-weighted cells.
The nonlinearity of the current-mode DPA is mainly caused by the output capacitance C d variations against output power level [30]. C d can be derived as C gd where C ds is the total effective capacitance between the drain and the source of M 2 and A is the voltage gain of the cascode transistor (M 2 ) [43]. First, the C gd of the cascode transistor (M 2 in Fig. 5) is varied according to the device operation region as [44] C gd_triode = WLC ox 2 + WC OV C gd_saturation = WC OV (8) where W is the cascode transistor gate width; L is the gate effective length; C ov is the drain-gate overlap capacitance; and C ox is the gate-oxide capacitance. As more digital cells are turned on, the output voltage swing of V out node increases. At this time, since the gate bias is fixed, as V out increases, M 2 operates in the triode region for a longer period, which increases C d . In addition, when the power cell is turned off, C d = C gd_off , since C ds is terminated with high impedance, providing low capacitance. In summary, as more cells are turned on in the conventional current-mode DPA, more cells operate in triode for longer periods, hence the total PA output capacitance increases as a function of output power. This modulated capacitance shifts the resonance frequency, which causes AM-PM distortion as shown in Fig. 5(c). As the output power increases, the AM-PM goes increasingly negative and we call it as lagging AM-PM [34]. To reduce the time period during the triode region, we use adaptive biasing on the cascode device. As more cells are turned on, the bias voltage is decreased as shown in Fig. 6(b). This operation shortens the interval in the triode region, which reduces the capacitance variation over output power. As shown in Fig. 7, employing adaptive biasing reduced the total AM-PM distortion from 11.3 • to 6.7 • at 2.4 GHz.

B. VOLTAGE-MODE AM-PM COMPENSATION
In this section, we analyze and show the AM-PM distortion behavior of voltage-mode digital PA, conventional SCPA [26], and class-G [40]. As shown in Fig. 8, the conventional single-ended SCPA consists of an M-bit binary weighted unit cell and a bandpass matching network [26]. The output power level is determined according to the number of cells turned on by the AM code selected (m), whose bottom plates are switched between V DD and GND at the carrier frequency. The capacitance of the unswitched cells (2 M − (m + 1)) × C u is shorted to ground, while the capacitance looking into the switched-on cells is m × C u . Hence, the equivalent capacitance (C out ) looking into the PA continues to be (2 M − 1) × C u regardless of the number of cells turned ON. Hence, the inductance (L ind ) continues to resonate at the same frequency, and we can assume there is the same phase between V x and V out . On the other hand, the where M is the total number of bits of the SCPA, and m is the number of "ON" SCPA power cells. The charging/discharging time ( t) of C in can be expressed as follows: where I is the current driving strength of the SCPA unit power cell. C in is substituted in (11) and as a result, the transition charging/discharging time ( t) at V x can be further derived as [34] As shown in this equation, the larger the number of unit cells (m) turned on, the shorter the transient time, corresponding to a positive frequency shift, and a corresponding leading behavior, which is inverse from the current-mode DPA AM-PM distortion. We can expand this concept to the class-G DPA. A voltage-mode amplifier can be represented as a capacitive divider, and Fig. 9 shows the VDD mode and 2VDD mode of class-G operation. In class-G VDD mode, AM-PM distortion demonstrates a leading behavior, the same as the conventional SCPA. However, when operating in the 2VDD mode, it can be expressed as a capacitive divider with two input sources as shown in Fig. 9(b) and it can be expressed by the following charging/discharging equation: where n is the number of tuned on unit cells as 2VDD.
As summarized in Fig. 9, for VDD mode, as the number of VDD cells (m) turned on increases, the charging/discharging time becomes shorter, which illustrates the leading AM-PM distortion behavior. However, in the case of the 2VDD mode, as the number of unit cells (n) transitioning from VDD to 2VDD is increased, the output power increases, the charging/discharging time becomes longer, and lagging AM-PM distortion behavior occurs. Looking at the simulation results of class-G operation, as shown in Fig. 10, the efficiency improves at 6-dB PBO thanks to class-G operation [40], and at the same time, the AM-PM distortion direction transitions from leading to lagging, and hence compensates itself. The magnitude of leading AM-PM distortion of the V-DPA can be manipulated by the driving strength of the SCPA power cells and the size of C u , which is a direct tradeoff with the efficiency and output power [34].

C. AM-PM OPERATION OF PROPOSED ARCHITECTURE
The AM-PM nonlinearity as a function of the output power level is self-compensated by the proposed architecture. First, the AM-PM distortion of current-mode DPA has a lagging (negative) behavior according to output capacitance. However, it is mitigated by adaptive biasing. Second, as the DPA in the voltage-mode DPA is turned on in the VDD mode, the direction of AM-PM distortion is changed to the leading (positive) behavior, opposite to the previous current mode, which is a characteristic of the hybrid (current/voltage) operation. Third, the AM-PM distortion behavior changes its direction back to lagging as the cells in the Aux path change to the 2VDD mode. Fig. 11 illustrates the simulation results of the AM-PM distortion, and Fig. 12 shows the simulated results of the AM-AM response that changes as each mode is operated in the proposed architecture.

IV. MEASUREMENT RESULTS
A proof-of-concept hybrid polar Doherty DPA is implemented in the Globalfoundries 45-nm CMOS SOI process with a chip size of 2.57 mm × 1.98 mm, including all decoupling capacitors and electrostatic discharge (ESD) I/O pads (Fig. 13). This is a fully integrated DPA design with C-DPA and V-DPA power cells, adaptive bias, output passive network, and AM and PM drivers. The chip is mounted on an FR4 PCB board and wire-bonded to facilitate the probingbased testing. The dc supplies are 1.1 and 2.2 V for class-G operation.
We first characterize the DPA using continuous wave (CW) signals with a 50-standard load. A single-ended PM signal is first converted by an off-chip balun (Krytar4010180) to generate the differential signals and fed to an input PM driver. The AM sequence is controlled using a USB-1024LS with a custom LabVIEW code. The amplified single-ended output signal is measured by an RF power  meter (Keysight N1913A). Fig. 14 Fig. 15.
The PA is then characterized with modulations. Desired complex modulation signals are synthesized in an advanced design system (ADS) and decomposed into their corresponding AM and PM signals for polar operation. The memoryless 1-D AM-AM lookup table (LUT) for each PA is made  based on the characterized CW test, and a pattern generator (Keysight 16822A) generated the 8-bit AM control LUT. The PM signals are generated by the arbitrary waveform generator (AWG) (Tektronix AWG7002A). Since the timing alignment between AM path and PM path is very critical for the modulation performance [45], we use a pulse function generator (Agilent 81160A) to generate the trigger pulses for AWG and pattern generator to synchronize the AM and PM signal with a fine control delay. The output signals from the PA are demodulated by a real-time oscilloscope (Keysight MSO840A). Fig. 16 shows the demodulated 20-MSym/s single-carrier 64-QAM signal at 1.2 GHz without any phase predistortion. It achieves 14.8-dBm average P out and 22.8% average DE, 23.48-dB EVM and −25.36-dBc ACLR. Table 1 shows the comparison of the proposed hybrid single transformer with state-of-the-art RF CMOS digital PAs. This proposed the single-transformer footprint hybrid current-voltage digital Doherty PA achieves broadband operation compared to the state of the art.

V. CONCLUSION
This article presents a compact broadband hybrid current-/voltage-mode digital Doherty PA with a single three-coil transformer as its output network and built-in large-single AM-PM distortion compensation, which is capable of supporting large-PAPR high-speed modulation signals without any phase predistortion. An adaptive biasing scheme is proposed to minimize the current-mode DPA's inherent AM-PM nonlinearity. Class-G operation within the voltage-mode PA is introduced to achieve efficiency enhancement and AM-PM nonlinearity reduction. A current-/voltage-mode DPA architecture is proposed to support AM-PM cancelation, removal of unnecessary switches, and support load modulation within a single-transformer network.