Flexible Interlinking Converter With Enhanced FRT Capability for On-Board DC Microgrids

In this paper, a flexible interlinking dc/dc converter with enhanced FRTC is proposed to satisfy the advanced requirements of modern on-board DC MGs; the topology uses a non-isolated switched capacitor-type multilevel converter in combination with a cascaded step up/down converter to facilitate the incorporation of various types of energy storage and/or production units in a DC MG. Overall, a high voltage conversion ratio between the dc bus of the MG and the power unit is achieved. The proposed configuration facilitates the CCM operation of both the power unit and the DC MG and it is characterized by bidirectional power flow capability, enhanced FRTC, zero switching losses for the multilevel converter, limited complexity of the control scheme (compared to the counterpart multilevel solutions) and low real-time communication demands, corresponding so to the increasing flexibility needs of the EMS of modern MGs. The mathematical analysis and the dynamic performance of the control scheme of the proposed topology concept are evaluated via MATLAB/Simulink simulations and real-time CHIL tests, with the use of a 1202 dSPACE platform and an external dsPIC30F4011 microcontroller.

HBC switches. D 1 -D 4 HBC diodes. G p switches for the parallel connection of C 0 ÷C n-1 . G s switches for the series connection of C 0 ÷C n-1. G L switches for the connection of n-1 cells. G s1 , G s2 step up, step-down operation switch. D s1 , D s2 step up, step-down operation freewheeling diode. S 0 ÷S 5 switching states of the topology.  (max) (maximum) i bus reference (A). P sw,loss(,max) (maximum) switching losses (W). V DD , I D base values for drain-source voltage (V), drain current (A). E on , E off turn on, off switching energy loss (mJ). I bus steady-state peak to peak variation of i bus (A). I s (max) (maximum) steady-state peak to peak variation of i s (A

A. MOTIVATION AND APPLICATION UNDER STUDY
Nowadays, the more the electrification level of the TMs' increases, the more the electrical system of a modern ETM becomes comparable to a land-based autonomous MG [1]; in light of this, the incorporation of various RES (e.g., photovoltaics, DGs) and alternative energy sources (e.g., fuel cells), other energy harvesters (such as thermoelectric generators) as well as multiple buses of different voltage levels in the ETM's powertrain has become a trend in research community and automotive industry, aiming at the reduction of the use of fossil fuels and green-house gases' emissions, consequently.
On the other hand, the incremental penetration of RES, ESSs (e.g., BES, SCs) and energy harvesters with inherent DC operation, as well as the growing ratio of DC loads in ETMs' on-board power systems, seems to pave the way for further utilization of DC systems or even for the adoption of pure DC onboard MGs [1]. For example, in M/AEA a purely HVDC distribution architecture, utilizing 270 V or 540 V (±270 V) main DC buses, has been widely investigated and proposed [2]. Furthermore, in recent M/AES concepts, a wide range of voltage levels of the main DC distribution architecture has been proposed, using 1-35 kV MVDC [3] -depending on the different types/classes of the vessels -as well as lower DC buses, such as 690 V [1], [4].

B. LITERATURE REVIEW
Several voltage step-up topologies have been proposed in the literature, regarding the appropriate interlinking of the previously mentioned DGs and/or loads in a modern DC MG, dealing in particular with the case of the high/medium power ones, where high voltages are usually utilized at the MG side [5], [6], [7], [8]. As regards the state-of-the-art bidirectional converters that are proposed for the dc/dc high power conversion in DC MGs, these are characterized by high λ capability, good dynamic performance (thanks to direct current control) and modularity (in system/cell lever or in both). In more detail, the isolated dual active bridge (DAB) constitutes the most promising candidate so far [9], [10], [11], [12], [13] providing advantages such as galvanic isolation, high-power density, fast power flow reversal, step-up and step-down operation (with high λ), applicability of synchronous rectification, inherent fault isolation capability. In addition, some other isolated converter topologies based on the DAB, such as the resonant type DAB [14], [15], have been proposed with the prospect of expanding the soft-switching region (realizing both ZVS and ZCS), where a capacitor and/or an inductor can be placed in series with the transformer. However, these converters suffer from well-known disadvantages regarding the magnetically coupled circuit (i.e., incorporation of a high-frequencythough relatively bulky -transformer which moderates power density and raises saturation issues) and the complexity of the control scheme to achieve soft/zero switching operation. On the other hand, a non-isolated multilevel converter topology [16], [17], such as the MMC, is an alternative attractive solution for high-power conversion in modern DC MGs [18], [19], [20]. The merits of this converter over conventional ones are the inherent redundancy, the current-fed control that facilitates self-balancing of the capacitors, the low device ratings, the very low output harmonic distortion, the scalability and the possibility of common dc-bus configuration for multidrive applications; on the contrary, the practical bottlenecks that may prohibit the use of the MMC for higher voltage and power levels (as reported in [18]) are: the voltage stresses across the flying capacitors that may lead to a bulky capacitor bank, the operational limitations due to the complex charging pattern and the hard switching characteristics (that limit the increase of the switching frequency in practice). It is worth noting that the common characteristic of interest, regarding the above-mentioned solutions, is their default inability of providing FRTC (due to the magnetic coupling of the transformer-based converters and the voltage fed circuitry/configuration in combination with the different state of charge of the capacitors in each sub-module of the multilevel topologies); however, FRTC constitutes a critical/important feature of the contemporary standards regarding the power quality in DC MGs [20], [21].

C. CONTRIBUTION OF THE PRESENT PAPER
Under this light and with respect to the recently published/introduced SAF concept regarding the connection of a dynamic power unit to a DC MG via an appropriate interlinking converter (facilitating the energy flow between the DC MG and an electric machine [22], [23]), this paper aims to further extend that circuitry analysis to similar DC MG applications. Specifically, the present study proposes the series connection of various types of power units (e.g., APU, DG, BES, SCs, fuel cells, etc.) and a DC MG, being a configuration which has already proved its enhanced FRTC [22], [23]; the basic scope of the proposed circuitry concept is the facilitation of the energy transactions between the power unit (being the DC port/input of the interlinking topology) and the DC MG, as well as between DC buses with different voltage levels (as depicted in Fig. 1), through the development of a flexible EMS (serving as a modern electrical energy hub in essence). It is noted that, any converter that enables bidirectional power flow can be used in the proposed interlinking topology (which constitutes a current-fed converter in essence); the present work proposes the incorporation of a switched capacitor-type multilevel (n-level) converter [24] in combination with a cascaded step-up/down converter [25], as Fig. 2 illustrates; an appropriate (dis)charging pattern is implemented at the multilevel converter (utilizing the basic idea of a charge pump circuitry [26]), allowing for the CCM operation at each side connected to the interlinking topology, under high λ, as it will be discussed. The advantages of the proposed concept (that will be demonstrated by the theoretical analysis and the presented results) are the following: 1) elimination of the narrow λ range of the traditional step-up/down converters (via the switchedtype pattern of the capacitor-based circuit), 2) coherent design  methodology, ensuring the optimal performance of the converter (in terms of the practical components' selection) and facilitating CCM at both sides (i.e., the power unit and the DC MG), 3) flexibility feature; step-up and step-down operation, facilitating the bidirectional power flow in the interlinking topology, enabling so a) the incorporation of various types of power units, such as energy storage and/or production ones (energy hub in essence) in the DC MG, b) the interconnection of dc buses of different voltage levels (e.g., interconnection of an HVDC and an LVDC of the MEA), c) modularity via the multiport feature of the circuitry configuration, which can be considered as a building block (comprising of any type of bidirectional power components' cells, such as BES and SCs), d) implementation of various energy management strategies, with simple real-time communication demands among the system's units (i.e., incorporated power units, multiple interlinking converter blocks and DC MG buses), 4) zero switching losses (ZCS) of the multilevel converter, 5) reliability and redundancy of the proposed topology, thanks to the availability of identical components' cells/building blocks of the interlinking converter and 6) enhanced FRTC (thanks to the current-fed configuration of the interlinking topology and the self-balancing ability of the multilevel converter's switching pattern), which is neither inherent nor practical for the common dc/dc cascaded configuration (voltage-fed converters).
It is worth noting that the main scope of this work is to introduce the basic concept/idea of this flexible interlinking topology (by proposing a series connected dc/dc converter configuration) and its circuit analysis, as well as to validate its EMS control feasibility; practical issues (such as the capacitors' health monitoring and DGs' and ESSs' actual control loops) are excluded from thisinitial -study, being some interesting points for further work. The dynamic performance of the proposed switched capacitor-type multilevel converter is enhanced via the developed design algorithm, while the theoretical analysis of the proposed EMS control scheme has been verified through both MATLAB/Simulink simulations and a CHIL test-bench via a dSPACE MicroLabBox platform and an external DSP, i.e., the 16-bit dsPIC30F4011 microcontroller.

II. CIRCUIT ANALYSIS OF THE PROPOSED INTERLINKING TOPOLOGY
The basic concept of the proposed interlinking topology lies on the incorporation of a switched capacitor-type multilevel dc/dc converter between a power unit (in this study the power unit circuit is modeled as a voltage source connected in series with an inductor, as depicted in Fig. 2) and the DC MG under study (in this study the DC MG is modeled as a voltage source, whereas the series inductance is set in accordance with the desired switching frequency -as it will be discussed in Section III); a dual-mode (dis)charging pattern is implemented at the multilevel converter, facilitating so different charging and discharging rates of the capacitive unit, as it will be thoroughly explained. It is noted that for the presentation of the basic concept of the proposed charge pump pattern [25], ideal capacitors (of the same C-capacitance value per capacitor) are employed.

A. PROPOSED SWITCHED CAPACITOR-TYPE MULTILEVEL DC/DC CONVERTER
For the implementation of the proposed topology, a n-level capacitive unit along with an HBC is employed in the circuitry, as shown in Fig. 2. The input of the HBC is the capacitive unit (which is also connected to the power unit circuit), while the output of the HBC is connected to the DC MG under study. For the sake of the present analysis, the power unit is considered as the low voltage side, while the DC MG is considered as the high voltage side (thus λ≥1).
The operating principle of the proposed topology regarding the interlinking of a power unit (it can be considered both as a power source and a sink) and a DC MG lies on the implementation of a dual-mode (dis)charging pattern of the intermediate n-capacitors' matrix that is incorporated in the multilevel circuitry (C 1 ÷ C n ); as Fig. 2 depicts, n − 1 capacitor cells are needed for the construction of a n-level capacitor matrix. For the implementation of the bidirectional power flow, i.e., from the power unit to the dc bus (voltage step-up operation) and vice versa (voltage step-down operation), each capacitor cell must be comprised of three (3) bidirectional switches that facilitate the parallel and series connection of the capacitors of the n − 1 cells.
Specifically, as Fig. 2 illustrates, a pair of bidirectional switches allows for the parallel connection of the capacitors (G p , G L ) while one bidirectional switch (G s ) serves their series connection, so that a n-level topology is constructed. Moreover, at the power unit side, the step-up operation is achieved by the using G s1 and D s1 , while the step-down operation is achieved by using G s2 and D s2 .
As it will be analytically explained, the number of levels (n) that facilitate the bidirectional power flow in CCM operation of the power unit circuit, depends on λ. The step-up operation of the proposed topology is analytically described in the following subsection (the mathematical description of the step-down operation can be derived accordingly). Table 1 presents the status of the variables of the total topology, including the power unit circuit, the interlinking circuit and the DC MG of Fig. 2, according to the switching states (S 0 ÷S 5 ) of Fig. 3(the switching states during step-down operation are also included). It is noted that the basic states of operation are S 0 and S 3 , while S 1 , S 2 , S 4 and S 5 are used for the zero current switching (ZCS) of the capacitor cells' switches (transition states). In addition, the power flow regulation is imposed via the hysteresis current control that is implemented on i bus , keeping it so at a constant value (I ref ) within a constant hysteresis zone (H). It is noted that the selection of a specific current controller type (i.e., hysteresis or peak current or average current mode control) has no effect on the operating principles of the proposed scheme. Fig. 3 presents the switching states during the step-up operation of Fig. 2, in which the power flows from the power unit to the DC MG. During S 0 , G s1 is on and i s increases in  (Fig. 3)

FIGURE 3. Switching states (S 0 ÷S 5 ) of the proposed interlinking topology for step-up operation.
the face of V s . At the same time, G p1 , G p2 are off, G s , G n − 1 , G 1 and G 4 are on, so that i bus increases in the face of nv c -V bus while the capacitors discharge. Regarding S 0 , the following equations are derived: S 0 ends when i bus reaches the upper limit of the hysteresis zone (I ref +H/2). At this point, G 4 turns off (S 1 begins) and i bus decreases in the face of -V bus , while i c becomes zero. Following that, G s turns off (zero current switch) and S 2 begins, while i bus keeps decreasing.
Next, at the time spot when i c reaches zero (according to Table 1) S 3 starts; G s1 turns off, i s decreases in the face of V s -v c and the capacitors charge. At the same time, G p1 , G p2 , G n−1 are on, G s is off and G 1 turns off, so that i bus decreases in the face of -v c -V bus and the capacitors charge. As regards S 3 , the following equations are derived: S 3 ends when i bus reaches the lower limit of the hysteresis zone (I ref -H/2). At this point, G 1 turns on, S 4 begins and i bus keeps decreasing in the face of -V bus , while i c becomes zero. Following that, G p1 , G p2 turn off at S 5 (zero current switch), while i bus keeps decreasing. Equations (1)-(6) are used for the average model analysis of the following section.

III. AVERAGE MODEL AND PERFORMANCE ANALYSIS
The average modeling of the circuitry in Fig. 3 is presented in Fig. 4; for the derivation of d, only the basic states, i.e., S 0 and S 3 of Fig. 3, are used. In addition, it is noted that a high capacitance value (C) facilitates the mathematical analysis approach, accounting for the constant capacitor voltage assumption throughout the development of the theoretical equations. Moreover, it is noted that for the sake of the simplicity of the analysis of the present section, the parasitic components of L bus , L s and C have been omitted.

A. AVERAGE MODEL IN STEP-UP AND STEP-DOWN OPERATION
The analysis of the steady state operation (V Ls = V Lbus = 0) of Fig. 4 leads to the following set of equations: Taking (7) and (8) into account, d in step-up operation can be defined as follows: From (9) it is obvious that as n increases, d decreases, facilitating so the stable step-up operation of the proposed topology for a wide practical d range (i.e., 0.2 ÷ 0.8), as λ increases. As a result, a wide λ range can be satisfied under CCM operation of the power unit's circuit.
The steady state analysis of Fig. 4 regarding the step-down operation leads to the following expression (derived in the same manner as for the step-up operation): From (10) it is obvious that, as in step-up operation, a wide λ range can be satisfied under CCM operation of the power unit's circuit. Moreover, from (7) and (8) regarding the step-up operation, the following expression can be extracted (which is also valid for the step-down operation):

B. PERFORMANCE ANALYSIS AND DESIGN OF THE PROPOSED TOPOLOGY
The circuit design (passive components and semiconductors) of the proposed topology of Fig. 2 must ensure the optimal performance at both sides of the topology (i.e., the power unit and the DC MG) during the implementation of the control scheme/pattern (according to the switching states of Table 1) under load, voltage and power supply variations. The basic feature of the proposed circuitry is the implementation of the energy transactions between two independent sources (i.e., the DC MG and the power unit) with the aid of a series-connected converter; the latter acts as a controllable voltage source (regulated by i bus ), facilitating the imposition of the desired level of the transferred power. Since the hysteresis current control of i bus directly affects d (which is common to the total circuitry of  (9), (11) that formulate the average model of Fig. 4 are used along with (A8)-(A11) of the Appendix, so that the following TF is derived: In (12): Working similarly for the step-down operation, the following TF is derived: In (20): Equations (12)- (21) clarify that: i) The open-loop gain (G do ) in (13) constitutes a current amplifier at the power unit's side in essence; in light of this, a high G do -value ensures a wide margin for a wide range of d-values. ii) From (12) and (20) it turns out that G do is common for both step-up and step-down operations. The assumptions i and ii can be used to develop a rigorous design procedure that allows for the selection of the appropriate parameters' values of the proposed topology in Fig. 2, facilitating the bidirectional power flow (i.e., step-up and down operation) between the power unit and the DC MG, on the basis of the following criteria: a) The design is oriented upon the MOP(I ref,max ), according to the specifications/inputs of the system under study -i.e., λ (V s , V bus ). b) The selected n-value facilitates the optimal dynamic response of the power unit's side for operation in CCM, in both step-up and step-down modes -dictated by the selected d from (9) and (10). c) The expression of the open-loop gain (G do ) is used for the selection of the optimal components of the topology (i.e., L bus , L s , C) that facilitate its best performance. From (13) it turns out that, for fixed λ and n, G do is directly increased by a large k-value and decreased by a large ω sw -value. Moreover, (14) suggests that ω 0 is proportional to k and ω r , while a large ω sw -value increases M in (15) and N in (21); in (16) increases with ω r . These observations/conclusions constitute the basic tool for the design of the optimal/desired performance of the system -in terms of the frequency domain response analysis [27] of the TFs in (12) and (20). Considering a-c, the design procedure of the proposed topology can be summarized in the following steps: 1) Define the system's specifications as inputs: MOP (I ref,max ), λ (V s , V bus ) -practically, λ is rounded up to the next integer number. Move to step 2. 2) Select d from (9), (10); e.g., setting d = 0.5 (optimal choice in terms of dynamics for practical converters [28]), the following is derived: In (22), λ≥1 (initial assumption, Section II, Subsection A), thus n≥2. Define n from (22) and move to step 3. 3) Define the maximum ω sw (ω sw,max ) which results in acceptable P sw,loss (P sw,loss,max ) of the interlinking HBC (with respect to commercial HBC modules for the application under study), according to the following formula [22]: Define ω sw,max from (23), for P sw,loss,max . Move to step 4. 4) Minimize I bus (in the present control implementation, I bus = H) according to the power quality specifications of the system under study, through an appropriate Hvalue (H = δ 1 ·I ref,max , e.g., δ 1 = 5%). L bus -value can be calculated via the following equation (which is derived for n = λ + 1 at step 2d = 0.5), with the use of (2), (11) for the step-up operation (accordingly for the step-down operation): Define L bus,min from (24) and L bus,max according to practical design/components' limitations, such as the inductors' costs [28]. It is noted that the L bus,max -value results in the minimum ω sw -value (ω sw,min ) of the converter. Move to step 5. 5) Ensure CCM operation of the power unit, via the following condition (which is derived for n = λ+1 at step 2, d = 0.5, with respect to (1) and (11) for the step-up operation and accordingly for the step-down operation): Define L s,min from (25) and L s,max according to practical design/components' limitations, such as the inductors' costs [28]. Move to step 6. 6) Define the maximum acceptable V c from the following equation (which is derived for n = λ+1 at step 2): (26). End of the design process. Finally, the outputs of the 6-step design algorithm are: nvalue (for the desired d that facilitates the optimal dynamic response of the topology; usually d = 0.5 is considered), ω sw,max (resulting in acceptable switching losses of the interlinking converter), acceptable range of L bus , L s valuesthe final choice of k value facilitates G d0 >>1 in (13)and C min -value (resulting in the optimal ω r that leads to the optimal performance and power quality of the system, with respect to the Bode plot analysis). Specifically, with respect to the analysis of Subsection B of the present section, for the selected values of λ (step 1) and n (step 2), the maximum k-value (L bus,max , L s,min ) along with ω sw,min facilitate the wide open-loop gain margin as regards the response of the TFs expressions in (12) and (20) -it is evaluated with the use of the Bode plots. On the other hand, the C-value (with reference to the optimal value, C min ) can be used for the determination of the appropriate ω r , with respect to the frequency domain analysis of the TFs in (12) and (20), as it is highlighted in the presented results of the following section (Section IV).
It is noted that the simplified analysis (with the use of ideal components in the circuitry of Fig. 4) that yields (12)-(26)  does not cancel the rational of the proposed design procedure; the latter can be used in practical cases, including more detailed/accurate design parameters, such as the parasitic elements of the passive components and the bidirectional switches, that lead to a more complex system description.

C. DEVELOPMENT OF THE EMS CONTROL SCHEME
In the present subsection, the EMS scheme of the proposed topology of Fig. 2 is developed according to the energy flow schedule of the DC MG (i.e., from/to the power unit); Table 2 presents the possible operating modes of the energy sources (i.e., the power unit and the DC MG) attached to the interlinking circuitry for the proposed EMS, while Fig. 5 illustrates the block diagram of the EMS.
As regards the proposed EMS, the power unit can either provide (mode 1 of Table 2) or store (mode 3 of Table 2) energy to / from the DC MG, according to the control implementation of Fig. 5(a); in case of disconnection of the  power unit from the circuitry of Fig. 2, the multilevel converter toggles between modes 2 and 4 according to the control implementation of Fig. 5(b), so that the capacitors charge and discharge between V c,ref,max and V c,ref,min (hysteresis control implementation on v c ); the latter results in zero average power transfer between the DC MG and the interlinking converter during the disconnection time interval of the power unit, enforcing so the operation of the proposed topology as a flexible bond that facilitates energy transactions between the (various voltage level) buses of the MG.
On the other hand, in the case of a short circuit fault at the main DC bus side (i.e., V bus = 0), the EMS control scheme continues its operation for n = 1, which in this case ensures the circuitry's operation with d = 0.5. In more detail, for n = 1 and V bus = 0, (2) and (5) suggest that d = 0.5, while f sw is reduced (T sw is increased). At the same time, the capacitor bank continues its (dis)charging pattern, with positive average charge during each cycle of the control implementation -as it can be derived from (3) and (6); thus, constant current flow (uninterrupted hysteresis current control on i bus ) is provided to the DC MG during the fault, ensuring so the enhanced FRTC of the proposed scheme. However, it is worth noting that, under this condition, the power unit operates in DCMwhich is dictated by (25).

IV. PERFORMANCE VALIDATION VIA SIMULATIONS & REAL-TIME CHIL IMPLEMENTATION
The performance of the developed EMS scheme of the proposed circuitry (as described in detail in Sections II and III)

TABLE 3. Real-Time Model Parameters of the Proposed Circuitry
is validated via simulations in Simulink (MATLAB R2018b software) and real-time control implementation; Fig. 6 illustrates the block diagram of the CHIL set-up.
The dSPACE MicroLabBox 1202 platform (combined with MATLAB R2014b software) has been employed, in cooperation with an external dsPIC30f4011 DSP controller hardware; the latter receives the real-time feedback signals (i.e., i bus and v c are the microcontroller's inputs) from the simulation model (i.e., the circuitry of Fig. 2 is built in MicroLabBox 1202), implements the proposed control algorithm and sends the appropriate control signals (i.e., the on/off commands of the switches of the power unit and the multilevel converter are the microcontroller's outputs) back to the MicroLabBox 1202.
The parameters of the CHIL tests are given in Table 3 and they have been selected according to the 6-step design algorithm of Section III, Subsection B (considering the realtime sampling frequency restriction of the MicroLabBox 1202 hardware [22]). The CHIL tests of the present subsection are used as a proof of concept of the developed control method under real-time implementation, considering the influence of second order effects such as computational and PWM delays, quantization errors of the embedded ADCs in the microcontroller, deadtime of the inverter, etc. [22], [29], [30]. Fig. 7 exhibits the Bode plot of the TF in (12) -the response of the TF in (20) is similar, for various combinations of k and ω r values (with respect to the maximum and minimum boundaries that are defined with the use of the 6-step design algorithm of Subsection B, Section III); this figure verifies that a high k-value satisfies the wide gain margin requirement of the topology, while ensuring that this constant gain is oriented at the low frequency range (which is desirable for the stable operation of the circuitry). Furthermore, the selection of an appropriate ω r value (through C-value) facilitates the wide range of the gain damping at the high frequency region (close to switching frequency), which is another significant requirement (noise damping). Fig. 8(a) illustrates the step-down operation of the developed control algorithm in real-time implementation, under step changes of I ref , highlighting the good dynamic performance of the proposed control scheme. Moreover, Fig. 8(b) confirms the robustness of the proposed system and control algorithm during operating mode changes, dictated by the proposed EMS. Finally, Fig. 8(c) verifies the FRTC, under a 200 ms short circuit fault at the DC MG side. The dSPACE CHIL results in Fig. 8(a) and (b) show that the proposed EMS control strategy is effective under various scenarios in real time, while the high sampling frequency of the simulations in Fig. 8(c) is used for better accuracy of the presented results.

V. CONCLUSION
In the present work, a dc/dc switched-type multilevel converter is combined with a cascaded step up/down converter to form a flexible interlinking topology, which can be incorporated in modern DC MGs, enabling the flexible connection of various power units; the proposed circuitry facilitates the wide λ range and high-power range requirements in CCM, with relatively low semiconductor switches/components count (with respect to similar counterpart multilevel topologies), while achieving zero current switching operation and reduced realtime communication demands.
The most significant advantages of the developed currentfed topology are its enhanced FRTC (which is not an inherent feature of the counterpart converters of similar high λ capability), the high dynamic performance (thanks to the current mode control) and the modularity (in cell level) that are favorable for the DC MG application under study.
The theoretical analysis has been verified by both simulations and real-time (CHIL) test results, highlighting the good dynamic response of the converter and the effectiveness of the EMS control scheme that is implemented during step changes. In summary, this work has successfully introduced the concept of this flexible interlinking topology and its control/operational principles and validated its feasibility.
As regards the step-up operation, using (A1)-(A7), (9) and (11), the state-space average model of Fig. 4 can be expressed by the following equations: