MMC Based Hybrid Switched Capacitor DC-DC Converter MMC Based Hybrid Switched Capacitor DC-DC Converter

—Aiming to address the growth and the integration of renewable sources and electronic loads, different types of dc-dc topologies with speciﬁc features have been proposed, going from medium frequency isolated Modular Multilevel Converter to Switched Capacitor and Hybrid Switched Capacitor topologies. In this paper, a bidirectional Modular Multilevel Converter based Hybrid Switched Capacitor dc-dc converter is presented, featuring transformerless structure, automatic total arm voltages clamping/balancing, voltage static gain independent of the submodules quantity and efﬁciency with reduced duty cycle inﬂuence. The topology operates with a Quasi-Two-Level modulation, which provides passive components volume/weight reduction, a degree of freedom regarding the dv/dt applied on the magnetic windings and basis to perform the submodule capacitor voltages equalization within each arm. The topology operating principles are approached by an average value static analysis, while an instant value static analysis is used to estimate the operating current spike worst case. A 1 . 17 kW, 350 / 200 V laboratory scale prototype using IGBTs is implemented to experimentally conﬁrm the theoretical approaches.


I. INTRODUCTION
Intending to reliably interface medium/high voltage dc grids (MVDC/HVDC) and low/medium voltage dc power loads, such as electrical vehicles, electrified transport, data centers, etc, dc-dc converters based on multilevel topologies have been intensively studied in recent years, with the Modular Multilevel Converter (MMC) playing an important role in this scenario, mainly because of the modularity and capability of using well known electronic technologies provided by this topology.
In this context, medium frequency isolated MMC based dc-dc topologies have been proposed [1]- [3]. The galvanic isolation enhances the fault protection capability and the transformer turns ratio can be used to better interface the inverter and the rectifier stages. Moreover, the medium frequency operation leads to the converter volume/weight reduction. On the other hand, all the power processed by the converter must flow through the transformer and the higher frequency tends to increase the dv/dt applied on the windings, which can limit the medium transformer volume/weight reduction and make its design quite challenging [4].
In order to reduce the power processed by the transformer, the dc auto-transformer converter is proposed in [5]. Also based on MMC with Half-Bridge (HB) submodules (SM), this topology has a direct electrical connection between the inverter and the rectifier stages, allowing part of the power to flow straight from the input dc voltage source to the load and, then, reducing the transformer power rating up to half of the total power. However, this arrangement comes at the cost of loosing the galvanic isolation between the dc terminals, as well as part of the converter fault blocking capability, unless more complex SM configurations are used, instead of HB. Furthermore, the transformer can still be bulky, specially when the difference between the input and the output voltages is significant.
Due to the medium frequency transformer issues, some transformerless MMC based dc-dc converters have been studied [6]- [13]. In general, these topologies use either a capacitive path or the MMC arm inductors to perform the voltage balancing between the upper and lower arms. However, when the difference between the input and output voltages is significant, a high ac current and/or bulky arm passive components are needed to achieve this balance, leading to low efficiency and bad use of the components capacity in these cases. This drawback is addressed in [14], [15], where different current source modules are used to intermediate the energy transfer between the dc terminals. Since the increase of the SMs quantity takes to a decrease of the maximum output voltage, these topologies covers applications that demand high voltage ratio between dc input and output.
Another category of transformerless dc-dc converters is composed by the Switched Capacitor (SC), Switched Inductor (SL) and Hybrid Switched Capacitor (HSC) topologies [16]- [22]. The operating principle of these converters consists in parallel/series connecting groups of capacitors/inductors to process the energy, which results in high voltage ratio capability and converters with high power density. Moreover, self-voltage clamping and balancing of some components is achieved on SC and HSC converters. On the other hand, the efficiency dependence on the operating duty cycle, the large components count, the voltage ratio variation with the number of cells and the current/voltage spikes concern can impose some limitations or add complexity to these topologies. This paper is aimed to present a bidirectional MMC based Hybrid Switched Capacitor dc-dc topology. It is a transformerless converter, designed to avoid the arms voltage balancing ac components by using the voltage clamping feature of the SC converters. Furthermore, the proposed topology has a voltage static gain independent of the N SMs that compose each arm and can be operated in a region where the duty cycle influence over the converter efficiency can be minimized. The Quasi-Two-Level (Q2L) modulation [23] is used to reduce the passive components size, to create a degree of freedom regarding the dv/dt applied on the magnetic, by limiting the voltage steps on the windings [24], and to provide a voltage equalization method to balance the SM capacitors within each arm.
The proposed converter is introduced in [25], where more superficial and general topology analyses are developed. The current paper is conceived to provide a broader and more detailed mathematical approach regarding the topology operation, covering: two operation modes; an equivalent output resistance thorough analysis; a peak current estimation method that takes into account the Q2L transitions and the SM capacitance effects; and experimental results to compare with the analytical data.
This text is divided in a general topology overview, approaching the topological states and the applied modulation technique; an average value static analysis, to define the converter equivalent output resistance characteristic and the voltage static gain; an instant value static analysis, to address the SC current spikes; and the laboratory scale prototype experimental results along with discussion. Variables defined with small and capital initial letters represent ac plus dc signals and signal average or RMS value, respectively. Matrices are defined by bold and initial capital letter variables.

II. PROPOSED DC-DC TOPOLOGY
The topology presented in this paper is a transformerless bidirectional dc-dc converter based on the integration of the Three-Level Buck converter (or dc-dc Flying Capacitor converter) and the MMC. The representative diagram of the topology is presented in Fig. 1, which is composed by four series connected sets of N SMs, here defined as arms (A a , A b , A c and A d ), a flying capacitor (C f ) and an output LC filter composed by L o and C o . The LC filter input voltage is defined as v LC = v Lo + v o . All the analysis presented in this paper considers the topology operating in Buck mode, but can be similarly applied to obtain the Boost mode equations.
The SM configuration can be chosen according to some desired features. For example, HB SMs will provide a low account of semiconductors, reducing the converter complexity and losses. On the other hand, the use of Full-Bridge (FB) SMs in the upper arms (A a and A b ) provides bidirectional short-circuit interruption capability to the topology, improving safety and robustness. All the analysis presented in this paper considers equal HB SMs composing the proposed converter.

A. Topological states
Initially, it is considered that all the SMs within an arm operate equally, always changing to the same requested state at the same time. Therefore, the N SMs of each arm can be represented by an equivalent SM, where C eq,i = C sm /N and i ∈ {a, b, c, d} identifies the arms. Additionally, it is defined that an arbitrary arm assumes the state A i = 1 when the corresponding equivalent SM upper switch is off and the lower is on, bypassing C eq,i . On the other hand, A i = 0 when the upper switch is on and the lower is off, connecting C eq,i to the SM output.
Considering that A a = A d and A b = A c , in order to avoid short circuits and high voltage differences when the switched capacitor parallel connections are performed, four fundamental topological states, depicted in Fig. 2, can be obtained from the arms configuration.
The converter behavior during each topological state can be described as follows: ergy through L o to the output, increasing i Lo . C f exchanges charges with C eq,c . V H , C f and C eq,d also exchange charges among themselves; V H , C f and C eq,d also exchange charges among themselves; V H , C f and C eq,a also exchange charges among themselves; only L o transfers energy to the output on a free-wheeling behavior, decreasing i Lo . C f exchanges charges with C eq,b . V H , C f and C eq,a also exchange charges among themselves.

B. Modulation
To operate the converter, the Q2L PWM modulation is chosen. Basically, it is composed by one triangular carrier with peak value V p and by 4N modulation signals, one for each SM. Since A a = A d , there is always one modulation signal of A a equivalent to another of A d . The same can be applied to the pair A b and A c . These definitions are represented by the modulation signals v a,d The implemented comparison logic between the modulators and the carrier is The analysis of (1) leads to two different topology operating modes, where each one uses a distinct set of topological states. These modes are defined as Buck Mode 1 (BM1) and Buck Mode 2 (BM2), being implemented according to the amplitude of v a,d m and v b,c m .
The converter can change from one mode to another without discontinuities, basically varying v a,d m and, consequently, v b,c m . It results in only one static and one dynamic model for both modes, simplifying the topology analysis and the controller design.
The Q2L modulation is achieved by adding/subtracting a constant value ∆V m to/from each modulation signal. Consequently, the SM capacitors will be connected/disconnected to/from the circuit in a sequential order, adding a transition state between every subsequent topological states, as represented in Fig. 3.
The modulation signals condition, the set of states used and the respective duration times are summarized in Table I, where 0 ≤ D ≤ 1 is the duty cycle regarding the time interval that A a = A d = 1. Each transition duration time is defined as ∆t 12 = ∆t 23 = ∆t 34 = ∆t 41 = t tr .

C. Average Value Static Analysis
The objective of this analysis is to achieve a mathematical understanding about the topology currents and voltages average values, when it operates in steady state. From this, the voltage static gain and the equivalent output resistance  behavior, which is related to the converter conduction losses and inherent resistive voltage drops, can be obtained. Some considerations are made in order to simplify the analysis: • the switches and diodes have the same on-resistance R; • the switches saturation voltage is V sat and the diodes forward voltage drop is V f , unless otherwise specified; • each arm is composed by N SMs, represented by an equivalent SM with capacitance C eq,i ; • t tr << T s , making the transition effects negligible; • the converter operates in BM1, unless otherwise specified. The state-space representation of each topological state is created from the Kirchoff's Voltage and Current Laws, being defined byẋ The state-space inputs are V H , V f and V sat ; and the state variables A st and B st are 7-by-7 and 7-by-3 matrices, respectively, where st ∈ {1, 2, 3, 4} represents the respective topological state.
At first, the topology equivalent output resistor characteristic is approached. To achieve this mathematical model, the voltage ripple over C eq,i is considered negligible regarding the respective average value V Ceq,i . Moreover, V sat = V f = 0. The inductor current is also considered constant and equal I Lo . Thus, defining α ∈ {∆t 1 , ∆t 2 , ∆t 3 , ∆t 4 } as the currently analyzed time interval and T α φ as its respective initial time (e.g. where The initial values in (3) can be obtained by recursively equaling each v α Cf 0 to the respective previous state final value. Obtaining i ∆t1 a , i ∆t2 a and i ∆t4 a from the circuit analysis and knowing that I ∆t1 a = I Lo , the following relation is achieved Solving (5) leads to where On the other hand, i α b = i α a − i α Cf average value is zero within the interval from the beginning of ∆t 4 until the end of ∆t 2 and the following relation is achieved Solving (9) and replacing (10) in (6) leads, respectively, to and where The LC filter input voltage during ∆t 1 and ∆t 2 can be described by which results in It is shown in the subsequent analysis that V Ceq,a = V Ceq,b and V Ceq,c = V Ceq,d . Therefore, replacing (10) and (11) in (15) leads to where R eqo is a function of h Cf and D that represents the topology equivalent output resistance. Since R eqo (h Cf , D) is a quite large exponential equation, that do not provide a clear idea of the responses caused by varying h Cf and D, it is decided to present an abacus to illustrate R eqo . The lowest R eqo (h Cf , D) value is 2N R, which is obtained when h Cf → ∞. This value can be used to normalize R eqo , as follows Sweeping (17) for different values of h Cf and D results in the abacus presented in Fig. 4(a), which is intended to be used as a design guideline to find C f or the switching frequency f s . As typical for SC converters, the increase of h Cf leads the converter to operate in Partial Charge (PC) and No Charge (NC) modes [26], where R eqo and, consequently, the conduction losses are both reduced, because of the lower current spikes caused by the capacitors parallel connections. However, it also makes R eqo to be more independent of D, which is an interesting characteristic in terms of the converter efficiency when it is operated in closed-loop, since duty cycle variations will not significantly increase the conduction losses.
In order to reduce the conduction power losses and its duty cycle dependence, it is considered, from now on, that the converter operates with h Cf ≥ 0.5. Within this region, the maximum value that R eqo can assume is 1.04, approximately, which leads to an acceptable conduction loss penalty. Moreover, the R eqo variation with D is not significant. However, it must be considered that the reduction rate of R eqo decreases for higher h Cf values. In other words, the reduction in conduction losses tends to become unworthy regarding the switching frequency and/or C f increase, which is necessary to achieve such high h Cf . In this case, the switching losses and/or capacitor volume/weight tend to be the converter limitation.
Taking into account that additional resistances and inductances will be part of the converter, due to the actual components and PCB characteristics, a better damp of the current spikes tends to be achieved in real operation. Therefore, to simplify the converter design, it is assumed that this additional impedance sufficiently increases the total loop resistance, so that the definition of R as the highest conduction resistance between the used switch and diode results in a good trade-off between current spikes and component design.
Continuing the average value analysis, from (2) is also possible to obtain the following average value matrix The matrix B is similarly obtained.
In steady state,ẋ = 0. Therefore, the state-space variables average values are calculated by that results in where R o is the load equivalent resistance and It is verified in (20) that the total voltage average value on each upper arm is slightly higher than on each lower arm. It is due to the output current circulation through the semiconductors conduction resistances, which generates voltage drops that increase the upper arms and decrease the lower arms voltages.
Since V Co = V o , the topology voltage static gain (M V DC ) is defined by Replacing (20) in (2) for the used set of topological states, average value representations of C f and C eq,i currents (I α Cf and I α Ceq,i , respectively) are achieved for each time interval α. Therefore, applying the RMS mathematical definition to I α Cf along T s , the RMS values of C f currents for BM1 and BM2 are respectively defined as and Similarly, the average and RMS values of the equivalent SM lower switches (S i,L ) currents, shown in Table II, can be obtained. These equations are valid for BM1 and BM2.
It is important to mention that (20) is only valid when the converter operates in PC or NC, which are the charge modes aimed by the topology operation to minimize the conduction losses.
Despite of the method usefulness, the consideration of only average values results in zero voltage ripple on C eq,i and no current spikes. However, this is not a practical condition and non-linear currents will flow through C eq,i and C f . By estimating the current spikes values, it is possible to better calculate the converter switching losses and to prevent possible EMI issues. Furthermore, high power semiconductors with significant on resistances, such as SiC and silicon IGBT, may be used to build the converter, demanding a detailed conduction losses calculation. For this reason, an instant value analysis is developed to allow an estimation of C f peak current (i Cf,p ) and of the SM capacitors currents RMS (I rms Csm,i ) values.

D. Instant Value Static Analysis
This analysis basically consists in obtaining C eq,i voltages and currents equations as functions of time by solving (2). Once the analyzed system is composed by seven state variables, it is considered that, for simplification purposes, V sat = V f = 0 and v Cf is defined by (3). Additionally, i Lo time equations can be defined using (20) to find v Lo for the used topological states, since h Cf ≥ 0.5.
At first, considering only BM1, the transition states influence on this analysis has to be addressed. During t tr , an equivalent SM capacitor per arm is defined as follows C tr eq,i = Analyzing the interval from the beginning of ∆t 41 until the end of ∆t 12 , it can be stated that I d = 0 and the L o current average value is I Lo . Furthermore, according to the Table II, I a = I Sa,L = I Lo D during ∆t 1 . With some mathematical manipulation, it results in where I ∆t12 Ceq,a and I ∆t41 Ceq,a are the C tr eq,a currents average values during the respective transition intervals.
The currents that flows through C tr eq have a stepped waveform, due to the SMs voltages sorting algorithm. As an approximation, this current is considered to be a ramp that varies |I Lo | during t tr . Thus, C tr eq,i voltages can be defined as where β ∈ {∆t 12 , ∆t 23 , ∆t 34 , ∆t 41 } defines the considered transition interval and T β φ its respective initial time (e.g. The same method used to obtain (3) can be applied to define v {α,β} (30) The voltages v Ceq,b and v Ceq,c are defined as v Ceq,a (t − π) and v Ceq,d (t − π), respectively. The constants of (29) and (30) are shown in Table III, where k 2 = 1/2RC sm , ∆i α Lo is the variation of i Lo in the interval α and ∆v α Cf is the variation of v Cf in the interval α.
Taking C eq,a and C eq,d currents from (28) and (29), respectively, i Cf,p can be obtained. For BM1, the peak value happens at the beginning of ∆t 1 and can be normalized regarding I Lo , resulting in The normalized current i Cf,p is a quite large equation, function of h Csm , D, N , h Cf , t tr and p = ∆I Lo /I Lo , where ∆I Lo is the L o peak-to-peak current ripple and h Csm = RC sm f s . A similar process can be done to achieve i Cf,p for BM2.
To provide a better understanding of i Cf,p , the abacus of Figs. 4(b) and 4(c) are generated, where i Cf,p is plotted for different values of h Cf (changing C sm ) and D, adopting N = 3, t tr = 0.02T s and p = 0.25. Since i Cf,p tends to increase for lower values of h Cf , it is defined h Cf = 0.5, in order to have a worst case analysis. The normalized peak current tends to be lower and to have less sensibility, regarding h Cf m variations, when h Csm increases. It is because a higher C sm reduces the ripple of v Ceq,i , which becomes more negligible regarding V Ceq,i . Therefore, the latter ends up predominating on i Cf,p behavior.
It is noticed that i Cf,p increases when D → 0.5. This is because a pair of complementary arms tends to perform the SC connections on the same instant, the more D approaches to 0.5. It means that both arms peak currents will occur with a short time difference between each other. Since part of i Cf is composed by these currents overlap, it results in a higher i Cf,p .
Despite the assumed simplifications, the errors are within an acceptable tolerance (maximum of 5.7% for D = 0.5). Therefore, the presented methodology can be used as a i Cf,p related design guideline for C sm .
The equations (28) and (29) can be used to calculate the respective RMS values of the capacitors currents. To achieve a better precision, the sorting algorithm effect can be taken into account. These currents acquire a stepped waveform during the transitions, where the amount of steps, with t tr /(N − 1) duration time, increases/decreases every time the arm is transitioned. It means that the current of each SM capacitor changes in amplitude and duration, cycling in a frequency of f s /N due to the sorting logic.

III. EXPERIMENTAL RESULTS AND DISCUSSION
A laboratory scale prototype is used to proceed with the experimental verification of the topology operation. The prototype picture is presented in Fig. 5, whereas the parameters and components specification is described in Table IV. For C f and C sm film capacitors are used, due to their low ESR. The former capacitance is chosen to respect h Cf ≥ 0.5, whilst the laboratory component availability defined the latter. The inductance L o is chosen in order that ∆i Lo ≤ 0.25I Lo and the capacitance C o is designed so that the output filter resonance frequency is f s /20, at least. The output power is defined according to the available load bank. Generally, SC converters are implemented with MOSFETs, due to their resistive conduction characteristic. However, IG-BTs with ultrafast soft recovery diodes are used in this case, due to the laboratory components availability. Despite of being an oversized IGBT regarding the prototype parameters, there is the interest to verify the operational viability of using this technology in a HSC topology. Since IGBTs tend to have a higher conduction current capability than MOSFETs, the use of the former would increase the topology power processing level.
The first order model of an conducting IGBT is composed by a resistance plus V sat . As V sat is not considered in the instant value analysis, the converter can be designed by adopting an equivalent conduction resistance composed by the sum of (V CE , I C ) curve slope and V sat /I C , for I C = I o , resulting in R = 0.2 Ω.
The converter operation is analyzed for the two different buck modes. Since the specified parameters of Table IV result in D = 0.6, the rated converter operation occurs in    Fig. 4(c) results in a theoretical i Cf,p = 1.56. The difference regarding the experimental value is explained by the presence of the circuit stray resistances and inductances. Since the prototype is not designed to minimize these elements, the lower experimental i Cf,p is expected. Moreover, the considered abacus is implemented to a defined worst case, where h Cf = 0.5, also contributing for the obtained difference.
There is a predominance of i Lo over the switched capacitor exponential currents in i Cf composition. It is indicated by the nearly trapezoidal shaped v Cf ac component presented in the detailed waveform of Fig. 8(a). This behavior is consequence of choosing h Cf ≥ 0.5, since it places the SC converter stage in PC or NC operation.
The effects of the transition between topological states on v LC and i Cf , generated by the Q2L modulation, are presented in Fig. 8(b) for BM2. Despite of the high frequency oscillations, caused by the interaction of the circuit stray inductances and the semiconductors output capacitors, the voltage steps are clearly defined on v LC , as expected. It can also be noticed that, between every two steps, i Cf pattern changes during a short period. This behavior is caused by the SMs dead time and the stray inductances in series with each arm. When in dead time state, the SMs upper diodes become forward biased because of the stray inductances voltages, generated to keep the flowing direction of the arms currents. Considering D > 0.5, this behavior does not change the voltage levels applied on the filter input. On the other hand, when D = 0.5, the two pairs of complementary arms are transitioned at the same time, clamping the stray inductances voltages in a value that increases v LC during the dead time periods, as shown in Fig. 8(c). It does not change the topology basic operation when D = 0.5, however, it may influence on L o physical design, due to the variation of v Lo .
The voltages on the upper arms SM capacitors are slightly higher than on the lower arms, stabilizing in 61 V and 57 V, respectively, as depicted in Fig. 9(a). The calculated theoretical values are 59.6 V and 57.1 V, respectively. The high frequency distortions in both waveforms are switching noises circulating through the switches stray capacitances.
The SM sorting algorithm, implemented with the Q2L modulation, achieves the expected voltage equalization within the arms. To evaluate this functionality, a load step is performed, decreasing from 100% to 0% of the rated output power. The disturbance behavior of the A a SM capacitors voltages is presented in Fig. 9(b), where the proper equalization process can be noticed, with small deviation during the transient

period.
With the converter operating in closed-loop for V o , V Cf and I Lo , the zero load operation stability and the topology bidirectional characteristic are verified. Additionally, the prototype is designed with a low C o value, in order to assess the converter performance during considerable v o undershoot and overshoot conditions. Applying the same mentioned load step, V o converges to the rated value after the transition period, as depicted in Fig. 9(c). This behavior also confirms the bidirectional feature, otherwise, v o would settle in a higher amplitude, due to the impossibility to deliver the remaining inductor energy back to V H . No voltage unbalancing or overestimated peak currents take place under high v o variations. Furthermore, it is verified that the converter operating mode can be naturally changed from BM2 to BM1.
It can also be noticed that V Cf converges to a slightly different value after the disturb. This is because the variation of V Cf is physically performed by I Lo , that becomes too low to compensate the small static error in no load operating condition.
The achieved converter efficiency is 93.3% on the rated P o . Moreover, the obtained efficiency curve presents a typical buck-type behavior, indicating the negligible duty cycle influence on R eqo . The experimental data points and the respective trend curve are presented in Fig. 10 and are obtained with the converter operating in closed-loop, with V o = 200 V being applied on different load values. The efficiency reduction for P o < 360 W is due to the switching losses predominance over the conduction losses. However, this scenario is reverted when P o > 360 W. In this case, the higher P o , the lower is the difference between R o and R eqo , causing the efficiency decrease, influenced by the conduction losses, mostly.

IV. CONCLUSION
A bidirectional MMC based HSC dc-dc topology is proposed. It can be composed by different SM configurations (HB, FB, NPC, etc), according to the application requirements, and the number of SMs per arm is defined in order to attend the semiconductors blocking voltage limit. The Q2L modulation allows the equalization of the SMs capacitors voltages within each arm.
The absence of arm inductors allows the total arms voltages automatic clamping on half the input voltage, eliminating the need for a voltage balancing control among the arms. On the other hand, the acquired SC converter characteristics demand a low, duty cycle independent, output equivalent resistance and low current spikes oriented design, in order to increase the topology efficiency and to avoid harmful EMI issues.
Based on the achieved theoretical and experimental results, it can be inferred that the proposed topology can be suitable  Fig. 9. Steady state waveforms of (a) v Cf (Ch 2 -50 V/div), v Csm,a1 (Ch 3 -10 V/div) and v Csm,d3 (Ch 4 -10 V/div) for D > 0.5 (20 µs/div). The 100% to 0% load step transient waveforms of: (b) i Cf (Ch1 -5 A/div), v Csm,a1 (Ch 2 -50 V/div), v Csm,a2 (Ch 3 -50 V/div) and v Csm,a3 (Ch 4 -50 V/div) during a 100% to 0% load step (200 ms/div) and (c) i Cf (Ch 1 -5 a/div), v Cf (Ch 2 -50 V/div) and vo (Ch 4 -50 V/div) (100 ms/div) to attend low to medium voltage dc-dc applications, in the range of tens to hundreds of kW. The main bottlenecks that limit the use for higher voltages and powers are: the voltage applied to the flying capacitor, that, depending on the required capacitance, may lead to an expensive and bulky capacitor bank; the semiconductors switching speed attached to the number of SMs, since the transition time must be reasonable to cover all the steps and, at the same time, considerably lower than f s ; and the hard switching characteristic, that limits the increase of f s . Some future works suggestions are: converter implementation with GaN and SiC technologies, since some of the mentioned issues tend to be naturally addressed by them; flying capacitor replacement by MMC SMs, in order to overcome the bulky capacitor bank for high power and voltage applications; an interleaved topology variation can be evaluated, where two or more parallel connected converters divide the total power processing, allowing the increase of f s and, consequently, the use of faster semiconductors and smaller passive components; and the study of MMC based HSC dc-ac topologies.