Analytical Loss Model for Three-Phase 1200V SiC MOSFET Inverter Drive System Utilizing Miller Capacitor-Based dv/dt-Limitation

Next-generation Variable Speed Drive (VSD) systems utilize SiC MOSFETs to achieve both high efﬁciency through reduced bridge-leg losses and high power density through an order-of-magnitude increase in switching frequency or reduction of the DC-link capacitance. These systems, however, must con-tend with the high voltage slew rate (d v DS / d t ) of these next-generation power semiconductors, especially in the context of protecting the motor from partial discharge phenomena, surge voltages from cable reﬂections, and unequal distribution of the voltage across motor windings. We assess the attractiveness of an external Miller capacitor across the bridge-leg power semiconductors to limit the maximum voltage slew rate in a system. To evaluate this technique, we propose a maximum d v DS / d t model, ﬁnding that the maximum turn-on slew rate occurs at Zero-Current Switching (ZCS) with an increase in d v DS / d t as the device junction temperature increases. During the turn-off transition, the applied d v DS / d t saturates at a particular current. We then ﬁnd a switching loss model, arriving at a piecewise-linear dependence of bridge-leg switching losses on current under d v DS / d t -limited conditions, a ﬁnding that runs counter to the widely-utilized quadratic current dependence. The proposed models are validated on a SiC MOSFET bridge-leg designed for a 10 kW 800 V DC-link Variable Speed Drive (VSD) system with a switching frequency of 16 kHz, where the Miller capacitor-based technique achieves lower losses (for the same maximum d v DS / d t ) than a gate resistor-only d v DS / d t limiting approach. This SiC MOSFET bridge-leg achieves peak calculated bridge-leg efﬁciencies of 99 . 2 % for a d v DS / d t limitation of 10 V / ns and 99 . 4 % for a limit of 15 V / ns.


I. INTRODUCTION
Variable Speed Drive (VSD) inverter systems are critical for the efficient electrification of the mobility, manufacturing, and logistics sectors, with VSD-driven industrial motors projected for over 30 % of electricity growth to 2040 [1]. More broadly, VSD-driven motors are rapidly replacing single-speed motors for higher efficiency, better control, and lower operating costs.
For the switching power semiconductor devices, state-ofthe-art VSD inverters use Insulated Gate Bipolar Transistors (IGBTs), often with a blocking voltage of 1200 V, accompanied by anti-parallel freewheeling diodes. IGBTs incur high switching losses due to the bipolar on-state carriers, and these switching losses limit the switching frequency of industrial drives that utilize IGBTs to 4 kHz to 16 kHz, typically.
With the most recent commercialization and adoption of Silicon Carbide (SiC) Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), these switching frequencies can be extended by nearly an order-of-magnitude, enabling full sine-wave filtering [2], [3] and higher performance on both power density and efficiency (including at partial load [4]), simultaneously. Relative to IGBTs with the same blocking voltage, SiC Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) incur significantly lower switching losses due to the unipolar carrier characteristic, lower conduction losses due to fundamental material improvements [5], [6] and the lack of an on-state voltage drop in forward or reverse conduction, and support synchronous rectification. Further, the internal body diode of the MOSFETs eliminates the need for external freewheeling diodes. Overall, SiC MOSFETs support smaller overall chip areas, lower conduction and switching losses, and higher switching frequencies for smaller highfrequency motor losses and lower DC-link capacitance for given switching frequency voltage ripple.
These next-generation VSD systems (like the three-phase VSD shown in Fig. 1) must contend, though, with new complications introduced by the faster switching speeds of SiC MOSFETs. High slew rate voltages, or dv/dt values, at the output of the VSD can lead to partial discharge phenomena and progressive insulation aging of the motor [7], [8], unequal distribution of the voltage across the motor windings, and/or surge voltages from reflections in long motor cables. VSD systems must meet critical standards that protect industrial motors from these deleterious effects [9], [10]. One method of dv/dt-limiting is to implement a full sine-wave LC-filter to limit the dv/dt applied to the motor, but this approach carries the familiar drawbacks of additional highpower passive components: volume, design and realization effort, and cost [11]. Alternatively, the voltage slope applied to the motor can be limited directly through other techniques, but with industrial IGBTs feature switching speeds of only 1 V/ns to 5 V/ns [12] while SiC MOSFETs can achieve slew rates of up to 100 V/ns, a deeper exploration of dv/dt-limiting concepts is required.
The most straightforward approach to limit the dv/dt applied to the motor is with a dv/dt-filter, where an LC-filter with a resonant frequency above the switching frequency is implemented between the switching stage and the motor terminals (or the cable). Different passive filter implementations to limit dv/dt applied to the motor include a damped LCRfilter [13] or an undamped LC-filter with Diode-Resistor-Capacitor (DRC) damping [14], which utilizes a pair of diodes but does not require active control. Combined Differential-Mode (DM) and Common-Mode (CM) filters, further, feature capacitors connected to the DC-link rails [15], [16] and limit both bearing currents [17] and radiated electromagnetic emissions [18]. Finally, as a combination of a passive filter and an active control scheme, an undamped LC-filter can be combined with an adaptive switching cycle to enforce resonant transitions without overshoot [19], [20]. Each of these concepts reduces the filter requirements relative to a bulky full sine-wave filter, but still require the design, implementation, and realization of multiple passive components that diminish the benefits of the adoption of SiC MOSFETs in VSD systems.
Alternatively, the dv/dt applied to the motor can be limited through gate drive control of the MOSFET directly. The simplest approach is to increase the resistance of the gate resistor to increase the gate time constant [21] (including with multiple discrete gate resistance values [22]), leading to slower switching transients and higher switching losses but lower dv/dt slew rates. An improvement to this approach, as shown in Fig. 1, is to implement a conventional gate driver with gate resistor and an additional Miller feedback capacitor connected between the gate and drain of each MOSFET [23], [24]. The additional Miller capacitor influences the transient of the switch-node voltage but, unlike an oversized gate resistor, does not have a meaningful effect on the gate time constant. A larger Miller capacitance prevents, a priori, fast voltage transients instead of filtering them out, linearizes the gate voltage (especially valuable for Gallium Nitride (GaN) [24]), and is small in both capacitance value and size. Further, unlike alternative gate drive modifications that require additional active circuits [25], [26] or closed-loop concepts to control dv/dt [27]- [29], the Miller capacitor concept is simple, compact, and straightforward to implement.
Despite the performance promised by the Miller capacitor concept for next-generation VSD systems, there is limited literature on the optimal Miller capacitor configuration for SiC MOSFETs [25], with more for GaN-based systems [24], [26], [30]. None of this prior work, however, includes (a) accurate modeling and analysis for SiC MOSFETs or (b) the effect of the Miller capacitor on overall system performance beyond dv/dt, most notably on switching losses and the shorter deadtime (and lower diode conduction losses) supported by the faster gate time constant.
Motor-integrated VSD systems support dv/dt values as high as 10 V/ns to 15 V/ns, as no cable reflections need to be considered with direct motor integration. In [31], we analyzed a number of approaches to meet these dv/dt requirements in an V dc = 800 V VSD system, and found the Miller capacitor solution promised the best analytical performance. In this paper, we extend this work into a complete switching loss model for SiC MOSFETs with an external Miller capacitor, first revisiting the switching behavior of a bridge-leg and experimentally validating the effect of the Miller capacitor on the switching transient (Section II). From there, we find a parametric gate drive model to enable the selection of a gate resistor and Miller capacitor combination to achieve the desired voltage slew rate during turn-on and turn-off, and propose and validate a loss model for the switching losses across these voltage slew rates that unifies turn-on and turn-off switching loss models under soft-and hard-switching conditions (Section III). In Section IV, these switching losses are validated on a 10 kW VSD, where the inverter losses are derived for sinusoidal current and then verified by measurements with both an external Miller capacitor and under conventional operation, achieving a peak bridge-leg efficiency of 99.4 % at a 15 V/ns slew rate limitation. In Section V, we provide a design approach for implementing dv/dt-limited VSD systems. Section VI concludes the paper and points to further improvements for Wide-Bandgap (WBG)-enabled, motor-integrated, next-generation VSD systems.

II. SWITCHING BEHAVIOR WITH AN EXTERNAL MILLER CAPACITOR A. SWITCHING BEHAVIOR EXPLANATION
To understand the external Miller capacitor (C M ) approach under investigation, we first must analyze the effect of C M on the switching transient. To investigate this switching behavior, we consider a half-bridge configuration with a high-side T h and a low-side transistor T l connected to a DC-link with the voltage V dc and driving an ohmic-inductive load with both positive and negative load currents i L (such that either a strictly positive or strictly negative current is seen during a switching cycle). In Fig. 2, the half-bridge power semiconductors are each shown with a gate driver and an explicit Miller feedback capacitor For a positive load (and switched) current, the load is connected to the negative DC-link rail, as shown in Fig. 2(a.i). When T h is conducting, the load current i L is increasing (under v DS = V dc ) until the switching transition occurs, at which time T h is turned-off and i L = i off (Fig. 2(b.i)). This triggers a Zero-Voltage Switching (ZVS) turn-on transition [32] for the low-side switch T l and a ZVS turn-off transition for the high-side switch T h , where the effective switch-node capacitance is the combination of the output capacitances of the high-side C oss,Th and low-side transistor C oss,Tl and both Miller capacitors C M (as both switches are off). This switchnode capacitance defines the slope as the switch-node voltage v DS discharges from V dc to zero, at which point the voltage transient ends and the load current flows through the low-side diode.
After the enforced dead-time t D , the low-side transistor is turned-on and the load current commutates from the diode to the MOSFET channel (note that the low-side transistor, under a strictly positive current condition, cannot trigger any transitions and only enables synchronous rectification). While the low-side switch is on, the current decreases (v DS = 0 V) until T l is turned-off again at i L ≈ i on > 0 A and the current commutates back from the channel to the low-side diode. Again, after an enforced dead-time t D , T h is turned on and a hard-switching event occurs i L = i on . This hard-switching event discharges C oss,Th and the high-side C M while charging C oss,Tl and the low-side C M to bring the switch-node voltage v DS from zero to V dc , and this fast transient typically causes a voltage overshoot caused by an oscillation between the equivalent output capacitance and the commutation loop inductance.
Under a negative load current, where the load is equivalently connected to the positive DC-link rail ( Fig. 2(a.ii)), the behavior of T h and T l are reversed, with the high-side device transistor turned-on under ZVS and the low-side transistor hard-switched at turn-on, as shown in Fig. 2(b.ii).

B. EXPERIMENTAL VALIDATION
To validate our understanding of the effect of the external Miller capacitance on the switching transition, we construct a half-bridge using two next-generation low-R DS,on SiC MOS-FETs (C3M0016120K [33]) and a gate driver with an output clamp variant (for enhanced noise immunity) [34] that drives the transistors at the maximum positive (V G,on = 15 V) and minimum negative (V G,off = −4 V) gate drive voltages. The Miller capacitor is implemented with a Mica capacitor [35], which has low dissipation factor, linear capacitance, and is rated for transients up to 20 V/ns [35]. Turn-on and turn-off behavior for the half-bridge is measured under Double-Pulse Test (DPT) conditions, and we define the rise time t r and fall time t f of v DS as the time interval between 10 % and 90 % (or 90 % and 10 %) of the DC-link voltage V dc with a resulting voltage slope dv DS Firstly, we measure and analyze the behavior for R G = 0 without a Miller capacitor (C M = 0 pF), as reported in Fig. 3. The turn-on transition occurs under Zero-Current Switching (ZCS) conditions (I on = 0 A) and the measured slew rate is dv DS /dt = 60 V/ns, with the turn-off transitions at I off = 5 A and I off = 40 A achieving voltage slew rates of 6.1 V/ns and 45 V/ns, respectively. We might expect the voltage slew rate to increase by a factor of 8 with an 8× increase in current; instead, we find an increase of 7.4 and encounter the saturation of dv DS /dt under high-current switching conditions that was reported in [36]. For all of the measured turn-on and turn-off transitions in Fig. 3, the drain-source voltage transitions nearly linearly between 10 % and 90 % (or 90 % and 10 %), justifying the previously-introduced derivation of voltage slope based on the rise (or fall) time.
The power loop inductance can be estimated from the oscillation frequency of the commutation loop, which is measured at 71 MHz in Fig. 3(a.ii) and corresponds to 20 nH, which originates primarily from the parasitic inductances of the two TO-247 packages. Even with a current slew rate of 2 A/ns, a reasonable value for the gate resistors considered here, the inductive voltage drop is only 40 V -less than 5 % of V dc , and safely neglected in the subsequent analysis.
Next, the gate resistor is increased to R G = 30 while maintaining zero Miller capacitance (C M = 0 pF), which slows the turn-on voltage slew rate significantly to 8.8 V/ns. We find, perhaps unexpectedly, a negligible effect on the turnoff slew rate at 5 A (measured at 5.7 V/ns), but the highcurrent turn-off transient slew is reduced from 45 V/ns to 9.0 V/ns. The gate transient, as we see in Fig. 3(b), is also much slower relative to the reference case with R G = 0 .
Finally, an arbitrary Miller capacitance of C M = 50 pF is added to the half-bridge, and a much-lower gate resistance of R G = 10 is selected to achieve the dv DS /dt at turn-on as for the R G = 30 case ( Fig. 3(a.i)). The gate transient is now faster than for the large gate resistance case (although still slower than for the R G = 0 , C M = 0 pF case, as expected), and we again find little effect on the turn-off transition at 5 A (measured at 5.6 V/ns) but a large influence on the highcurrent transition (slew measured at 11.5 V/ns at 40 A).
At low current levels during turn-off, the rise time may become longer than the dead time t D , which is selected to minimize the diode conduction losses. Under these conditions, a partial hard turn-on event occurs, causing an incomplete ZVS transition (see [32] for a more complete discussion). During this turn-off transition, the gate-source voltage decays to a negative voltage during the dead time, and, when the second transistor turns on after the dead time (but before the transition is complete), a ZCS-like transition occurs for the remaining voltage difference, with a fast dv DS /dt transient. A measured waveform for this event is shown in Fig. 4 (for R G = 10 , C M = 50 pF) at a turn-off current of 1 A and a dead time of 400 ns. Because the low current (which must be the case to cause this condition) causes a slow transition during the dead-time, the slew rate limitation is still met under these conditions. We see, then, that the Miller capacitor slows the voltage transient, as desired, and that the Miller capacitor can achieve different turn-on and turn-off voltage slew rates with the same gate resistor. For the same drain-source voltage slope, the Miller capacitance solution has a faster gate transition than a gate resistor alone, which could be beneficial. Most importantly, though, we find a significant dependence of the voltage slew rates dv DS /dt on the switched current, an influence beyond the gate drive parameters R G and C M alone, and this warrants a deeper investigation.

C. VOLTAGE SLEW RATE MEASUREMENTS ACROSS SWITCHED CURRENT
To understand the current dependence of the slew rate, the voltage slew rate dv DS /dt is measured across switched current with and without the Miller capacitor. We sweep the At turn-on, we find that dv DS /dt reduces with higher switched turn-on currents I on , with the maximum slope occurring at ZCS (dv DS /dt| 0 ). This aligns with conventional theory with a transconductance g m , where the Miller voltage increases at higher currents as v M = v th + I on /g m and the slew rate goes as dv DS /dt| on ∝ V G,on − v M . We also find a temperature dependence by applying continuous switching under ZCS (rather than the DPT) at around 100 • C junction temperature, which is indicated by the black dots in Fig. 5 and achieves higher a dv DS /dt than ZCS under DPT conditions (with a junction temperature near room temperature). The maximum measured voltage slope under turn-on (at the elevated junction temperature) is dv DS /dt| 0 = 9.8 V/ns without the Miller capacitor and 7.4 V/ns with C M = 20 pF.
At low turn-off currents and under ZVS, the voltage slew rate dv DS /dt scales with the switched turn-off current I off . At higher switched currents, though, the voltage slope dv DS /dt saturates, replicating the "kink current" I k behavior found in [36]. The kink current is: with C eff = 2C dQ,oss + 2C M + C par and C dQ,oss as the chargeequivalent capacitance [32] of the transistor between 10 % and 90 % of the DC-link voltage. Without an external Miller capacitance, and considering C M and any parasitic capacitance C par as negligible compared to C dQ,oss , the effective capacitance is C eff ≈ 2C dQ,oss = 666 pF and the kink current is I k,A = 6.5 A. With C M = 20 pF, the kink current is I k,B = 4.9 A as a result of the reduced dv DS /dt| 0 , with these values labeled in Fig. 5 (although the kink current transition from rising slope to saturated is relatively smooth here). In sum, then, the external Miller capacitance C M maintains the behavior of the voltage slew rates across current, but reduces dv DS /dt overall and can be used with a gate resistor to achieve the desired voltage slope. That said, the important saturation current characteristic mandates a deeper investigation of the switching behavior during a transition, leading to an analytical model for both dv DS /dt and switching losses for any gate resistance and Miller capacitor combination.

III. DV/DT AND LOSS MODELS
In this Section, we derive a dv DS /dt model to find suitable gate drive configurations (for an arbitrary power semiconductor device) to achieve a desired dv DS /dt and a related switching loss model for determining turn-on and turn-off losses. First, we return to a deeper investigation of the half-bridge during a switching transition to better understand the detailed models derived here. Fig. 6(a) shows the equivalent half-bridge circuit present during the turn-off and turn-on transition of the low-side switch (T l in Fig. 2(a)), with the corresponding waveforms shown in Fig. 6(b). Here, we limit our focus to the switch-node voltage transient, with the broader gate and bridge-leg waveforms detailed in [22], [25]. The switching current I sw is assumed positive (hard-switching T l at turn-on), constant during the switching transition, and with a magnitude greater than the kink current as I sw > I k . The waveforms use a straight-line approximation and C DS represents the charge equivalent output capacitance between the drain and source, including the drain-source capacitance of T l , the output capacitance of T h (indicated in the figure only with a free-wheeling diode to which I sw commutates) and any additional parasitic capacitances, such that C DS = C oss,Th + C ds,Tl + C par .

1) TURN-OFF TRANSITION
At turn-off ( Fig. 6(a.i) and Fig. 6(b.i)), the initial condition is with T l turned on, such that the gate is charged to V G,on . The gate driver applies V G,off , and the internal gate-source voltage is reduced and clamped at the Miller voltage v GS,i = v M = v th + I sw /g m . We assume a strict Miller plateau, such that v GS,i = v M is strictly true and therefore no current flows to C GS . Through KVL, we can then Using the straight-line approximation such that d 2 v DS dt 2 = 0 V 2 /s 2 , we find our model for dv DS /dt during the turn-off transition: with an additional fitting time constant τ off to account for further delays, perhaps inside the semiconductor or the semiconductor package. With no external gate resistor (R G,off = 0 ), the internal gate resistance R int limits the voltage slew rate.

2) TURN-ON TRANSITION
At turn-on ( Fig. 6(a.ii) and Fig. 6(b.ii)), T l is turned off and the gate is therefore charged to V G,off . The gate driver applies V G,on , and we can follow the same analysis as for the turnoff model -with the important exception that v GS,i = v th because the device is turned-on under ZCS to consider the worst-case dv DS /dt ( Fig. 6(b.ii) shows the behavior for a current value I sw different from zero). During turn-on, the voltage slew rate is: C GD corresponds to the charge-equivalent gate-drain capacitance. Although the local value (c GD ) is voltage-dependent and non-linear, the external Miller capacitor linearizes or even dominates the total gate-drain capacitance. The drain-source voltage change is therefore more linear, and we emphasize   The results are reported in Fig. 7, with the modeled voltage slope shown as lines and the measured slope as dots. The turn-on model is fit to the measurements with v th = 6.0 V, C GD = 24.5 pF, R int = 2.2 and τ on = 143 ps, and the turnoff model is fit with v M = 8.7 V, C GD = 45.7 pF, R int = 2.5 and τ off = 151 ps. These parameters are quite similar, as desired, with the large deviation for C GD assumed to originate in the different contribution of C GS between turn-on and turn-off since the Miller plateau is not perfectly flat [37], [38].
The proposal models match the measurements across gate driver circuit values, supporting the selection of suitable gate resistor-Miller capacitor combinations to achieve the desired voltage slew rate in any application. In Fig. 7, our targets of dv DS /dt| 0 = 10 V/ns and dv DS /dt| 0 = 15 V/ns are highlighted, with the Miller capacitance and gate resistor values that result in those maximum slew rates summarized in Table 1.

B. DV/DT RELATED LOSS MODEL 1) LOSS MEASUREMENTS
We see in Table 1, then, that different gate drive parameter combinations can achieve the same maximum voltage slew rate, but recall from Fig. 3 that the time-domain behavior can be quite distinct among them. Here, we explore if this degree of freedom can be used to minimize switching losses, and derive a suitable -and novel, for turn-on losses -model for switching losses.
We use the thermal transient measurement method [39] to conduct ZCS-only, turn-off-only, and turn-on and turn-off loss measurements for all six sets of gate drive parameters that achieve our maximum voltage slew rates in Table 1. These results are given in Fig. 8 across turn-on and turn-off currents, where we report the loss measurements alongside the measured dv DS /dt for a single transition (Fig. 8(a)) under continuous half-bridge operation (Fig. 8(b) and Fig. 8(c)). We see, upon a quick examination, that the losses depend, to first order, upon dv DS /dt but that the tradeoff between gate resistor and Miller capacitor value has almost no influence, and we move to find a suitable loss model that explains this behavior.

2) TURN-OFF LOSS MODEL
A detailed turn-off loss model is given in [36], and only a short summary is given here.
For currents below the kink current, only the resonant charging-discharging C oss -losses [40] occur during turn-off, denoted as E 0 . Above the kink current, the voltage slew rate dv DS /dt saturates and a portion of the load current flows through the channel, resulting in losses of E 0 + k off (I off − I k ), with k off = 1 2 V 2 dc / dv DS dt | 0 . Turn-off switching losses are, then: with I off > 0 A. Note that the gate current flows as i G = −i C,M − i C,DG (with the gate charge related to the Miller plateau Q G0 = i G0 t r0 ), which corresponds to the charge requirements of C M and C GD and must be absorbed by the gate driver itself. For our application here, we apply (1) and find I k10 = 6.6 A for dv DS /dt| 0 = 10 V/ns and I k15 = 10 A for 15 V/ns.

3) TURN-ON LOSS MODEL
During the turn-on transition, the charge corresponding to the total capacitance Q tot = Q oss (V dc ) + (C M + C par /2)V dc is charged/discharged via the channel, resulting in ZCS losses of V dc Q tot . If dv DS /dt is assumed as independent of load-current, a reasonable approximation from our findings in Section II (see Fig. 5), then the current-dependent losses increase linearly with the current as k on I on and can be considered the losses associated with dv DS /dt-overlap. The turn-on losses, then, can be described as E sw,on (I on ) = V dc Q tot + k on I on , or: For turn-on losses, our model utilizes the values Q oss (V dc ) = 344 nC, C par = 100 pF (PCB), and a neglected charge contribution from the Miller capacitor for Q tot = 384 nC. We fit k on = 1. 35 2 V 2 dc / dv DS dt | 0 , with the factor of 1.35 interpreted as a waveform correction factor for the turn-on losses.

4) UNIFIED LOSS MODEL
Finally, we can unify the two loss models, finding a linear piecewise function for half-bridge losses that is distinct, and novel, from the typical assumption of a quadratic loss model that is dependent on current.
With a simple summation, and neglecting E 0 which is always small fraction of V dc Q tot [40], the half-bridge switching losses E sw (I sw ) = E sw,on (I on ) + E sw,off (I off ) at a low current ripple (i.e. I sw ≈ I on ≈ I off ) result in a piecewise linear function: These linear functions intersect at the value of the kink current I k , which is dependent -along with k on and k off -on the selected maximum voltage slew rate dv DS /dt| 0 . Critically, half-bridge switching losses are actually piecewise-linear on I sw , rather than quadratic [39], with the kink current I k playing a critical role as the intersection of these functions and the switched current value after which switching losses start increasing more rapidly. This arises because of the lack of dependence -in either turn-on or turn-off losses -on di/dt, as mentioned previously [22], [25]. The proposed model is validated in Fig. 8(b) and Fig. 8(c), with the turn-off losses measured directly and with tight matching (cf. Fig. 8(i)). Turn-on losses cannot be measured directly easily, so we instead measure half-bridge losses with a small current ripple, which are comprised of one turn-on and one turn-off transition, and report the total measured losses (cf. Fig. 8(ii)). The obtained parameters for the switching loss model are reported in Table 2.

IV. CASE STUDY: 10 KW MOTOR DRIVE SYSTEM
The derived dv DS /dt and loss models are validated by measuring the losses (thermally [39]) of a single C3M0016120K bridge-leg of a VSD system for an electric motor, as shown in Fig. 1. The specifications for this motor drive are V dc = 800 V, P M = 10 kW,î nom = 25 A pk ,î opt = 20 A pk , M = 0.8, M cos φ = 0.68 [31] with a switching frequency f sw = 16 kHz to remain outside the audible range [41].
With large motor inductances, the output phase current is sinusoidal under Continuous Current Mode (CCM) with a low ripple. For a sinusoidal phase current i( ) =î sin( ), the output power is P INV = 3 4î V dc M cos φ. The half-bridge losses will include both conduction and switching losses as P HB = P cond + P sw , with conduction losses as P cond = 1 2 R DS,onî 2 (with current ripple neglected) and the switching losses P sw = f sw 1 2π 2π 0 E sw (i( ))d . Using the derived loss model of (8) for the switching losses, the total half-bridge losses are: and the bridge-leg efficiency is: The power semiconductor losses and bridge-leg efficiency are measured with the gate driver circuit parameters of Table 2 under the maximum voltage slew rates of 10 V/ns and 15 V/ns, with the results shown in Fig. 9. The modeled conduction losses use an on-resistance value of R DS,on = 20 m , which corresponds to a junction temperature of 100 • C. The die area of the selected C3M0016120K SiC MOSFETs is optimal for a phase current of 20 A pk [31], which we denote asî opt .
The loss measurements match neatly with the total loss predicted by the proposed loss model across maximum slew rate dv DS /dt| 0 limits, phase current, and combinations of gate resistance and Miller capacitance. With the 10 V/ns maximum slew rate constraint, the measured bridge-leg losses are P HB = 22.3 W forî opt = 20 A pk without the Miller capacitor and improve to 20.9 W with C M = 50 pF. Similarly, with the same 10 V/ns maximum slew rate but atî nom , the measured bridge-leg losses are P HB = 29.9 W without the Miller capacitor and improve to 27.3 W with C M = 50 pF. With a higher slew rate limitation of 15 V/ns, the measured bridge-leg losses are reduced relative to the 10 V/ns case, as expected, from 17.2 W (C M = 0 pF) to 16.3 W (C M = 50 pF) atî opt and from 22.3 W (C M = 0 pF) to 20.9 W (C M = 50 pF) atî nom .
For the slew rate limit of 10 V/ns, the maximum calculated bridge-leg efficiency reaches 99.2 % at 17.0 A pk and for the maximum slew rate of 15 V/ns, the maximum calculated bridge-leg efficiency reaches 99.4 % at 18.1 A pk . Without the slew rate limitation (0 gate resistance, which reaches a slew rate of 60 V/ns, as reported in Section II), the peak bridge-leg efficiency is 99.6 % (calculated based on [31]), as shown with the dotted line in each plot in Fig. 9.
For the slew rate limit of 10 V/ns, the maximum calculated bridge-leg efficiency reaches 99.2 % at 17.0 A pk and for the maximum slew rate of 15 V/ns, the maximum calculated bridge-leg efficiency reaches 99.4 % at 18.1 A pk .

A. PERFORMANCE COMPARISON TO A Dv/Dt-FILTER-BASED SLEW RATE LIMITATION
To evaluate the performance of the proposed Miller-capacitorbased approach, we compare the system volume and losses with a conventional dv/dt-LC-filter-based approach [14] to meet the same slew rate limitation. We derive a simple volume model and use the filter loss model from [31] for the comparison.
The volume of the power stage is primarily driven by the volume of the heatsink. We assume a maximum hestsink temperature of T HS = 85 • C and an ambient temperature of T amb = 45 • C, and use the Cooling System Performance Index (CSPI) approach [42] with a typical CSPI of 20 W/KL to calculate the heatsink volume Vol HS . The design equations for the heatsink volume are: For a three-phase inverter at nominal operation (î nom = 25 A pk ) and a slew rate limit of 15 V/ns ensured by the discussed gate drive modifications, the inverter heatsink volume is Vol HS = 81 cm 3 (for maximum semiconductor losses of 64.6 W atî nom = 25 A pk ) with total losses of 50.5 W at i opt = 20 A pk . Without the slew rate limitation (0 gate resistance, which reaches a slew rate of 60 V/ns, as reported in Section II), the peak bridge-leg efficiency is 99.6 % at 21.3 A pk and the power stage heatsink volume is reduced by almost 40 % to 51 cm 3 (for maximum semiconductor losses of only 41 W atî nom = 25 A pk ).
Without the bridge-leg slew rate limitation, the dv/dt-LCfilter is now required to protect the motor winding system. We use, as a reference, an LC-filter with DRC damping branches (connected between the filter output and the positive and negative DC bus, [14]) this is designed for the same application scenario with 15 V/ns. If we consider the Permanent-Magnet Synchronous Motor (PMSM) 1FT7084 from Siemens [43], the dv/dt-filter capacitor of a phase needs to be at least C o = 1.5 nF [31], which can be implemented with a Mica capacitor [35] for a volume of only 0.1 cm 3 per phase. While this small capacitor volume can be easily neglected, the filter capacitors introduce additional capacitive switching losses, resulting in additional losses of P C = 3 f sw C o V 2 dc = 46 W that are dissipated in the damping resistors. An additional heatsink for these resistors (which we allow to reach T HS,R = 125 • C, as power resistors can be operated at high temperatures) requires a volume of Vol HS,R = 28.8 cm 3 .
According to [31], in each phase a filter inductor with L o = 1.2 µH is required which causes a current swing of 28 A, thus the inductor must be designed to saturate above 58 A. This filter inductor can be implemented with the HCI Inductor from Würth Elektronik [44] for only 3 cm 3 of additional volume per phase.
In sum, then, a dv/dt-limiting passive LC-filter with DRC damping (in each phase) achieves a system volume of 89.4 cm 3 and system losses atî opt of 79 W, for an overall system volume increase of 10 % and an overall system loss increase atî opt of 56 % compared to the Miller capacitor approach (efficiency reduction from 99.4 % to 99 %). Further, the relatively large filter inductors may prevent automated assembly of the power stage and the filter approach is sensitive to the selected motor since the filter capacitor C o must dominate the motor capacitance [31]. The proposed Miller capacitor approach is, in contrast, not sensitive to the motor characteristics, as any additional parasitic capacitance only increases C eff and the kink current I k but does not influence the dv/dt limit, which depends only on the gate drive configuration (cf. (2) and (3)). This increase in kink current reduces the turn-off losses, while the increased ZCS losses only occur inside the motor.
In sum, then, the combination of SiC MOSFETs and a slew rate limit enforced with an external Miller capacitance uniquely enables high-performance VSD systems -without the significant size, weight, or cost associated with bulky filters -that clearly exceed the IGBT bridge-leg efficiency limit of ≈ 98 % [31] while protecting motors from high voltage slew rates.

V. DESIGN PROCEDURE FOR VOLTAGE-SLEW-RATE-LIMITED BRIDGE LEGS
With a voltage slew rate limitation on the bridge-leg itself attractive in many VSD systems, we provide a design procedure to implement the dv DS /dt-limitations explored in this work. The goal of this section is to summarize the critical design steps for a tangible and straightforward guide to apply dv DS /dt limits in motor drives with a sinusoidal phase current with peak valueî.
1) The specification of the application must be defined, including the maximum slew rate dv DS /dt| 0 and DC-link voltage requirements. 2) Select the transistor technology based on the blocking voltage (the DC-link voltage, with margin) and other considerations, including cost and preferred manufacturers. a) For this transistor family, devices with a range of on-resistances are typical available. b) The loss minimum chip area -based on the on-resistance R DS,on at the desired junction operating temperature T J,op , and the output charge Q oss (V dc ) = V dc 0 c oss (v)dv (all of which can be determined from the datasheet) -is [31]: 3) With the power transistor now selected, we move to the configuration of a gate drive, where we have to distinguish two cases: a) For the known half-bridge configuration of Section II, with existing data from this work for the C3M0016120K [33] and a gate driver with an output clamp variant, the designer may straightforwardly select: i) C M = 50 pF should be selected for maximum performance, as it achieves minimal losses without causing instability through excessive gate ringing. ii) A minimum effort implementation with no Miller capacitor (C M = 0 pF) and elevated gate resistors incurs a switching loss increase of 6 % to 8 %. iii) The corresponding on and off resistances for the given dv DS /dt| 0 -limit can be selected according to Fig. 7. b) If, alternatively, the half-bridge power semiconductors and/or gate drivers have not been characterized: i) An evaluation bridge-leg must be constructed to conduct simple voltage slope measurements, as described in Section II. ii) Testing should begin with C M = 0 pF, and the turn-on resistance should be gradually increased (with R G,off = 0 ) until the voltage slope limit is reached under continuous ZCS conditions, with the switching frequency selected to achieve a junction temperature close to the maximum operating temperature T J,op in the application. iii) After this sweep is completed, R G,on should be fixed and R G,off can be selected such that the same voltage slope limit is achieved during turn-off at the maximum phase current and under DPT conditions (room temperature device). iv) To further increase the performance, the prior two steps can be repeated for different Miller capacitor values, stopping before a maximum value where additional ringing occurs in the gate-source voltage during transients. 4) With the Miller capacitance selected, the effective capacitance is C eff = 2C dQ,oss + 2C M + C par , where C dQ,oss = 0.9V dc 0.1V dc c oss (v)dv is the charge-equivalent capacitance of the transistor between 10 % and 90 % of the DC-link voltage and C par includes the parasitic capacitance of the PCB and the load, which appears between switch node and either one of the DC-link rails. 5) Between C eff and the slew rate limit dv DS /dt| 0 , the kink current I k is fully-known from (1): and the loss coefficients are: 6) The half-bridge losses are, from (9): An appropriate heatsink can now be designed, and the system can be implemented and validated.

VI. CONCLUSION
Variable Speed Drive (VSD) systems utilizing next-generation Wide-Bandgap (WBG) power semiconductors hold the promise of boosting the efficiency, power density, and adoption of electric motors to electrify manufacturing, logistics, and mobility. To realize fully the loss reduction and frequency increase benefits of SiC MOSFETs, however, the voltage slew rate applied to the motor must be limited to values such that the motor will not be damaged by partial discharge phenomena, surge voltages from cable reflections, or unequal distribution of the voltage across motor windings.
In this work, we evaluate the potential of an external Miller capacitor to limit the maximum dv DS /dt of a bridge-leg, and derive a detailed understanding of the switching behavior to derive analytical models -across switched current, gate resistance, and Miller capacitance -for the maximum dv DS /dt and switching losses during the turn-on and turn-off transitions. The dv DS /dt model and matching measurements show that the maximum slew rate occurs, for turn-on, at Zero-Current Switching (ZCS) and at elevated temperatures, while the turn-off dv DS /dt saturates after an analytical "kink current" is passed. The kink current derivation, which can be understood in the context of the current paths during switching, helps us arrive at a critical finding for the broader field: that switching losses in a bridge-leg are not quadratic with current (at least under limited dv DS /dt conditions), as long modelled, but are rather piecewise linear on current, with the second linear function starting at the kink current itself.
The dv DS /dt and loss models are validated on a SiC MOS-FET bridge-leg for a 10 kW 800 V DC-link VSD system with dv DS /dt limitations of 10 V/ns and 15 V/ns, where we find excellent matching between the model and the measured bridge-leg losses. The Miller capacitor-based technique achieves lower losses for the same maximum dv DS /dt than a gate resistor-only technique, highlighting the promise of realizing VSD systems with SiC MOSFETs that simultaneously achieve high efficiency, high power density, and limited voltage slew rates.