Analytical Calculation of the Residual ZVS Losses of TCM-Operated Single-Phase PFC Rectifiers

Triangular-current-mode (TCM) modulation guarantees zero-voltage-switching across the mains cycle in AC-DC power converters, eliminating hard-switching with a minor <inline-formula><tex-math notation="LaTeX">${\approx} {30}{\%}$</tex-math></inline-formula> penalty in conduction losses over the conventional continuous current mode (CCM) modulation scheme. TCM-operated converters, however, include a wide variation in both switching frequency and switched current across the mains cycle, complicating an analytical description of the key operating parameters to date. In this work, we derive an analytical description for the semiconductor bridge-leg losses in a TCM AC-DC converter, including the rms current and/or conduction losses, switching frequency, and switching losses. For SiC <sc>mosfet</sc>s, we introduce a new loss model for switching losses under zero-voltage-switching, which we call “residual ZVS losses”. These losses include the constant <inline-formula><tex-math notation="LaTeX">$C_\text{oss}$</tex-math></inline-formula> losses found in previous literature but must also add, we find, turn-off losses that occur at high switched currents. The existence and modeling of these turn-off losses, which are due to currents flowing through the Miller capacitance and raise the inner gate source voltage to the threshold level and accordingly limit the voltage slew rate, are validated on the <italic>IMZA65R027M1H</italic> 650V SiC <sc>mosfet</sc>. The complete loss model – and the promise of TCM for high power density and high efficiency – is validated on a 2.2 kW hardware bridge-leg demonstrator, which achieves a peak 99.6<inline-formula><tex-math notation="LaTeX">$\%$</tex-math></inline-formula> semiconductor efficiency at full load. The proposed, fully-analytical model predicts bridge-leg losses with only 12<inline-formula><tex-math notation="LaTeX">$\%$</tex-math></inline-formula> deviation at the nominal load, accurately including residual ZVS losses across load, modulation index, and external gate resistance.

and/or full-bridge arrangement of Fig. 1(a), the preferred topology for single-phase AC-DC power conversion today.
This topology utilizes one high-frequency switching leg, often implemented with SiC MOSFETs or GaN high-electronmobility transistors (HEMTs), and one line-frequency switching leg as an unfolder, typically implemented with SJ Si MOSFETs designed to minimize the conduction losses. Under continuous conduction mode (CCM) operation, also known as pulse width modulation (PWM), the high-frequency bridgeleg operates with a constant switching frequency and the duty cycle is set to sinusoidally shape the mains current and thus, define the output power. In this mode, the inductor current ripple is relatively small and, during each half-cycle, one turn-on transition in the high-frequency bridge-leg is hard while the other is soft under zero-voltage conditions (assuming an average output current much larger than the current necessary for soft-switching). In an effort to further improve the power density of these converters and avoid hard commutation of early MOSFETs (and later of Si SJ MOSFETs), however, designers have proposed new modulation schemes with full zero-voltage-switching (ZVS) [4], [5], including the widelyadopted triangular current mode (TCM) operation [6]- [9], which is shown in Fig. 1(b) and, in detail, in Fig. 1(c) with transition times from low-side to high-side t t,l-h and high-side to low-side t t,h-l .
TCM modulation confers significant benefits to the simultaneous pursuit of high efficiency and high power density. Firstly, and most importantly, the voltage across the power MOSFETs is reduced to zero before turn-on, eliminating the dominant switching loss component of the energy stored in the parasitic output capacitor, C oss . These switching losses are eliminated without requiring auxiliary circuits, as only the control of the main power circuit is modified, and this control can be implemented using modern digital signal processing devices (e.g. DSPs and FPGAs) and simple sensing circuits. When combined with novel wide-bandgap semiconductors that have both low on-resistance and an output capacitance that is both small and linear (relative to Si SJ MOSFETS), the higher rms current in TCM (≈ 15% higher than in CCM, resulting in ≈ 30% higher conduction losses) is easily tolerated and the switching frequency can be increased even further.
Under TCM modulation (and closely-related schema for soft-switching, including critical conduction and quasisquare-wave), AC-DC power converters with SiC MOSFETs and 400 V or 800 V DC-links have reached switching frequencies as high as 650 kHz [10], [11]. With GaN power semiconductors, designers have pushed switching frequencies into the MHz regime [12] (as high as 3 MHz [13], [14]) and simultaneously achieved efficiencies over 99% and power densities well over 100 Win −3 [15], [16]. Despite these demonstrated improvements and the widespread adoption of TCM schemes, though, there does not exist a straightforward method to calculate the power semiconductor losses in a TCM operated rectifier or inverter, eliminating the ability to optimize power semiconductor selection, thermal design, or switching frequency with limited effort.
In the paper, we seek to fill this critical literature gap, deriving an analytical power semiconductor loss calculation for TCM rectifiers even in the presence of (a) current-dependent ZVS losses and (b) the wide variation in switching frequency seen in TCM converters (Section II). The soft-switching (or C oss ) losses occur during the process of resonantly charging and discharging the parasitic output capacitor of the semiconductor and may be current-dependent [17]. These are combined with current-dependent turn-off losses in zero-voltageswitched converters, and we term this power dissipated as the "residual ZVS losses" that, with conduction losses, comprise the power semiconductor losses in a TCM converter. This loss model is proposed and validated with measurements on a next-generation 650 V SiC MOSFET in Section III. Section IV introduces the analytical expressions for the semiconductor losses and in Section V, we validate the analytical equations and loss model in a 2.2 kW PFC rectifier, a typical power level [12]- [14] used in, for example, data center applications and industrial automation (see specifications in Table 1). Finally, Section VI summarizes the key findings of the paper,

II. TCM OPERATING BEHAVIOR
To ascertain the power semiconductor losses in TCM, we first must describe the fundamental operating waveforms, preferably with analytical solutions. With the sought-after residual ZVS losses dependent on both frequency (soft-switching losses are the product of energy dissipated per cycle and frequency) and current (both soft-switching and turn-off losses depend on current), and both switching frequency ( f sw ) and switched current varying across the mains cycle, this description is fundamental to an accurate loss prediction.

A. ANALYTICAL DESCRIPTION
With a fundamental ac voltage of u ac (t ) =û ac sin(ω ac t ) with peakû ac and DC-link voltage U dc , the modulation index is: The fundamental current i ac is in phase with the voltage (i ac (t ) =î ac sin(ω ac t )), as is required for PFC operation. In TCM operation, an opposite-polarity current is selected to ensure ZVS during each half of the mains cycle, shown in Fig. 1(b-c) as I L-< 0 A for the positive half of the mains cycle. With a peak ac current ofî ac , the current bands during the positive half of the mains cycle (u ac ≥ 0 V) are: and during the negative half of the mains cycle (u ac < 0 V), the current bands are: With these bands defined, we introduce the "ZVS current ratio" as the ratio between the current selected to achieve ZVS and the fundamental peak current, or: The opposite polarity current, I L-< 0 A, must be selected such that ZVS is guaranteed across the full mains cycle. From the u − Zi diagram analysis in [8] that considers both the rectifier and the inverter cases, the characteristic impedance to guarantee ZVS is: where 2C oss,Q is the total charge-equivalent output capacitance of the bridge-leg semiconductors (C oss,Q,Th + C oss,Q,Tl = 2C oss,Q ). For rectifier operation, ZVS is guaranteed (even with I L-= 0 A) with M ≤ 0.5. At larger modulation indices, the minimum required turn-off current is required at the voltage peak (u ac =û ac ) as: For inverter operation, similarly, ZVS is guaranteed with M ≥ 0.5. The minimum current requirement occurs at the voltage zero-crossing (u ac = 0 V) as: which is the worst-case condition over the entire operating space and therefore defines the minimum required oppositepolarity current |I L-|.
Assuming the resonant transition is (a) much shorter than the on-time and off-time of the bridge-leg transistors and (b) the additional current from the resonant transition is small, we can make a triangular current approximation, and derive analytical equations for the switching frequency f sw across the mains cycle and the rms current through the inductor (I L,rms ) and the power devices I h,rms and I l,rms .
First, the on-and off-time for the high-side switch T h , during the positive half-cycle, are defined with with the bridge-leg inductance L, a mains angular frequency ω ac , and the time-dependent peak-to-peak current ripple i L (t ) = 2|I L-| + 2î ac | sin (ω ac t )|. The expressions for t on and t off have to be exchanged during the negative half-cycle due to the operation of the unfolder bridge-leg. The switching period definition T sw (t ) = t on (t ) + t off (t ) = 1/ f sw (t ), however, is true in both the positive and negative half-cycle and the switching frequency for both rectifier and inverter operation is: and the global maximum f sw,max occurs at ζ = | sin (ω ac t * )| = γ 2 + γ M − γ (see Fig. 2(a.i)) and is: With the triangular shape of the inductor current i L , the local inductor rms current i 2 L,rms = 1 T sw T sw 0 i 2 L (t )dt over a switching period T sw = 1/ f sw is determined by the positive and negative current limits as: which can also be written as i 2 L,rms (t ) = i 2 h,rms (t ) + i 2 l,rms (t ), due to the triangular current approximation. The instantaneous (local) rms current across the mains cycle is shown in Fig 2( Therefore, we can find the local high-side and low-side switch rms currents, i h,rms and i l,rms , which determine the conduction losses. These are given as: with the instantaneous duty cycle d (t ) = uā n (t )/U dc of: These local rms values can then be used to calculate the global rms currents, as, for example, For γ = 0, the inductor rms current is I L,rms =î ac 2 3 , for 33% more conduction losses than in CCM (neglecting any ripple).
The unfolder operation ensures symmetrical operation in the high-frequency bridge-leg, allowing for a simple determination of the switch global rms currents as I h,rms = I l,rms = 1 √ 2 I L,rms .

B. SIMULATION VALIDATION
The analytical expressions for the frequency f sw and the various currents, including I L,rms , are compared to the results from GeckoCIRCUIT [18] numerical simulations in Fig. 2 to validate the proposed equations. The simulations are carried out with the specifications of Table 1 with U ac = 230 V rms , an assumed C oss,Q = 370 pF of each power transistor, and a constant turn-off current of I L-= −4 A to ensure full ZVS (as analyzed later, in Section V). Firstly, the analytically calculated and simulated local switching frequency f sw (Fig. 2(a.i)) and transistor local rms currents i h,rms and i l,rms and inductor rms current i L,rms ( Fig. 2(b.i)) are compared over one mains cycle (T ac = 1/ f ac ) for an ac voltage of 230 V rms and a maximal power of 2.2 kW. The agreement between the derived analytical expressions and the numerical simulations is very good, with small deviations that are then further explored across the operating space.
In Fig. 2(a.ii), the analytically-calculated maximum switching frequency across ac voltage (including the considered application range from 120 V rms to 230 V rms ) and output power is shown, varying between 100 kHz and 1100 kHz. The maximum switching frequency occurs at no-load operation. This prediction is then compared to numerical simulations in Fig. 2(a.iii). Because the calculation ignores the resonant transition times, the calculated switching frequency is always higher than the simulated switching frequency. Across the operating space, though, the absolute error remains below 6% for full-load operation and below 16% even at the worst-case of zero-load operation.
Similarly, Fig. 2(b.ii) shows the calculated inductor rms current over the operating area, with the minimum rms current (I L,rms,min = |I L-|/ √ 3 = 2.3 A) corresponding to no-load operation, and Fig. 2(b.iii) shows the error between this calculation and the simulated current. Again, because the analytical equations ignore the resonant transition times (where inductor current increases), the analytical prediction is always smaller than the current values obtained from simulation. However, since the resonant transitions are only a small fraction of the total period, the error at full load is smaller than 1%. The error increases with lower power levels but never exceeds 14%.
Overall, the proposed analytical expressions accurately describe the key parameters and waveforms in TCM operation, and we can confidently apply them to determine the total power semiconductor losses. First, though, the remaining switching losses that occur during ZVS operation must be determined, and we combine the well-known soft-switching (or C oss ) losses [17], [19]- [28] with turn-off losses to describe the total switching losses under ZVS, which we term "residual ZVS losses."

III. RESIDUAL ZVS LOSSES
Soft-switching losses occur during the resonant chargedischarge process of the parasitic output capacitance in a power semiconductor, and are well-characterized in a breadth of device types [19]- [28]. In SiC MOSFETs, in particular, recent literature has found that these soft-switching losses per cycle are independent of du ds /dt and are therefore constant with switched current [17], [29]. In ZVS implementations, however -like the TCM topology here -the measured "switching" losses are higher-than-expected and increase with current, necessitating the inclusion of an additional switching loss mechanism beyond C oss losses. While comprehensive analytical models of switching behavior have been previously given (for example, [30], [31]), we focus on a minimumcomplexity equivalent circuit (and resulting equations) to ascertain the core driver of these residual ZVS losses. Fig. 3(a) shows the equivalent circuit present during the turn-off transition of the low-side switch (T l in Fig. 1(a)) and the corresponding waveforms are shown in Fig. 3(b), assuming the inductor current is flowing during the whole switching transition in the indicated direction and that the dead-time is large enough to guarantee zero-voltage turn-on of T h ) for complete ZVS [5]. C ds represents the equivalent output capacitance between D and S, including the drain-source capacitance of T l , the output capacitance of T h (only indicated with a free-wheeling diode to which I sw commutates) and any additional parasitic capacitances, i.e. C ds =C ds,Tl +C oss,Th + C par . While this turn-off transition is typically ignored when considering the losses in unipolar power semiconductors, there is an unmistakable remnant voltage-current overlap at enhanced load current during this time in ZVS converters that may result in large and non-negligible losses [32], as shown in Fig. 3

A. TURN-OFF TRANSITION ANALYSIS
This turn-off transition is now analyzed in detail to ascertain the source, mechanisms, and dependencies of these residual ZVS losses. During turn-off, the switched current I sw is taken as constant, and commutates from the channel (i ch ) to charge the output capacitor (C ds with current i Cds ) and the Miller capacitor (C gd with current i Cgd ). As the switched current I sw increases, the switching voltage transition is expected to occur more rapidly due to higher capacitor charging current, which increases the voltage slew of the transition du ds /dt = U dc /t r . This indeed occurs -to a point.
As the switched current I sw increases, i Cgd also increases with the current divider C gd /(C ds + C gd ) between the gate-drain and equivalent drain-source capacitance. The gate current is assumed to be determined by the gate drive circuit as i g = (u gs,i + |u g,n |)/R g , with the inner gate-source voltage u gs,i , the negative gate driver voltage magnitude u g,n = |u g,n | ≥ 0 V, and the total gate resistance R g = R g,int + R g,ext . As long as the current through the Miller capacitance i Cgd is smaller than the gate drive current i g , i Cgd < i g , the gate-source capacitance is discharged and the channel is closed before the drain-source voltage u ds starts rising significantly, cf. Fig. 3(b). This case results in ideal ZVS with no turn-off losses beyond C oss and gating losses, and a voltage slew rate du ds /dt that is proportional to I sw : with C eff = 2C oss,Q + C par . During this transition, the following order of operations occurs, assuming that in the active region the relationship between the gate-source voltage and the channel current is linear and defined by the transconductance g. Firstly, the gate-source capacitance is discharged to some level (with no effect on the power circuit), and once the (inner) gate-source voltage u gs,i reaches this level, u gs,i = u th + I sw · g, the channel current starts decreasing, a decay that we assume to be linearly proportional to the difference of u gs,i and the threshold voltage u th (Fig. 3(b)). With the high-side diode still blocking, the switched current I sw that no longer flows through the channel (i ch ) must flow through the capacitances C ds + C gd , building up the drain-source voltage quadratically (for a linear decrease in channel current). With a fast change in channel current, the voltage-current overlap during this time period can be (and has been, in prior art) neglected. Once the channel current has fully commutated to the output capacitcances, the gate-drain current is determined by the voltage slew and the Miller capacitance, and the gate-source capacitor continues to discharge. When i Cgd < i g , the discharge of the gate-source capacitance continues at a reduced slope, and once the voltage transition has finished, the full gate current again discharges the gate-source capacitance and the slope increases until the transition is completed.
As I sw is further increased, we first encounter the corner case i Cgd = i g with u gs,i = u th , (Fig. 3(c)), which we call the "kink current" I k : In this case, the switched current I sw = I k is again split between C ds and C gd , but the current through the Miller capacitance from the voltage slew du ds /dt equals the gate driver current, i.e. i Cgd = i g . Therefore, u gs,i remains at the threshold voltage u th and no charge is removed from the gate-source capacitor (see Fig. 3(c)). As the gate-drain current is defined by the gate driver current, i Cgd = i g ≈ (u th + |u g,n |)/R g , the slew rate at the kink current is: If I sw is increased beyond the kink current I k , the gatesource capacitance is discharged only to a voltage that remains slightly higher than the threshold voltage u th (Fig. 3(d)), and the channel remains turned on and conducts the switched current (to reiterate, taken as constant) that cannot flow through the combination of the gate-source and drain-source capacitances. This causes voltage-current overlap losses, which are deemed "residual ZVS losses" here. With the gate-source voltage above the threshold voltage, the continued channel current slightly expedites the voltage transition, resulting in a voltage slew rate of: with the slope s dependent on the MOSFET transconductance g as s = I k g(u th +|u g,n |) . As soon as the voltage transient is completed, the gatesource voltage drops, the device turns off fully, the remaining channel current commutates to the high-side device, and the transition is completed.

B. EXPERIMENTAL VALIDATION OF TURN-OFF TRANSITION WAVEFORMS
To validate the proposed model and conceptual waveforms of Fig. 3, we measure the turn-off transition across drain currents of a 650 V, 27 m 4-pin SiC MOSFET from Infineon IMZA65R027M1H operated with |u g,n | = 3 V and R g,ext = 24.3 (a relatively large gate resistance is selected for better visualization) in a half-bridge setup. The waveforms of the drain-source voltage u ds , the gate-source voltage u gs (measured with the Tektronix IsoVu [33]), and the gate current i g (measured indirectly via the voltage drop of the external gate resistor) are shown during the turn-off transition in Fig. 4 and in Fig. 5. The saturation of the du ds /dt is shown in Fig. 4, where the measured drain-source voltage during the turn-off transition (solid lines) is compared to a linear-scaled version of the 2.5 A transition (dashed lines, which correspond to an ideal ZVS transition), an operating point well below the kink current of 6.4 A (calculated using the fitted model parameters of Table 2, as detailed below). The voltage slew rate clearly  shows the expected saturation effect for currents above the kink current.
The internal threshold voltage u th , the quantity that determines device behavior, can be translated into an externallymeasurable quantity u th,ext by assuming a resistive voltage divider in the gate path between the external R g,ext and the device-internal gate resistance R g,int , and is given as: For the given operating conditions, this results in u th,ext = 5.6 V, a threshold that is highlighted in Fig. 5 and consistent with the level at which the behavior change of the MOSFET occurs. Even with the non-constant Miller region of SiC MOSFETs [34], [35], the measurements align well with the proposed waveforms of Fig. 3. Particularly, the increased gate-source voltages and gate currents at higher switched currents indicate the predicted presence of a channel current during the turn-off transition.
In examining the measurements of Fig. 4 and Fig. 5, we also observe ringing in all measured waveforms of u ds , u gs , and i g for switched currents above the kink current. This is attributed to the remnant channel current commutating to the high-side switch very quickly, exciting the parasitic power loop inductance and causing the observed ringing. A small fraction of this inductance is coupled with the gate-to-kelvinsource connection, and even this small ringing is seen in the gate-source voltage measurement of Fig. 5.

C. RESIDUAL ZVS LOSS MODELLING
Because the total switched current is constant during the turnoff period, the current that cannot flow through C gd (and C ds ) must flow through the channel as leading to an energy loss due to the voltage-current overlap for currents I sw ≥ I k . The total energy loss in the zero-voltageswitched power semiconductor, then, can be written as: where E 0 represents the constant C oss losses in SiC MOSFETs [17] plus the gating losses, and is therefore a currentindependent, device-specific term. The factor k = 1 2 U 2 dc / du ds dt includes the voltage slope du ds dt , which, according to Eqn. (19), is dependent on the switched current. Assuming s ≈ 0 as an approximation, the voltage slope is constant, du ds dt = du ds dt | k = I k C eff (for I sw ≥ I k ) and we can introduce a current-independent approximation of k, To fit and validate the model, further measurements are conducted on the previously-introduced half-bridge setup. Double-pulse experiments are conducted for three additional gate resistors (R g,ext = 0 , 3.3 , 5.1 ) and two turn-off voltages (|u g,n | = 0 V, 3 V), with the results shown in Fig. 6. The du ds /dt measurements are also shown for R g,ext = 24.3 and |u g,n | = 3 V for completeness, as it verifies the kink current model even for large gate resistors. Voltage slew rates du ds /dt are evaluated between 10% and 90%.
Based only on the du ds /dt measurements, the critical device parameters of Table 2 can be estimated -from which the kink current I k and the coefficient k can be simply calculated. The maximum voltage slew rate results in the C eff and s parameters of C eff = 646 pF (which corresponds to twice the charge equivalent output capacitance between 40 V and 360 V, i.e. 2 × 320 pF) and s is considered to be 0.2 for small gate resistors, i.e. for R g,ext < 6 . For larger resistance values (e.g. R g,ext = 24.3 ), the value of s drops, for example to 0.1. The remaining parameters are derived based on estimated kink currents and result in 1 + C ds C gd = 18, u th = 7 V (which corresponds to the datasheet value of the extracted threshold voltage from the typical transfer characteristic), and R g,int = 4 , which is slightly larger than that specified in the datasheet (R g,int = 3 ).
The resulting kink currents for R g,ext = 0 , 3.3 , 5.1 , and 24.3 according to the proposed model are, respectively, I k = 29.3 A, 17.3 A, 14.0 A for |u g,n | = 0 V and I k = 31.6 A, 24.7 A, 20.0 A and 6.4 A for |u g,n | = 3 V, with the latter set highlighted in Fig. 6. We note here that for the combination of large negative gate drive voltage magnitudes and small gate resistors, a gate drive current limit of approximately 1.7 A must be included in the analysis due to the limited gate driver fall time (10 ns), which is similar to the corresponding voltage rise/fall time of the SiC MOSFET t R = 8 ns (at 50 Vns −1 , cf. Fig. 6). Finally, the switching losses under ZVS are calorimetrically measured [36] and shown in Fig. 7. The negative gate driver voltage magnitude is |u g,n | = 1 V during the measurements (due to a voltage drop within the gate driver circuitry that occurs when switching the devices between 500 kHz-1 MHz), which leads to E 0 = 2.4 µJ.
The kink currents and resulting voltage slew rates (for s = 0.2) and the results of the residual ZVS loss model are shown overlaid in both Fig. 6 and Fig. 7, with the calculations relying on the fitted model parameters given in Table 2. The largest deviation between model and measurements appears at the kink current. This occurs because the model does not include the non-linearity of C dg , which is largest at u ds = 0 V, and the voltage slew rate limitation occurs at lower currents than specified by the kink current.
Even with these approximations and simplifications -using only voltage slope measurements, ignoring temperature effects, and neglecting the non-linearities of the respective capacitances with voltage -the model and measurements agree closely, with the loss model predicting the current (I k at which the losses start to increase beyond the constant C oss losses) for all three gate resistors. The maximum voltage slew rate and existence of an asymptote is also well-predicted by the proposed model, as shown in Fig. 6. The key results are given in the top half of Table 3 for the measured device.
As an important aside, we note that this analysis clearly indicates the need for high-performance gate drive solutions with low gate resistances and large negative gate driver voltage magnitudes, which push out the kink current. The only downside of an increased negative gate driver voltage is the increase in gate drive losses, but a voltage increase from |u g,n | = 0 V to 3 V only increases the fixed gating energy loss from 1.13 µJ to 1.45 µJ per cycle. This energy loss increase of 0.32 µJ is negligible compared to the constant part of E 0 = E G + 5%E oss = 1.13 µJ + 1.11 µJ = 2.24 µJ (considering a C oss -related energy loss of only 5% E oss [17]). This  clearly motivates the selection of the highest-possible negative gate driver voltage magnitude, which is typically limited by the maximum rating of the device. Finally, while this derived model predicts the behavior accurately, the loss estimation is difficult to implement analytically due to the discontinuity at I k . The residual ZVS losses can, instead, be approximated by a quadratic loss model [36] as (for I sw > 0 A): where a, b, and c are switch-dependent switching loss coefficients and I sw is the switched current. These fittings are overlaid on the measured losses in Fig. 7 with the coefficients of Table 3. The coefficient a is selected to be equal to E 0 (which also includes a fixed gating loss of 1.3 µJ per cycle). Unlike the discontinuous loss model, these coefficients have no physical meaning (e.g. b < 0) but still approximate the measured losses under ZVS accurately from 10 A to 50 A of switched current. In Appendix A, the switching characteristics of a SiC MOSFET from a different voltage class and manufacturer (1.2 kV, 16 m 4-pin SiC MOSFET C3M0016120K from Wolfspeed) are measured, further validating the model's predictions of voltage slew rate, kink current, and soft-switching losses. We find, then, that the complete switching losses under ZVS across current are predicted by the proposed model. The residual ZVS losses, further, can be accurately approximated with a continuous quadratic loss function, and we can use this to analytically determine the total power semiconductor losses in the TCM operated converter-of-interest.

IV. POWER SEMICONDUCTOR LOSSES IN TCM
The total power semiconductor losses in a TCM converter, then, comprise the conduction losses -based on the rms currents derived in Section II -and the switching loss model of the previous section, where residual ZVS losses were determined as a function of current. The local conduction losses are: which are mainly determined by the local rms currents of Eqn. (12) and Eqn. (13). The local switching losses are the product of the switching frequency (determined in Eqn. (9) and validated in Fig. 2(a)) and the energy loss, which is a function of the turn-off current: Again, the analytical predictions are compared to the results from GeckoCIRCUIT numerical simulations (with the quadratic fit loss model), this time for the switching losses. Fig. 8(a) shows the comparison of the local switching losses over one mains cycle T ac = 1/ f ac for an external gate resistor of R g,ext = 3.3 . Again, we find an accurate proposed model of residual ZVS losses and, further, show the accuracy of the quadratic loss approximation. In Fig. 8(b), the switching losses are shown over the complete operating area of modulation index and load, and we highlight the current-dependency of the switching losses (which would not be included in the C oss -loss-only model). Fig. 8(c) shows the relative error between the calculated and predicted switching losses, where we find excellent matching that degrades somewhat at light loads due to the error in switching frequency prediction (see Fig. 2(a.iii)).
With each loss component determined analytically in previous sections of the paper, we can now find the total conduction and switching losses across the considered modulation range, FIGURE 9. Analytically-calculated (a) conduction P cond , (b) switching P sw , and (c) total semiconductor losses P semi = P cond + P sw for the power semiconductor bridge-leg under the specifications given in Table 1. Evaluated for (i) R g,ext = 0 and (ii) R g,ext = 3.3 to highlight the importance of the residual ZVS losses in the bridge-leg performance of TCM converters.
load, and turn-off current for ZVS. The average conduction losses are: The relative conduction losses with respect to the output power P o = MU dcîac /2, result in P cond P o = 2 3 R ds MU dc (2 + 4 π γ + γ 2 )î ac and increase with the current level.
The average switching losses of the bridge-leg are P sw = 1 T ac T ac 0 p h,sw (t ) + p l,sw (t )dt leading to with the average energy loss E sw as function of M,î ac , and γ : The relative switching losses are obtained by with E L,pk = Lî 2 ac /2. Finally, the total semiconductor losses are P semi = P cond + P sw .
These analytical switching and conduction loss expressions are evaluated across modulation index M and output power in Fig. 9 for a TCM converter of Table 1 using the IMZA65R027M1H SiC MOSFET with two different values of external gate resistors, (i) 0 and (ii) 3.3 . Conduction losses are shown in Fig. 9(a), which, as expected, do not change between the gate resistance values. Switching losses ( Fig. 9(b)) -even under ZVS, we must recall -significantly increase at the higher gate resistance, as I k is lowered and the residual ZVS losses climb rapidly with current. The R g,ext = 3.3 , case, however, sees the maximum du ds /dt reduced from 50 Vns −1 to 35 Vns −1 , cf. Fig. 6, which may be beneficial for EMI performance.
In the next section, the total loss predictions of Fig. 9(c)and, therefore, the proposed model and analytical expressions -are validated in a hardware prototype.

V. EXPERIMENTAL VERIFICATION
The constructed hardware prototype to validate the theoretical results is shown in Fig. 10, with the filter implemented externally for flexibility. The 2.2 kW hardware prototype includes both a high-frequency (IMZA65R027M1H SiC MOSFETs) and an unfolder bridge-leg (UF3SC065007K4S SiC MOSFETs), DC-link capacitors, and the required sensor suite for control and monitoring, including a zero-crossing detection (ZCD) circuit [1] that obviates the need for a high-bandwidth current sensor.
The gate loop inductance is minimized through optimal placement and routing to support operation with a 0 external gate resistor. A high-performance gate driver, TI's UCC27531, ensures the lowest possible residual ZVS losses through high-current-sink capabilities of up to 5 A and fast rise/fall times in the range of 10 ns, and we operate the gate drive at the maximum recommended positive gate voltage (+18 V) to minimize on-resistance and close to the absolute maximum of the negative gate voltage (−2 V), although during operation the negative drive voltage is measured at −1 V and this value is used for the following loss predictions.  Fig. 1(a)), to validate the proposed analytical model of bridge-leg losses, switching frequency, and rms currents in a TCM converter. The hardware demonstrator includes both a high-frequency (realized with IMZA65R027M1H SiC MOSFETs) and an unfolder bridge-leg that can be realized with e.g., UF3SC065007K4S SiC MOSFETs. A zero-crossing detection (ZCD) circuit and the ZYNQ System-on-Chip are used for sensing and to ensure the inductor current is controlled to the calculated limits. The filter is implemented externally for extensibility and reconfiguration in testing.
With a charge-equivalent output capacitance of C oss,Q,Th = C oss,Q,Tl = 370 pF at U ds = 400 V for the IMZA65R027M1H SiC MOSFETs, the worst-case turn-off current requirements are 2.6 A at 230 V rms for rectifier operation (given by Eqn. (6)) and 3.2 A at zero output voltage for inverter operation (given by Eqn. (7)). The ZCD, further, requires a small opposite-direction current for correct operation, resulting in 3.96 A minimum current when the 140 ns circuit delay (including the 20 ns switch turn-on time) is considered. To achieve ZVS under all conditions and ensure correct operation of the ZCD circuit, then, a turn-off current of |I L-| = 4 A is selected.
Because it is only switched twice per line cycle, the unfolder bridge-leg only incurs conduction losses, and the lowest R ds devices with a sufficient voltage rating can be selected, i.e., the UF3SC065007K4S SiC cascode MOSFET from United SiC (11.7 m at 125°C). At the worst-case operating point (full power at 120 V rms ), the inductor rms current is 23 A and the unfolder bridge-leg losses are 6.2 W. Fig. 11 shows the measured oscilloscope waveforms of the hardware prototype of phase voltage (u ac ), phase current (i ac ), and inductor current (i L ). For all measured waveforms, an 11.5 µH air-core inductor is used for the filter inductor, with a 3 µF filter capacitor used for the 230 V rms measurement ( Fig. 11(a)) and an 11 µF filter capacitor used for the 120 V rms one ( Fig. 11(b)). These waveforms confirm correct operation of the hardware prototype under TCM modulation and we move to validate the proposed loss models.
Semiconductor bridge-leg losses are calculated and measured for 230 V rms and 120 V rms with 0 and 3.3 external gate resistors. The dead time is adjusted to minimize the diode conduction time. As Fig. 12 shows, the proposed fully-analytical model accurately predicts the measured semiconductor losses for the TCM hardware prototype. For all operating conditions, bridge-leg losses are predicted within 1 W at full load and within 0.9 W at 40% load. The maximum prediction error never exceeds 14% and is below 3% for most of the operating space. The worst-case partial load prediction error occurs at 40% load and R g,ext = 0 , with an 0.88 W underestimation (13.6%) for the 120 V rms condition. At full load, the worst-case prediction error occurs with R g,ext = 3.3 and 230 V rms , with an underestimation of 0.99 W (11.9%). These small differences are attributed to the resonant transition times, which are neglected in the analytical model, and the remaining diode conduction losses.
Further, the E 0 losses (C oss -related losses plus gating losses) are indicated in Fig. 12 to separate the contributions of these losses, which are constant with current, from the residual ZVS losses identified in this paper. At light load, the E 0 losses comprise nearly all of the semiconductor losses, while towards the nominal load -the operating point that typically drives the design of the cooling system -the residual ZVS losses must be considered for an accurate loss estimation. More tangibly, with R g,ext = 0 and 230 V rms , E 0 losses are 98.9% of switching losses at no load but only 48.7% at full load. Similarly, at R g,ext = 3.3 and 120 V rms , E 0 losses are 94.5% of switching losses at no load but only 9.3% at full load. The hardware prototype achieves a peak semiconductor efficiency of 99.6% at 230 V rms at full load and 99.3% at 120 V rms at 40% load. At low power levels, we see that the semiconductor losses rise due to the higher switching frequency, an increase that could be mitigated by increasing |I L-| (which would increase conduction losses but lower total losses).
The hardware prototype demonstrates the exceptional efficiencies achievable in AC-DC converters operating with TCM modulation, but, more importantly, proves the validity and efficacy of the proposed model to accurately predict bridge-leg losses with a fully-analytical solution.

VI. CONCLUSION
Triangular-current-mode (TCM) operation of AC-DC converters eliminates hard-switching losses with a rms current increase of only ≈ 15% (≈ 30% increase of conduction losses) over continuous current mode (CCM) modulation, unlocking power-dense and highly-efficient inversion and rectification for this key power processing block. With switched current and switching frequency variation across the mains cycle, however, an analytical description of the bridge-leg losses has eluded the field.
Literature has diverged on the current-dependence of softswitching losses in SiC MOSFETs (compare [17] to [19] and [23]). With the introduction here of the residual losses that occur even under zero-voltage-switching above a threshold current (the "kink current"), this work unifies the field, finding constant C oss -only losses at low switched currents and currentdependent soft-switching losses above the kink current. It is interesting to note that recent work on GaN HEMTs has found a similar switching loss dependence -again under ZVS conditions on the negative gate-driver voltage in a different class of power devices [37].
In the end, the simple and accurate analytical descriptions of switching frequency, rms currents, and semiconductor losses under TCM operation open the opportunity for optimized converters without time-consuming numerical simulations, a powerful and extensive tool for the next generation of AC-DC power conversion.

ACKNOWLEDGMENT
The authors would like to thank N. Kleynhans for carrying out the experimental du ds /dt analyses and switching loss measurements in great detail.

APPENDIX A SWITCHING LOSS MEASUREMENTS ON A 1.2 kV, 16 m 4-PIN SIC MOSFET
To verify the model across different blocking voltage classes of SiC MOSFETs, we also measure the switching losses on the 1.2 kV, 16 m 4-pin SiC MOSFET C3M0016120K from Wolfspeed. An identical procedure to that outlined in Section III is repeated, with du ds /dt measurements using the double-pulse test for two external gate resistors (here, (R g,ext = 0 and R g,ext = 5.1 ) and two turn-off voltages (here, |u g,n | = 0 V and |u g,n | = 5 V). The results are shown in Fig. 13 and Fig. 14.
We use only the du ds /dt measurements of Fig. 13 to fit the model parameters, which are reported in Table 4. The parameters C eff and s result directly in C eff = 666 pF (which corresponds to twice the charge equivalent output capacitance between 80 V and 720 V, or 2 × 313 pF), with s taken as s = 0.2 for simplicity. The remaining parameters are derived based on the estimated kink currents, resulting in 1 + C ds C gd = 19.5,   u th = 7 V (which corresponds to the datasheet value of the extracted threshold voltage of 6.5 V for the given typical transfer characteristic), and R g,int = 7 , which is larger than specified in the datasheet (2.6 ). The resulting kink currents are I k = 19.3 A (R g,ext = 0 ) and 11.5 A (R g,ext = 5.1 ) for u g,n = 0 V and 33.4 A (R g,ext = 0 ) and 19.3 A (R g,ext = 5.1 ) for u g,n = 5 V, as shown in Fig. 13.
Switching losses are again measured calorimetrically [36] with the two external gate resistors. During the experiments, the negative gate driver voltage magnitude was measured at |u g,n | = 4 V (due to a voltage drop within the gate drive, which also occurs during in-situ operation), leading to  Fig. 14, and the key results are given in Table 5. Again, the proposed model accurately predicts the maximum voltage slew rate, the existence of an asymptote, the current at which switching losses increase rapidly above E 0 , and, in the end, the switching losses for the 1.2 kV SiC MOSFET.
JOHANN W. KOLAR (Fellow, IEEE) received the M.Sc. degree in industrial electronics and control engineering and the Ph.D. degree in electrical engineering (summa cum laude/promotio sub auspiciis praesidentis rei publicae) from the Vienna University of Technology, Vienna, Austria, in 1997 and 1999, respectively. Since 1984, he has been an independent Researcher and International Consultant in close collaboration with the Vienna University of Technology, in the fields of power electronics, industrial electronics, and high-performance drive systems. He is currently a Full Professor and the Head with the Power Electronic Systems Laboratory, Swiss Federal Institute of Technology, ETH Zurich, Zurich, Switzerland. He has proposed numerous novel PWM converter topologies, modulation and control concepts, and multiobjective power electronics design procedures, and has supervised more than 75 Ph.D. students. He has authored or coauthored more than 900 scientific papers in international journals and conference proceedings, four book chapters, and has filed more than 190 patents. His current research interests include ultracompact and ultra-efficient SiC and GaN converter systems, ANN-based power electronics components and systems design, solid-state transformers, power supplies on chip, ultra-high speed and ultra-light weight drives, bearingless motors, and energy harvesting. He has presented more than 30  GERALD DEBOY (Senior Member, IEEE) received the M.Sc. and Ph.D. degrees in physics from the Technical University Munich, Munich, Germany, in 1991 and 1996, respectively. In 1994, he joined Infineon Technologies AG, Neubiberg, Germany, and is currently heading a group looking into opportunities and requirements for emerging applications. He has authored and coauthored more than 70 papers in national and international journals, including contributions to three student text books. He holds more than 60 granted international patents and has more applications pending.